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Sample records for access memory sram

  1. Access time optimization of SRAM memory with statistical yield constraint

    NARCIS (Netherlands)

    Doorn, T.S.; Maten, ter E.J.W.; Di Bucchianico, A.; Beelen, T.G.J.; Janssen, H.H.J.M.

    2012-01-01

    A product may fail when design parameters are subject to large deviations. To guarantee yield one likes to determine bounds on the parameter range such that the fail probability P_fail is small. For Static Random Access Memory (SRAM) characteristics like Static Noise Margin and Read Current,

  2. Low power and reliable SRAM memory cell and array design

    CERN Document Server

    Ishibashi, Koichiro

    2011-01-01

    Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.

  3. Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory

    Directory of Open Access Journals (Sweden)

    Luís Vitório Cargnini

    2014-08-01

    Full Text Available Static random access memory (SRAM is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

  4. An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM

    International Nuclear Information System (INIS)

    Weaver, H.T.; Axness, C.L.; McBrayer, J.D.; Browning, J.S.; Fu, J.S.; Ochoa, A. Jr.; Koga, R.

    1987-01-01

    A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively - primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM

  5. DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

    Directory of Open Access Journals (Sweden)

    A. KISHORE KUMAR

    2014-12-01

    Full Text Available Static Random Access Memory (SRAM has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST logic is proposed. The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability. The proposed design is simulated using 0.18 µm process technology and compared with conventional 6T cell. Simulation results show that the proposed memory cell achieves significant improvements in power consumption during read and write operations. It can retain data at a lower supply voltage of 300 mV. This new type of SRAM design can operate at a maximum frequency of 1 GHz at 1 V supply voltage. These qualities of the proposed design make it a best choice for high performance memory chips in the semiconductor industry where reliability and power consumption are of great interest.

  6. Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions

    Directory of Open Access Journals (Sweden)

    Chip-Hong Chang

    2016-08-01

    Full Text Available Static Random Access Memory (SRAM has recently been developed into a physical unclonable function (PUF for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS 45 nm bulk Predictive Technology Model.

  7. The manufacture of system for testing static random access memory radiation effect

    International Nuclear Information System (INIS)

    Chen Rui; Yang Chen

    2008-01-01

    Space radiation effects will lead to single event upset, event latch up and other phenomena in SRAM devices. This paper introduces the hardware, software composition and related testing technology of SRAM radiation effect testing device. Through to the SRAM chip current detection and power protection, it has solved the SRAM chip damage question in the SRAM experiment. It has accessed to the expected experimental data by using the device in different source of radiation conducted on SRAM Experimental study of radiation effects. It provides important references in the assessment of operational life and reinforcement of the memory carried in the satellites. (authors)

  8. Analysis of SEL on Commercial SRAM Memories and Mixed-Field Characterization of a Latchup Detection Circuit for LEO Space Applications

    Science.gov (United States)

    Secondo, R.; Alía, R. Garcia; Peronnard, P.; Brugger, M.; Masi, A.; Danzeca, S.; Merlenghi, A.; Vaillé, J.-R.; Dusseau, L.

    2017-08-01

    A single event latchup (SEL) experiment based on commercial static random access memory (SRAM) memories has recently been proposed in the framework of the European Organization for Nuclear Research (CERN) Latchup Experiment and Student Satellite nanosatellite low Earth orbit (LEO) space mission. SEL characterization of three commercial SRAM memories has been carried out at the Paul Scherrer Institut (PSI) facility, using monoenergetic focused proton beams and different acquisition setups. The best target candidate was selected and a circuit for SEL detection has been proposed and tested at CERN, in the CERN High Energy AcceleRator Mixed-field facility (CHARM). Experimental results were carried out at test locations representative of the LEO environment, thus providing a full characterization of the SRAM cross sections, together with the analysis of the single-event effect and total ionizing dose of the latchup detection circuit in relation to the particle spectra expected during mission. The setups used for SEL monitoring are described, and details of the proposed circuit components and topology are presented. Experimental results obtained both at PSI and at CHARM facilities are discussed.

  9. Design of ternary clocked adiabatic static random access memory

    International Nuclear Information System (INIS)

    Wang Pengjun; Mei Fengna

    2011-01-01

    Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions. (semiconductor integrated circuits)

  10. Design of ternary clocked adiabatic static random access memory

    Science.gov (United States)

    Pengjun, Wang; Fengna, Mei

    2011-10-01

    Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

  11. SEU measurements on HFETS and HFET SRAMS

    International Nuclear Information System (INIS)

    Remke, R.L.; Witmer, S.B.; Jones, S.D.F.; Barber, F.E.; Flesner, L.D.; O'Brien, M.E.

    1989-01-01

    The single event upset (SEU) response of n + -AlGaAs/GaAs heterostructure field effect transistors(HFETs--also known as SDHTs, HEMTs, MODFETs, and TEGFETs) and HFET static random access memories (SRAMs) was evaluated by measuring their response to focused electron pulses. Initially, focused electron beam pulses were used to measure and model HFET drain and gate SEU responses. Circuit simulations using these SEU models predicted that an HFET memory is most vulnerable to a single particle event in the area between the drain and the source (drain hit) of the OFF pull down HFET. Subsequent testing of an HFET SRAM cell confirmed this prediction. The authors discuss how these first SEU evaluations of HFETs and HFET memories show that measurements on individual HFETs and circuit simulations of SEU hits may be used to predict the SEU response of HFET memories

  12. Security strategy of powered-off SRAM for resisting physical attack to data remanence

    International Nuclear Information System (INIS)

    Yu Kai; Zou Xuecheng; Yu Guoyi; Wang Weixu

    2009-01-01

    This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

  13. Low-energy neutron-induced single-event upsets in static random access memory

    International Nuclear Information System (INIS)

    Guo Xiaoqiang; Guo Hongxia; Wang Guizhen; Ling Dongsheng; Chen Wei; Bai Xiaoyan; Yang Shanchao; Liu Yan

    2009-01-01

    The visual analysis method of data process was provided for neutron-induced single-event upset(SEU) in static random access memory(SRAM). The SEU effects of six CMOS SRAMs with different feature size(from 0.13 μm to 1.50 μm) were studied. The SEU experiments were performed using the neutron radiation environment at Xi'an pulsed reactor. And the dependence of low-energy neutron-induced SEU cross section on SRAM's feature size was given. The results indicate that the decreased critical charge is the dominant factor for the increase of single event effect sensitivity of SRAM devices with decreased feature size. Small-sized SRAM devices are more sensitive than large-sized ones to single event effect induced by low-energy neutrons. (authors)

  14. Experimental study on reactor neutron induced effect of deep sub-micron CMOS static random access memory

    International Nuclear Information System (INIS)

    Yang Shanchao; Guo Xiaoqiang; Lin Dongsheng; Chen Wei; Li Ruibin; Bai Xiaoyan; Wang Guizhen

    2010-01-01

    This paper investigates neutron irradiation effects of two kinds of commercial CMOS SRAM (static random access memory), of which one is 4M memory with the feature size of 0.25 μm and the other is 16M memory with the feature size of 0.13 μm. We designed a memory testing system of irradiation effects and performed the neutron irradiation experiment using the Xi'an Pulse Reactor. The upset of two kinds of memory cells did not present a threshold versus the increase of neutron fluence. The results showed that deep sub-micron SRAM behaved single-event upset (SEU) effect in neutron irradiation environment. The SEU effect of SRAM with smaller size and higher integrated level tends to upset is considered to be related to the reduction of the device feature size, and fewer charges for upsets of the memory cell also lead to the SEU effect. (authors)

  15. Experimental investigation on EMP effect of SRAM

    International Nuclear Information System (INIS)

    Han Jun; Xie Yanzhao; Zhai Aibin; Yao Zhibin

    2010-01-01

    The response of SRAM with different memory size at different read/write state was studied under EMP environment with pulse width of 50 ns, 350 ns and 1μs.The electric field amplitude of EMP ranges from 2.5 to 40 kV/m. It was found that the upset number has no obvious relation with memory size of SRAM and band width of EMP. The electric field amplitude is the crucial parameter leading to the upset effects. Further more, the upset effects of SRAM at read write state was much more seriously compared to the SRAM was not at read/write state. (authors)

  16. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  17. An SEU resistant 256K SOI SRAM

    Science.gov (United States)

    Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

    1992-12-01

    A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

  18. A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

    Science.gov (United States)

    Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

    2006-04-01

    A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

  19. Design of power balance SRAM for DPA-resistance

    Science.gov (United States)

    Keji, Zhou; Pengjun, Wang; Liang, Wen

    2016-04-01

    A power balance static random-access memory (SRAM) for resistance to differential power analysis (DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional short-circuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm2. The post-simulation results show that the normalized energy deviation (NED) and normalized standard deviation (NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002), and the K. C. Wong Magna Fund in Ningbo University, China.

  20. Performance Evaluation of 14 nm FinFET-Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

    OpenAIRE

    Wei Lim; Huei Chaeng Chin; Cheng Siong Lim; Michael Loong Peng Tan

    2014-01-01

    As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14 nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC)...

  1. Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

    Science.gov (United States)

    Warren, Kevin M.; Weller, Robert A.; Sierawski, Brian; Reed, Robert A.; Mendenhall, Marcus H.; Schrimpf, Ronald D.; Massengill, Lloyd; Porter, Mark; Wilkerson, Jeff; LaBel, Kenneth A.; hide

    2006-01-01

    The RADSAFE simulation framework is described and applied to model Single Event Upsets (SEU) in a 0.25 micron CMOS 4Mbit Static Random Access Memory (SRAM). For this circuit, the RADSAFE approach produces trends similar to those expected from classical models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

  2. Low standby leakage 12T SRAM cell characterisation

    Science.gov (United States)

    Yadav, Arjun; Nakhate, Sangeeta

    2016-09-01

    In this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.

  3. False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

    Science.gov (United States)

    Sawada, Takuya; Takata, Hidehiro; Nii, Koji; Nagata, Makoto

    2013-04-01

    Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

  4. Merits of CMOS/SIMOX technology for low-voltage SRAM macros

    CERN Document Server

    Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

    1999-01-01

    A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

  5. Design and analysis of single- ended robust low power 8T SRAM cell

    Directory of Open Access Journals (Sweden)

    Gupta Neha

    2016-01-01

    Full Text Available This paper is based on the observation of 8T single ended static random access memory (SRAM and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL. In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.

  6. Embedded Detection and Correction of SEU Bursts in SRAM Memories Used as Radiation Detectors

    CERN Document Server

    Secondo, R.; Danzeca, S.; Losito, R.; Peronnard, P.; Masi, A.; Brugger, M.; Dusseau, L.

    2016-01-01

    SRAM memories are widely used as particle fluence detectors in high radiation environments, such as in the Radiation Monitoring System (RadMon) currently in operation in the CERN accelerator complex. Multiple Cell Upsets (MCUs), arising from micro-latchup events, are characterized by a large number of SEUs, ultimately affecting the measurement of particle fluxes and resulting in corrupted data and accuracy losses. A study of the generation of this type of SEU bursts was performed on an 8 Mbit 90-nm SRAM memory. Experimental tests were carried out with a focused beam of protons on target as well as in a mixed field environment dominated by high energy hadrons. A solution approach using an on-line detection and correction algorithm embedded on an FPGA was investigated and evaluated for use on a RadMon device.

  7. The fast neutron SEU cross section of a 4 Mb SRAM memory

    International Nuclear Information System (INIS)

    Pereira Junior, Evaldo C.F.; Goncalez, Odair L.; Cruz, Marco Aurelio da; Prado, Adriane Cristina Mendes; Federico, Claudio Antonio; Gaspar, Felipe de Barros

    2013-01-01

    The results of a static test of single event upset (SEU) produced by fast neutrons on an ISSI 4Mb SRAM memory are reported in this work. To perform the tests, it was built a platform based on a motherboard which is controlled by microprocessor, whose function is to perform the writing, reading and control of the memories under irradiation. The irradiation was performed with a set of 8 241 Am-Be neutrons source in a quasi-isotropic incidence. The SEU cross was calculated from the accumulated bit flip count. (author)

  8. A robust SRAM-PUF key generation scheme based on polar codes

    NARCIS (Netherlands)

    Chen, Bin; Ignatenko, Tanya; Willems, Frans M.J.; Maes, Roel; van der Sluis, Erik; Selimis, Georgios

    2017-01-01

    Physical unclonable functions (PUFs) are relatively new security primitives used for device authentication and device-specific secret key generation. In this paper we focus on SRAM- PUFs. The SRAM-PUFs enjoy uniqueness and randomness properties stemming from the intrinsic randomness of SRAM memory

  9. Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

    Science.gov (United States)

    Ogasawara, Ryosuke; Endoh, Tetsuo

    2018-04-01

    In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

  10. Single Event Upset in Static Random Access Memories in Atmospheric Neutron Environments

    Science.gov (United States)

    Arita, Yutaka; Takai, Mikio; Ogawa, Izumi; Kishimoto, Tadafumi

    2003-07-01

    Single-event upsets (SEUs) in a 0.4 μm 4 Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476 m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using 252Cf.

  11. Development of measurement system for radiation effect on static random access memory based field programmable gate array

    International Nuclear Information System (INIS)

    Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

    2009-01-01

    Based on the detailed investigation in field programmable gate array(FPGA) radiation effects theory, a measurement system for radiation effects on static random access memory(SRAM)-based FPGA was developed. The testing principle of internal memory, function and power current was introduced. The hardware and software implement means of system were presented. Some important parameters for radiation effects on SRAM-based FPGA, such as configuration RAM upset section, block RAM upset section, function fault section and single event latchup section can be gained with this system. The transmission distance of the system can be over 50 m and the maximum number of tested gates can reach one million. (authors)

  12. Single event upset in static random access memories in atmospheric neutron environments

    CERN Document Server

    Arita, Y; Ogawa, I; Kishimoto, T

    2003-01-01

    Single-event upsets (SEUs) in a 0.4 mu m 4Mbit complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) were investigated in various atmospheric neutron environments at sea level, at an altitude of 2612 m mountain, at an altitude of commercial airplane, and at an underground depth of 476m. Neutron-induced SEUs increase with the increase in altitude. For a device with a borophosphosilicate glass (BPSG) film, SEU rates induced by thermal neutrons increase with the decrease in the cell charge of a memory cell. A thermal neutron-induced SEU is significant in SRAMs with a small cell charge. With the conditions of small cell charge, thermal neutron-induced SEUs account for 60% or more of the total neutron-induced SEUs. The SEU rate induced by atmospheric thermal neutrons can be estimated by an acceleration test using sup 2 sup 5 sup 2 Cf. (author)

  13. Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

    2017-04-01

    In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

  14. SEU ground and flight data in static random access memories

    International Nuclear Information System (INIS)

    Liu, J.; Duan, J.L.; Hou, M.D.; Sun, Y.M.; Yao, H.J.; Mo, D.; Zhang, Q.X.; Wang, Z.G.; Jin, Y.F.; Cai, J.R.; Ye, Z.H.; Han, J.W.; Lin, Y.L.; Huang, Z.

    2006-01-01

    This paper presents the vulnerabilities of single event effects (SEEs) simulated by heavy ions on ground and observed on SJ-5 research satellite in space for static random access memories (SRAMs). A single event upset (SEU) prediction code has been used to estimate the proton-induced upset rates based on the ground test curve of SEU cross-section versus heavy ion linear energy transfer (LET). The result agrees with that of the flight data

  15. A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

    Science.gov (United States)

    Han, Runze; Shen, Wensheng; Huang, Peng; Zhou, Zheng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

    2018-04-01

    A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

  16. Low-Power Built-In Self-Test Techniques for Embedded SRAMs

    Directory of Open Access Journals (Sweden)

    Shyue-Kung Lu

    2007-01-01

    Full Text Available The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

  17. A Robust SRAM-PUF Key Generation Scheme Based on Polar Codes

    OpenAIRE

    Chen, Bin; Ignatenko, Tanya; Willems, Frans M. J.; Maes, Roel; van der Sluis, Erik; Selimis, Georgios

    2017-01-01

    Physical unclonable functions (PUFs) are relatively new security primitives used for device authentication and device-specific secret key generation. In this paper we focus on SRAM-PUFs. The SRAM-PUFs enjoy uniqueness and randomness properties stemming from the intrinsic randomness of SRAM memory cells, which is a result of manufacturing variations. This randomness can be translated into the cryptographic keys thus avoiding the need to store and manage the device cryptographic keys. Therefore...

  18. SEE induced in SRAM operating in a superconducting electron linear accelerator environment

    Science.gov (United States)

    Makowski, D.; Mukherjee, Bhaskar; Grecki, M.; Simrock, Stefan

    2005-02-01

    Strong fields of bremsstrahlung photons and photoneutrons are produced during the operation of high-energy electron linacs. Therefore, a mixed gamma and neutron radiation field dominates the accelerators environment. The gamma radiation induced Total Ionizing Dose (TID) effect manifests the long-term deterioration of the electronic devices operating in accelerator environment. On the other hand, the neutron radiation is responsible for Single Event Effects (SEE) and may cause a temporal loss of functionality of electronic systems. This phenomenon is known as Single Event Upset (SEU). The neutron dose (KERMA) was used to scale the neutron induced SEU in the SRAM chips. Hence, in order to estimate the neutron KERMA conversion factor for Silicon (Si), dedicated calibration experiments using an Americium-Beryllium (241Am/Be) neutron standard source was carried out. Single Event Upset (SEU) influences the short-term operation of SRAM compared to the gamma induced TID effect. We are at present investigating the feasibility of an SRAM based real-time beam-loss monitor for high-energy accelerators utilizing the SEU caused by fast neutrons. This paper highlights the effects of gamma and neutron radiations on Static Random Access Memory (SRAM), placed at selected locations near the Superconducting Linear Accelerator driving the Vacuum UV Free Electron Laser (VUVFEL) of DESY.

  19. Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

    Science.gov (United States)

    Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

    2018-04-01

    We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

  20. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    International Nuclear Information System (INIS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

  1. A novel CMOS SRAM feedback element for SEU environments

    International Nuclear Information System (INIS)

    Verghese, S.; Wortman, J.J.; Kerns, S.E.

    1987-01-01

    A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

  2. Impact of temperature on single event upset measurement by heavy ions in SRAM devices

    International Nuclear Information System (INIS)

    Liu Tianqi; Geng Chao; Zhang Zhangang; Gu Song; Tong Teng; Xi Kai; Hou Mingdong; Liu Jie; Zhao Fazhan; Liu Gang; Han Zhengsheng

    2014-01-01

    The temperature dependence of single event upset (SEU) measurement both in commercial bulk and silicon on insulator (SOI) static random access memories (SRAMs) has been investigated by experiment in the Heavy Ion Research Facility in Lanzhou (HIRFL). For commercial bulk SRAM, the SEU cross section measured by 12 C ions is very sensitive to the temperature. The temperature test of SEU in SOI SRAM was conducted by 209 Bi and 12 C ions, respectively, and the SEU cross sections display a remarkable growth with the elevated temperature for 12 C ions but keep constant for 209 Bi ions. The impact of temperature on SEU measurement was analyzed by Monte Carlo simulation. It is revealed that the SEU cross section is significantly affected by the temperature around the threshold linear energy transfer of SEU occurrence. As the SEU occurrence approaches saturation, the SEU cross section gradually exhibits less temperature dependency. Based on this result, the experimental data measured in HIRFL was analyzed, and then a reasonable method of predicting the on-orbit SEU rate was proposed. (semiconductor devices)

  3. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  4. Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions

    Directory of Open Access Journals (Sweden)

    Mingyang Gong

    2018-06-01

    Full Text Available Static Random Access Memory (SRAM Physical Unclonable Functions (PUFs are some of the most popular PUFs that provide a highly-secured solution for secret key storage. Given that PUF responses are noisy, the key reconstruction must use error correcting code (ECC to reduce the noise. Repetition code is widely used in resource constrained systems as it is concise and lightweight, however, research has shown that repetition codes can lead to information leakage. In this paper we found that the strongest cell distribution in a SRAM array may leak information of the responses of SRAM PUF when the repetition code is directly applied. Experimentally, on an ASIC platform with the HHGRACE 0.13 μm process, we recovered 8.3% of the measured response using the strongest cells revealed by the helper data, and we finally obtained a clone response 79% similar to weak response using the public helper data. We therefore propose Error Resistant Fuzzy Extractor (ERFE, a 4-bit error tolerant fuzzy extractor, that extracts the value of the sum of the responses as a unique key and reduces the failure rate to 1.8 × 10−8 with 256 bit entropy.

  5. Low power test architecture for dynamic read destructive fault detection in SRAM

    Science.gov (United States)

    Takher, Vikram Singh; Choudhary, Rahul Raj

    2018-06-01

    Dynamic Read Destructive Fault (dRDF) is the outcome of resistive open defects in the core cells of static random-access memories (SRAMs). The sensitisation of dRDF involves either performing multiple read operations or creation of number of read equivalent stress (RES), on the core cell under test. Though the creation of RES is preferred over the performing multiple read operation on the core cell, cell dissipates more power during RES than during the read or write operation. This paper focuses on the reduction in power dissipation by optimisation of number of RESs, which are required to sensitise the dRDF during test mode of operation of SRAM. The novel pre-charge architecture has been proposed in order to reduce the power dissipation by limiting the number of RESs to an optimised number of two. The proposed low power architecture is simulated and analysed which shows reduction in power dissipation by reducing the number of RESs up to 18.18%.

  6. Highly flexible SRAM cells based on novel tri-independent-gate FinFET

    Science.gov (United States)

    Liu, Chengsheng; Zheng, Fanglin; Sun, Yabin; Li, Xiaojin; Shi, Yanling

    2017-10-01

    In this paper, a novel tri-independent-gate (TIG) FinFET is proposed for highly flexible SRAM cells design. To mitigate the read-write conflict, two kinds of SRAM cells based on TIG FinFETs are designed, and high tradeoff are obtained between read stability and speed. Both cells can offer multi read operations for frequency requirement with single voltage supply. In the first TIG FinFET SRAM cell, the strength of single-fin access transistor (TIG FinFET) can be flexibly adjusted by selecting five different modes to meet the needs of dynamic frequency design. Compared to the previous double-independent-gate (DIG) FinFET SRAM cell, 12.16% shorter read delay can be achieved with only 1.62% read stability decrement. As for the second TIG FinFET SRAM cell, pass-gate feedback technology is applied and double-fin TIG FinFETs are used as access transistors to solve the severe write-ability degradation. Three modes exist to flexibly adjust read speed and stability, and 68.2% larger write margin and 51.7% shorter write delay are achieved at only the expense of 26.2% increase in leakage power, with the same layout area as conventional FinFET SRAM cell.

  7. A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array

    OpenAIRE

    Kang, Mingu; Gonugondla, Sujan; Patil, Ameya; Shanbhag, Naresh

    2016-01-01

    This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (

  8. 39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

    Science.gov (United States)

    Yamamoto, Yasue; Moriwaki, Shinichi; Kawasumi, Atsushi; Miyano, Shinji; Shinohara, Hirofumi

    2016-04-01

    We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS.

  9. Single-word multiple-bit upsets in static random access devices

    International Nuclear Information System (INIS)

    Koga, R.; Pinkerton, S.D.; Lie, T.J.; Crawford, K.B.

    1993-01-01

    Energetic ions and protons can cause single event upsets (SEUs) in static random access memory (SRAM) cells. In some cases multiple bits may be upset as the result of a single event. Space-borne electronics systems incorporating high-density SRAM are vulnerable to single-word multiple-bit upsets (SMUs). The authors review here recent observations of SMU, present the results of a systematic investigation of the physical cell arrangements employed in several currently available SRAM device types, and discuss implications for the occurrence and mitigation of SMU

  10. A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

    Science.gov (United States)

    Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

    2018-04-01

    We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

  11. Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

    International Nuclear Information System (INIS)

    Xiao Yao; Guo Hong-Xia; Zhang Feng-Qi; Zhao Wen; Wang Yan-Ping; Zhang Ke-Ying; Ding Li-Li; Luo Yin-Hong; Wang Yuan-Ming; Fan Xue

    2014-01-01

    Synergistic effects of the total ionizing dose (TID) on the single event upset (SEU) sensitivity in static random access memories (SRAMs) were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed. (interdisciplinary physics and related areas of science and technology)

  12. Real-time soft error rate measurements on bulk 40 nm SRAM memories: a five-year dual-site experiment

    Science.gov (United States)

    Autran, J. L.; Munteanu, D.; Moindjie, S.; Saad Saoud, T.; Gasiot, G.; Roche, P.

    2016-11-01

    This paper reports five years of real-time soft error rate experimentation conducted with the same setup at mountain altitude for three years and then at sea level for two years. More than 7 Gbit of SRAM memories manufactured in CMOS bulk 40 nm technology have been subjected to the natural radiation background. The intensity of the atmospheric neutron flux has been continuously measured on site during these experiments using dedicated neutron monitors. As the result, the neutron and alpha component of the soft error rate (SER) have been very accurately extracted from these measurements, refining the first SER estimations performed in 2012 for this SRAM technology. Data obtained at sea level evidence, for the first time, a possible correlation between the neutron flux changes induced by the daily atmospheric pressure variations and the measured SER. Finally, all of the experimental data are compared with results obtained from accelerated tests and numerical simulation.

  13. Analysis of functional failure mode of commercial deep sub-micron SRAM induced by total dose irradiation

    International Nuclear Information System (INIS)

    Zheng Qi-Wen; Cui Jiang-Wei; Zhou Hang; Yu De-Zhao; Yu Xue-Feng; Lu Wu; Guo Qi; Ren Di-Yuan

    2015-01-01

    Functional failure mode of commercial deep sub-micron static random access memory (SRAM) induced by total dose irradiation is experimentally analyzed and verified by circuit simulation. We extensively characterize the functional failure mode of the device by testing its electrical parameters and function with test patterns covering different functional failure modes. Experimental results reveal that the functional failure mode of the device is a temporary function interruption caused by peripheral circuits being sensitive to the standby current rising. By including radiation-induced threshold shift and off-state leakage current in memory cell transistors, we simulate the influence of radiation on the functionality of the memory cell. Simulation results reveal that the memory cell is tolerant to irradiation due to its high stability, which agrees with our experimental result. (paper)

  14. Acquisition and classification of static single-event upset cross section for SRAM-based FPGAs

    International Nuclear Information System (INIS)

    Yao Zhibin; Fan Ruyu; Guo Hongxia; Wang Zhongming; He Baoping; Zhang Fengqi; Zhang Keying

    2011-01-01

    In order to evaluate single event upsets (SEUs) in SRAM-based FPGAs and to find the sensitive resource in configuration memory, a heavy ions irradiation experiment was carried out on a Xilinx FPGAs device XCV300PQ240. The experiment was conducted to gain the static SEU cross section and classify the SEUs in configurations memory according to different resource uses. The results demonstrate that the inter-memory of SRAM-based FPGAs is extremely sensitive to heavy-ion-induced SEUs. The LUT and routing resources are the main source of SEUs in the configuration memory, which covers more than 97.46% of the total upsets. The SEU sensitivity of various resources is different. The IOB control bit and LUT elements are more sensitive,and more attention should be paid to the LUT elements in radiation hardening,which account for a quite large proportion of the configuration memory. (authors)

  15. Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

    CERN Document Server

    Shibin, Konstantin

    2016-01-01

    During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom...

  16. SRAM-Based Passive Dosimeter for High-Energy Accelerator Environments

    CERN Document Server

    Makowski, D R; Napieralski, A; Swiercz, B P

    2005-01-01

    This paper reports a novel NVRAM-based neutron dose monitor (REM counter). The principle of this device is based on the radiation effect initiating the Single Event Upset SEU in high density microelectronic memories. Several batches of Non-Volatile memories from different manufactures were examined in various radiation environments, i.e. 241Am-Be (alpha,n) and Linear accelerators produced radiation fields. A suitable moderator was used to enhance the detector sensitivity. Further experiments were carried out in Linear Accelerators: Linac II, TTF2 and Beam Loss Environment of various Experimental Facilities at DESY Research Centre in Hamburg. A separate batch of SRAM was irradiated with 60Co-gamma rays up to a dose of about 60 Gy. No Single Event Upset (SEU) was registered. This validates, that gamma radiation has a negligible effect to trigger SEU in the SRAM. The proposed detector could be ideal for a neutron dose measurement produced by a high-energy electron linac, including synchrotron and Free Electron L...

  17. Ultra-Low Power Memory Design in Scaled Technology Nodes

    DEFF Research Database (Denmark)

    Zeinali, Behzad

    that the proposed SRAM reduces access time and leakage current by 40% and 20%, respectively, compared to the standard 8T-SRAM cell without any degradation in read and write margins. The second solution is an asymmetric Schottky barrier device, which can mitigate the read–write conflict of the 6T-SRAM cell in scaled...... technology nodes i.e. sub-50 nm. The 6T-SRAM designed based on the proposed device shows 18% leakage reduction and 54%, 6.6% and 3.1X improvement in read margin, write margin and write time, respectively, compared to the conventional 6T-SRAM cell. To address the standby power issue of SRAMs in scaled...... technology nodes, this thesis also investigates emerging non-volatile spintronics memories. In this respect, STT-MRAMs and SOT-MRAMs are studied and their design challenges are explored. To improve the read performance of STT-MRAMs, a novel non-destructive self-reference sensing scheme is proposed enabling...

  18. Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

    Directory of Open Access Journals (Sweden)

    Ali Asghar

    2017-01-01

    Full Text Available In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB. We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7, while varying the cluster sizes (4–16. Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

  19. DESIGN AND ANALYSIS OF STATIC RANDOM ACCESS MEMORY BY SCHMITT TRIGGER TOPOLOGY FOR LOW VOLTAGE APPLICATIONS

    Directory of Open Access Journals (Sweden)

    RUKKUMANI V.

    2016-12-01

    Full Text Available Aggressive scaling of transistor dimensions with each technology generation has resulted an increased integration density and improved device performance at the expense of increased leakage current. The Supply voltage scaling is an effective way of reducing dynamic as well as leakage power consumption. However the sensitivity of the circuit parameters increases with reduction of the supply voltage. SRAM bit- cells utilizing minimum sized transistors are susceptible to various random process variations. The Schmitt Trigger based operation gives better readconstancy as well as superior write-ability compared to the standard bitcell configurations. The proposed Schmitt Trigger based bitcells integrate a built-in feedback mechanism make the process with high tolerance. In this paper an obsolete design of a differential sensing Static Random Access Memory (SRAM bit cells for ultralow-power and ultralow-area Schmitt trigger operation is introduced. The ST bit cells incorporate a built-in feedback mechanism, provided by separate control signal if the feedback is given by the internal nodes, achieving process variation tolerance that must be used for future nano-scaled technology nodes. In this we proposed 32nm technology for designing 10T SRAM cell using Microwind.Total power about 30% is reduced due to 32 nm technology as compared to 65 nm technlology.

  20. Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

    International Nuclear Information System (INIS)

    Li Lei; Zhou Wanting; Liu Huihua

    2012-01-01

    In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

  1. Pattern imprinting in deep sub-micron static random access memories induced by total dose irradiation

    Science.gov (United States)

    Zheng, Qi-Wen; Yu, Xue-Feng; Cui, Jiang-Wei; Guo, Qi; Ren, Di-Yuan; Cong, Zhong-Chao; Zhou, Hang

    2014-10-01

    Pattern imprinting in deep sub-micron static random access memories (SRAMs) during total dose irradiation is investigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell's static noise margin (SNM) and the background data, and study the influence of irradiation on the probability density function of ΔSNM, which is the difference between two data sides' SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation (STI) oxide rather than from the gate oxide of the micron-device.

  2. SRAM Design for Wireless Sensor Networks Energy Efficient and Variability Resilient Techniques

    CERN Document Server

    Sharma, Vibhu; Dehaene, Wim

    2013-01-01

    This book features various, ultra low energy, variability resilient SRAM circuit design techniques for wireless sensor network applications. Conventional SRAM design targets area efficiency and high performance at the increased cost of energy consumption, making it unsuitable for computation-intensive sensor node applications.  This book, therefore, guides the reader through different techniques at the circuit level for reducing   energy consumption and increasing the variability resilience. It includes a detailed review of the most efficient circuit design techniques and trade-offs, introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability for the advanced technology nodes.    Discusses fundamentals of energy reduction for SRAM circuits and applies them to energy limitation challenges associated with wireless sensor  nodes; Explains impact of variability resilience in reducing the energy consumption; Describes various...

  3. Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

    Science.gov (United States)

    Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

    2018-04-01

    A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

  4. On the evaluation of the sensitivity of SRAM-Based FPGA to errors due to natural radiation environment

    International Nuclear Information System (INIS)

    Bocquillon, Alexandre

    2009-01-01

    This work aims at designing a test methodology to analyze the effect of natural radiation on FPGA SRAM-based chip-sets. Study of likely errors due to single or multiple events occurring in the configuration memory will be based on fault-injection experiments performed with laser devices. It relies on both a description of scientific background and a description of complex architecture of FPGA SRAM-Based and usual testing apparatus. Fault injection experiments with laser are conducted on several classes of components in order to perform static tests of the configuration memory and identify the links with the application. It shows the organization and sensitivity of SRAM configuration cells. Criticality criteria for configuration bits have been specified following dynamic tests in protons accelerator, in regard to their impact on the application. From this classification was developed a predicting tool for critical error rate estimation. (author) [fr

  5. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    International Nuclear Information System (INIS)

    Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  6. Pattern imprinting in deep sub-micron static random access memories induced by total dose irradiation

    International Nuclear Information System (INIS)

    Zheng Qi-Wen; Yu Xue-Feng; Cui Jiang-Wei; Guo Qi; Ren Di-Yuan; Cong Zhong-Chao; Zhou Hang

    2014-01-01

    Pattern imprinting in deep sub-micron static random access memories (SRAMs) during total dose irradiation is investigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell's static noise margin (SNM) and the background data, and study the influence of irradiation on the probability density function of ΔSNM, which is the difference between two data sides' SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation (STI) oxide rather than from the gate oxide of the micron-device. (condensed matter: structural, mechanical, and thermal properties)

  7. Hardware, Software and Data Analysis Techniques for SRAM-based Field Programmable Gate Array Circuits

    National Research Council Canada - National Science Library

    Hockenberry, Eugene B

    2008-01-01

    The main objective of this research is to accomplish two objectives; first, develop a robust test methodology to successfully allow researchers to isolate errors occurring in SRAM-based FPGAs and other memory devices...

  8. Analysis by Monte Carlo simulations of the sensitivity to single event upset of SRAM memories under spatial proton or terrestrial neutron environment

    International Nuclear Information System (INIS)

    Lambert, D.

    2006-07-01

    Electronic systems in space and terrestrial environments are subjected to a flow of particles of natural origin, which can induce dysfunctions. These particles can cause Single Event Upsets (SEU) in SRAM memories. Although non-destructive, the SEU can have consequences on the equipment functioning in applications requiring a great reliability (airplane, satellite, launcher, medical, etc). Thus, an evaluation of the sensitivity of the component technology is necessary to predict the reliability of a system. In atmospheric environment, the SEU sensitivity is mainly caused by the secondary ions resulting from the nuclear reactions between the neutrons and the atoms of the component. In space environment, the protons with strong energies induce the same effects as the atmospheric neutrons. In our work, a new code of prediction of the rate of SEU has been developed (MC-DASIE) in order to quantify the sensitivity for a given environment and to explore the mechanisms of failures according to technology. This code makes it possible to study various technologies of memories SRAM (Bulk and SOI) in neutron and proton environment between 1 MeV and 1 GeV. Thus, MC-DASIE was used with experiment data to study the effect of integration on the sensitivity of the memories in terrestrial environment, a comparison between the neutron and proton irradiations and the influence of the modeling of the target component on the calculation of the rate of SEU. (author)

  9. Soft error evaluation in SRAM using α sources

    International Nuclear Information System (INIS)

    He Chaohui; Chu Jun; Ren Xueming; Xia Chunmei; Yang Xiupei; Zhang Weiwei; Wang Hongquan; Xiao Jiangbo; Li Xiaolin

    2006-01-01

    Soft errors in memories influence directly the reliability of products. To compare the ability of three different memories against soft errors by experiments of alpha particles irradiation, the numbers of soft errors are measured for three different SRAMs and the cross sections of single event upset (SEU) and failures in time (FIT) are calculated. According to the cross sections of SEU, the ability of A166M against soft errors is the best and then B166M, the last B200M. The average FIT of B166M is smaller than that of B200M, and that of A166M is the biggest among them. (authors)

  10. A Technique for Designing Variation Resilient Subthreshold Sram Cell

    Directory of Open Access Journals (Sweden)

    Aminul Islam

    2013-04-01

    Full Text Available This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is similar to the standard read-decoupled 8-transistor (RD8T SRAM cell with the exception that the access FETS are replaced with transmission gates (TGs. In this work, various design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time and TWA (write access time respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35× and TWA distribution (3.79× compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD and 1.64× lower bitline leakage current (ILEAK respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58× tighter spread in IREAD (ILEAK compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency @ 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.   ABSTRAK: Kertas kerja ini membentangkan teknik merekabentuk sel bawah ambang SRAM yang bolehubah. Senibina sel yang dicadangkan adalah sama dengan sel SRAM 8-transistor (RD8T “pisahan-bacaan” piawai kecuali FET akses  digantikan dengan sel pintu transmisi (TGs. Di dalam kajian ini, beberapa metrik rekabentuk dinilai dan dibandingkan dengan sel RD8T SRAM. Rekabentuk yang dicadangkan menawarkan  peningkatan 2.14× dan 1.75×  dalam TRA (masa akses baca dan TWA (masa akses tulis berbanding dengan RD8T. Ia membuktikan kekukuhan variasi proses dengan menampilkan tebaran yang lebih sempit dalam pengagihan TRA (2.35 × dan pengagihan TWA (3.79 × berbanding dengan RD8T. Sel-Bit yang dicadangkan mempunyai arus baca 1.16

  11. Power optimized variation aware dual-threshold SRAM cell design technique

    Directory of Open Access Journals (Sweden)

    Aminul Islam

    2011-02-01

    Full Text Available Aminul Islam1, Mohd Hasan21Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India; 2Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, IndiaAbstract: Bulk complementary metal-oxide semiconductor (CMOS technology is facing enormous challenges at channel lengths below 45 nm, such as gate tunneling, device mismatch, random dopant fluctuations, and mobility degradation. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube-based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology. In this paper, we propose a low-power variation-immune dual-threshold voltage carbon nanotube field effect transistor (CNFET-based seven-transistor (7T static random access memory (SRAM cell. The proposed CNFET-based 7T SRAM cell offers ~1.2× improvement in standby power, ~1.3× improvement in read delay, and ~1.1× improvement in write delay. It offers narrower spread in write access time (1.4× at optimum energy point [OEP] and 1.2× at 1 V. It features 56.3% improvement in static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE (high-performance simulation program with integrated circuit emphasis environment.Keywords: carbon nanotube field effect transistor (CNFET, chirality vector, random dopant

  12. Fault-tolerance techniques for SRAM-based FPGAs

    CERN Document Server

    Kastensmidt, Fernanda Lima; Reis, Ricardo

    2006-01-01

    Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or highly-reliable applications engineers. Today, designers of many next-generation products must cope with reduced margin noises. The continuous evolution of fabrication technology of semiconductor components – shrinking transistor geometry, power supply, speed, and logic density – has significantly reduced the reliability of very deep submicron integrated circuits, in face of various internal and external sources of noise. Field Programmable Gate Arrays (FPGAs), customizable by SRAM cells, are the latest advance in the integrated circuit evolution: millions of memory cells to implement the logic, embedded memories, routing, and embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with current requirements.

  13. The Effect of Proton Energy on SEU Cross-Section of a 16Mbit TFT PMOS SRAM with DRAM Capacitors

    CERN Document Server

    Uznanski, Slawosz; Blackmore, Ewart; Brugger, Markus; Gaillard, Remi; Mekki, Julien; Todd, Benjamin; Trinczek, Michael; Vilar Villanueva, Andrea

    2014-01-01

    Proton experimental data are analyzed for a 16-Mbit Thin-Film-Transistor (TFT) PMOS Static Random Access Memory (SRAM) with DRAM capacitors. The presence of high-Z materials as tungsten causes an unusual increase of the Single Event Upset (SEU) proton cross-section for the energies above 100MeV. Monte-Carlo simulations reproduce the experimentally measured cross-sections up to 480MeV and predict a further increase up to GeV energies. The implications of this increase are analyzed in the context of the LHC and other radiation environments where a significant fraction of the fluence lies above 100MeV.

  14. Accessing memory

    Science.gov (United States)

    Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

    2017-09-26

    A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

  15. Combined methods of tolerance increasing for embedded SRAM

    Science.gov (United States)

    Shchigorev, L. A.; Shagurin, I. I.

    2016-10-01

    The abilities of combined use of different methods of fault tolerance increasing for SRAM such as error detection and correction codes, parity bits, and redundant elements are considered. Area penalties due to using combinations of these methods are investigated. Estimation is made for different configurations of 4K x 128 RAM memory block for 28 nm manufacturing process. Evaluation of the effectiveness of the proposed combinations is also reported. The results of these investigations can be useful for designing fault-tolerant “system on chips”.

  16. Comparisons of single event vulnerability of GaAs SRAMS

    Science.gov (United States)

    Weatherford, T. R.; Hauser, J. R.; Diehl, S. E.

    1986-12-01

    A GaAs MESFET/JFET model incorporated into SPICE has been used to accurately describe C-EJFET, E/D MESFET and D MESFET/resistor GaAs memory technologies. These cells have been evaluated for critical charges due to gate-to-drain and drain-to-source charge collection. Low gate-to-drain critical charges limit conventional GaAs SRAM soft error rates to approximately 1E-6 errors/bit-day. SEU hardening approaches including decoupling resistors, diodes, and FETs have been investigated. Results predict GaAs RAM cell critical charges can be increased to over 0.1 pC. Soft error rates in such hardened memories may approach 1E-7 errors/bit-day without significantly reducing memory speed. Tradeoffs between hardening level, performance and fabrication complexity are discussed.

  17. Modelling of the parametric yield in decananometer SRAM-Arrays

    Directory of Open Access Journals (Sweden)

    Th. Fischer

    2006-01-01

    Full Text Available In today's decananometer (90 nm, 65 nm, ..., CMOS technologies variations of device parameters play an ever more important role. Due to the demand for low leakage systems, supply voltage is decreased on one hand and the transistor threshold voltage is increased on the other hand. This reduces the overdrive voltage of the transistors and leads to decreasing read and write security margins in static memories (SRAM. In addition, smaller dimensions of the devices lead to increasing variations of the device parameters, thus mismatch effects increase. It can be shown that local variations of the transistor parameters limit the functionality of circuits stronger than variations on a global scale or hard defects. We show a method to predict the yield for a large number of SRAM devices without time consuming Monte Carlo simulations in dependence of various parameters (Vdd, temperature, technology options, transistor dimensions, .... This helps the designer to predict the yield for various system options and transistor dimensions, to choose the optimal solution for a specific product.

  18. Atomic memory access hardware implementations

    Science.gov (United States)

    Ahn, Jung Ho; Erez, Mattan; Dally, William J

    2015-02-17

    Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

  19. SRAM-PUF Based on Selective Power-Up and Non-Destructive Scheme

    OpenAIRE

    Mispan, Mohd; Zwolinski, Mark; Halak, Basel

    2016-01-01

    Abstract. Research in hardware security, particularly on Physical Unclonable Functions (PUF) has attracted a lot of attention in recent years. PUFs provide primitives for implementing encryption/decryption and device fingerprinting. Though a wide range of solutions exists for PUF-based CMOS devices, the most investigated solutions today for weak PUF implementation are based on the use of random start-up values of SRAM, which offers the advantage of reusing memories that already exist in many ...

  20. Single event simulation for memories using accelerated ions

    International Nuclear Information System (INIS)

    Sakagawa, Y.; Shiono, N.; Mizusawa, T.; Sekiguchi, M.; Sato, K.; Sugai, I.; Hirao, Y.; Nishimura, J.; Hattori, T.

    1987-01-01

    To evaluate the error immunity of the LSI memories from cosmic rays in space, an irradiation test using accelerated heavy ions is performed. The sensitive regions for 64 K DRAM (Dynamic Random Access Memory) and 4 K SRAM (Static Random Access Memory) are determined from the irradiation test results and the design parameters of the devices. The observed errors can be classified into two types. One is the direct ionization type and the other is the recoil produced error type. Sensitive region is determined for the devices. Error rate estimation methods for both types are proposed and applied to those memories used in space. The error rate of direct ionization exceeds the recoil type by 2 or 3 orders. And the direct ionization is susceptible to shield thickness. (author)

  1. Memory device sensitivity trends in aircraft's environment

    International Nuclear Information System (INIS)

    Bouchet, T.; Fourtine, S.; Calvet, M.C.

    1999-01-01

    The authors present the SEU (single event upset) sensitivity of 31 SRAM (static random access memory) and 8 DRAM (dynamic random access memory) according to their technologies. 2 methods have been used to compute the SEU rate: the NCS (neutron cross section) method and the BGR (burst generation rate) method, the physics data required by both methods have been either found in scientific literature or directly measured. The use of new technologies implies a quicker time response through a dramatic reduction of chip size and of the amount of energy representing 1 bit. The reduction of size makes less particles are likely to interact with the chip but the reduction of the critical charge implies that these interactions are more likely to damage the chip. The SEU sensitivity is then parted between these 2 opposed trends. Results show that for technologies beyond 0,18 μm these 2 trends balance roughly. Nevertheless the feedback experience shows that the number of errors is increasing. This is due to the fact that avionics requires more and more memory to perform numerical functions, the number of bits is increasing so is the risk of errors. As far as SEU is concerned, RAM devices are less and less sensitive comparatively for 1 bit, and DRAM seem to be less sensitive than SRAM. (A.C.)

  2. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

    Science.gov (United States)

    Huynh-Bao, Trong; Ryckaert, Julien; Sakhare, Sushil; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet

    2016-03-01

    In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

  3. Theoretical considerations for SRAM total-dose hardening

    International Nuclear Information System (INIS)

    Francis, P.; Flandre, D.; Colinge, J.P.

    1995-01-01

    The theoretical hardness against total dose of the six-transistor SRAM cell is investigated in detail. An explicit analytical expression of the maximum tolerable threshold voltage shift is derived for two cross-coupled inverters. A numerical method is used to explore the hardness of the read and write operations. Both N- and P-channel access transistors designs are considered and their respective advantages are compared. The study points out that the radiation hardness mainly relies on the technology. Results obtained with the very robust Gate-All-Around process are finally presented

  4. Influence of burn-in on total-ionizing-dose effect of SRAM device

    International Nuclear Information System (INIS)

    Liu Minbo; Yao Zhibin; Huang Shaoyan; He Baoping; Sheng Jiangkun

    2014-01-01

    The influence of Burn-in on the total-ionizing-dose (TID) effect of SRAM device was investigated. SRAM devices of three different feature sizes were selected and irradiated by "6"0Co source with or without pre-irradiation Burn-in. Some parameters for radiation effect of SRAM device such as upset data, were measured, and the influence on the TID effect of different feature size SRAM devices with or without pre-irradiation Burn-in was obtained. The influence of different temperature Burn-in on radiation resistant capability of SRAM device was studied for 0.25 μm SRAM device. The results show that the smaller the device feature size is, the better the radiation-resistant capability of SRAM device is and the weaker the influence of Burn-in is. And the higher Burn-in temperature is, the more serious the influence of Burn-in on the total-dose radiation effect is. (authors)

  5. Evaluation of A Low-power Random Access Memory Generator

    OpenAIRE

    Kameswar Rao, Vaddina

    2006-01-01

    In this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technologys, automating the simulation process and the creation of the workflow for the energy model. One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layou...

  6. A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs

    International Nuclear Information System (INIS)

    Wang Zhongming; Lu Min; Yao Zhibin; Guo Hongxia

    2011-01-01

    SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets (SEUs) in space applications. The failure mechanism in FPGA's configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach. (semiconductor integrated circuits)

  7. On Improving Reliability of SRAM-Based Physically Unclonable Functions

    Directory of Open Access Journals (Sweden)

    Arunkumar Vijayakumar

    2017-01-01

    Full Text Available Physically unclonable functions (PUFs have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 μ s at an area estimate of 4538 μ m 2 with error rate as low as 10 − 6 for intrinsic error probability of 15%.

  8. Microdose analysis of ion strikes on SRAM cells

    Science.gov (United States)

    Scheick, L.

    2003-12-01

    A method of measuring the effect from exposure to highly localized ionizing radiation on microstructures is described. The voltage at which a commercial SRAM cell cannot hold a programmed state changes with microdose. The microdose distribution across the array, in addition to the analysis of the occurrence of anomalous shifts in operating bias due to rare, large energy-deposition events is studied. The effect of multiple hits on a SRAM cell is presented. A general theory on multiple hits from which basic device parameters can be extracted is presented. SPICE, as well as analysis of basic device physics, is used to analyze the damage to individual transistors and the response of a SRAM cell.

  9. Power Management and SRAM for Energy-Autonomous and Low-Power Systems

    Science.gov (United States)

    Chen, Gregory K.

    We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems. These microsystems achieve zero-net-energy operation using solar energy harvesting and ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external wand while consuming 4.70nJ/bit. This provides rapid feedback about treatment efficacies to decrease physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual temperature sensor is presented that processes data using a 2.1muW near-threshold ARMRTM Cortex-M3(TM) muP that provides a widely-used and trusted programming platform. Energy harvesting and power management techniques for these two microsystems enable energy-autonomous operation. The IOP monitor harvests 80nW of solar power while consuming only 5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved load regulation, and tight line regulation. Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent power budgets. VDD scaling in memory decreases energy per access, but also decreases stability margins. These margins can be improved using sizing, VTH selection, and assist circuits, as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes 70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by 72mV. The circuit techniques for energy autonomy presented in this dissertation enable

  10. Low-Power Differential SRAM design for SOC Based on the 25-um Technology

    Science.gov (United States)

    Godugunuri, Sivaprasad; Dara, Naveen; Sambasiva Nayak, R.; Nayeemuddin, Md; Singh, Yadu, Dr.; Veda, R. N. S. Sunil

    2017-08-01

    In recent, the SOC styles area unit the vast complicated styles in VLSI these SOC styles having important low-power operations problems, to comprehend this we tend to enforced low-power SRAM. However these SRAM Architectures critically affects the entire power of SOC and competitive space. To beat the higher than disadvantages, during this paper, a low-power differential SRAM design is planned. The differential SRAM design stores multiple bits within the same cell, operates at minimum in operation low-tension and space per bit. The differential SRAM design designed supported the 25-um technology using Tanner-EDA Tool.

  11. Quantum random access memory

    OpenAIRE

    Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

    2007-01-01

    A random access memory (RAM) uses n bits to randomly address N=2^n distinct memory cells. A quantum random access memory (qRAM) uses n qubits to address any quantum superposition of N memory cells. We present an architecture that exponentially reduces the requirements for a memory call: O(log N) switches need be thrown instead of the N used in conventional (classical or quantum) RAM designs. This yields a more robust qRAM algorithm, as it in general requires entanglement among exponentially l...

  12. A novel high reliability CMOS SRAM cell

    Energy Technology Data Exchange (ETDEWEB)

    Xie Chengmin; Wang Zhongfang; Wu Longsheng; Liu Youbao, E-mail: hglnew@sina.com [Computer Research and Design Department, Xi' an Microelectronic Technique Institutes, Xi' an 710054 (China)

    2011-07-15

    A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military. (semiconductor integrated circuits)

  13. A novel high reliability CMOS SRAM cell

    International Nuclear Information System (INIS)

    Xie Chengmin; Wang Zhongfang; Wu Longsheng; Liu Youbao

    2011-01-01

    A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military. (semiconductor integrated circuits)

  14. Detecting Recycled Commodity SoCs: Exploiting Aging-Induced SRAM PUF Unreliability

    OpenAIRE

    Gao, Yansong; Ma, Hua; Al-Sarawi, Said F.; Abbott, Derek; Ranasinghe, Damith C.

    2017-01-01

    A physical unclonable function (PUF), analogous to a human fingerprint, has gained an enormous amount of attention from both academia and industry. SRAM PUF is among one of the popular silicon PUF constructions that exploits random initial power-up states from SRAM cells to extract hardware intrinsic secrets for identification and key generation applications. The advantage of SRAM PUFs is that they are widely embedded into commodity devices, thus such a PUF is obtained without a custom design...

  15. Overview of emerging nonvolatile memory technologies.

    Science.gov (United States)

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  16. Overview of emerging nonvolatile memory technologies

    Science.gov (United States)

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  17. Non-volatile memories

    CERN Document Server

    Lacaze, Pierre-Camille

    2014-01-01

    Written for scientists, researchers, and engineers, Non-volatile Memories describes the recent research and implementations in relation to the design of a new generation of non-volatile electronic memories. The objective is to replace existing memories (DRAM, SRAM, EEPROM, Flash, etc.) with a universal memory model likely to reach better performances than the current types of memory: extremely high commutation speeds, high implantation densities and retention time of information of about ten years.

  18. Serendipitous SEU hardening of resistive load SRAMs

    International Nuclear Information System (INIS)

    Koga, R.; Kirshman, J.F.; Pinkerton, S.D.; Hansel, S.J.; Crawford, K.B.; Crain, W.R.

    1996-01-01

    High and low resistive load versions of Micron Technology's MT5C1008C (128K x 8) and MT5C2561C (256K x 1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a 1 → 0 to 0 → 1 bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations

  19. A radiation-hardened two transistor memory cell for monolithic active pixel sensors in STAR experiment

    International Nuclear Information System (INIS)

    Wei, X; Dorokhov, A; Hu, Y; Gao, D

    2011-01-01

    Radiation tolerance of Monolithic Active Pixel Sensors (MAPS) is dramatically decreased when intellectual property (IP) memories are integrated for fast readout application. This paper presents a new solution to improve radiation hardness and avoid latch-up for memory cell design. The tradeoffs among radiation tolerance, area and speed are significantly considered and analyzed. The cell designed in 0.35 μm process satisfies the radiation tolerance requirements of STAR experiment. The cell size is 4.55 x 5.45 μm 2 . This cell is smaller than the IP memory cell based on the same process and is only 26% of a radiation tolerant 6T SRAM cell used in previous contribution. The write access time of the cell is less than 2 ns, while the read access time is 80 ns.

  20. Towards Terabit Memories

    Science.gov (United States)

    Hoefflinger, Bernd

    Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

  1. A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

    Directory of Open Access Journals (Sweden)

    Alireza Shafaei

    2015-08-01

    Full Text Available This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point.

  2. Implications of the spatial dependence of the single-event-upset threshold in SRAMs measured with a pulsed laser

    International Nuclear Information System (INIS)

    Buchner, S.; Langworthy, J.B.; Stapor, W.J.; Campbell, A.B.; Rivet, S.

    1994-01-01

    Pulsed laser light was used to measure single event upset (SEU) thresholds for a large number of memory cells in both CMOS and bipolar SRAMs. Results showed that small variations in intercell upset threshold could not explain the gradual rise in the curve of cross section versus linear energy transfer (LET). The memory cells exhibited greater intracell variations implying that the charge collection efficiency within a memory cell varies spatially and contributes substantially to the shape of the curve of cross section versus LET. The results also suggest that the pulsed laser can be used for hardness-assurance measurements on devices with sensitive areas larger than the diameter of the laser beam

  3. Architectures for a quantum random access memory

    OpenAIRE

    Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

    2008-01-01

    A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with n-bit addresses can access 2^n memory sites. Any design for a RAM or qRAM then requires O(2^n) two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices ...

  4. Memory device sensitivity trends in aircraft's environment; Evolution de la sensibilite de composants memoires en altitude avion

    Energy Technology Data Exchange (ETDEWEB)

    Bouchet, T.; Fourtine, S. [Aerospatiale-Matra Airbus, 31 - Toulouse (France); Calvet, M.C. [Aerospatiale-Matra Lanceur, 78 - Les Mureaux (France)

    1999-07-01

    The authors present the SEU (single event upset) sensitivity of 31 SRAM (static random access memory) and 8 DRAM (dynamic random access memory) according to their technologies. 2 methods have been used to compute the SEU rate: the NCS (neutron cross section) method and the BGR (burst generation rate) method, the physics data required by both methods have been either found in scientific literature or directly measured. The use of new technologies implies a quicker time response through a dramatic reduction of chip size and of the amount of energy representing 1 bit. The reduction of size makes less particles are likely to interact with the chip but the reduction of the critical charge implies that these interactions are more likely to damage the chip. The SEU sensitivity is then parted between these 2 opposed trends. Results show that for technologies beyond 0,18 {mu}m these 2 trends balance roughly. Nevertheless the feedback experience shows that the number of errors is increasing. This is due to the fact that avionics requires more and more memory to perform numerical functions, the number of bits is increasing so is the risk of errors. As far as SEU is concerned, RAM devices are less and less sensitive comparatively for 1 bit, and DRAM seem to be less sensitive than SRAM. (A.C.)

  5. 65NM sub-threshold 11T-SRAM for ultra low voltage applications

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Aunet, Snorre

    In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static noise margin (SNM) and the performance. Foundry models for a 65 nm standard CMOS process were used for obtaining reliable...... simulated results. The circuit was simulated for supply voltages from 0.2 V to 0.35 V verifying the robustness of the proposed circuit for different supply voltages. The simulations show a significant improvement in SNM and a 4X improvement in read speed still maintaining a satisfactory write noise margin...

  6. Security of helper data Schemes for SRAM-PUF in multiple enrollment scenarios

    NARCIS (Netherlands)

    Kusters, C.J.; Ignatenko, T.; Maes, R.; van der Sluis, E.; Selimis, G.; Willems, F.M.J.

    2017-01-01

    Fuzzy commitment and syndrome-based schemes are two well-known helper data schemes used to bind and generate, respectively, a secret key to/from SRAM-PUF observations. To allow the decoder to reconstruct this secret key from a new (verification) observation of an SRAM-PUF, an encoder has to generate

  7. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    Energy Technology Data Exchange (ETDEWEB)

    Ohmacht, Martin

    2017-08-15

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  8. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    Science.gov (United States)

    Ohmacht, Martin

    2014-09-09

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  9. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques

    International Nuclear Information System (INIS)

    Cai Jiangzheng; Zhang Sumin; Yuan Jia; Shang Xinchao; Chen Liming; Hei Yong

    2015-01-01

    This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94 μW at its lowest voltage (320 mV). (paper)

  10. A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation

    Science.gov (United States)

    Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan

    2018-01-01

    Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V. He received 2016 International Low Power Design Contest Award from ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from Univ. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008, 2001, and 1999 Samsung Humantec Thesis Award and, 2005 ETRI Journal Paper of the Year Award. He is an author/co-author of +100 journal and conference papers and has 17 US and Korean patents registered. His current research interests include low power and high performance digital, mixed- mode, and memory circuit design, ultra-low voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He serves as an associate editor of IEEE Transactions on VLSI Systems. He is an IEEE senior member and the Chair of IEEE Solid-State Circuits Society Singapore Chapter. He has served numerous conferences as a committee member.

  11. An experimental study on total dose effects in SRAM-based FPGAs

    International Nuclear Information System (INIS)

    Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

    2009-01-01

    In order to study testing methods and find sensitive parameters in total dose effects on SRAM-based FPGA, XC2S100 chips were irradiated by 60 Co γ-rays and tested with two test circuit designs. By analyzing the experimental results, the test flow of configuration RAM and bock RAM was given, and the most sensitive parameter was obtained. The results will be a solid foundation for establishing test specification and evaluation methods of total dose effects on SRAM-based FPGAs. (authors)

  12. Method and apparatus for managing access to a memory

    Science.gov (United States)

    DeBenedictis, Erik

    2017-08-01

    A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operational memory layout reduces an amount of energy consumed by the processor to perform the computing job.

  13. Accessing forgotten memory traces from long-term memory via visual movements

    Directory of Open Access Journals (Sweden)

    Estela eCamara

    2014-11-01

    Full Text Available Because memory retrieval often requires overt responses, it is difficult to determine to what extend forgetting occurs as a problem in explicit accessing of long-term memory traces. In this study, we used eye-tracking measures in combination with a behavioural task that favoured high forgetting rates to investigate the existence of memory traces from long-term memory in spite of failure in accessing them consciously. In 2 experiments, participants were encouraged to encode a large set of sound-picture-location associations. In a later test, sounds were presented and participants were instructed to visually scan, before a verbal memory report, for the correct location of the associated pictures in an empty screen. We found the reactivation of associated memories by sound cues at test biased oculomotor behaviour towards locations congruent with memory representations, even when participants failed to consciously provide a memory report of it. These findings reveal the emergence of a memory-guided behaviour that can be used to map internal representations of forgotten memories from long-term memory.

  14. A Physics-Based Engineering Approach to Predict the Cross Section for Advanced SRAMs

    Science.gov (United States)

    Li, Lei; Zhou, Wanting; Liu, Huihua

    2012-12-01

    This paper presents a physics-based engineering approach to estimate the heavy ion induced upset cross section for 6T SRAM cells from layout and technology parameters. The new approach calculates the effects of radiation with junction photocurrent, which is derived based on device physics. The new and simple approach handles the problem by using simple SPICE simulations. At first, the approach uses a standard SPICE program on a typical PC to predict the SPICE-simulated curve of the collected charge vs. its affected distance from the drain-body junction with the derived junction photocurrent. And then, the SPICE-simulated curve is used to calculate the heavy ion induced upset cross section with a simple model, which considers that the SEU cross section of a SRAM cell is more related to a “radius of influence” around a heavy ion strike than to the physical size of a diffusion node in the layout for advanced SRAMs in nano-scale process technologies. The calculated upset cross section based on this method is in good agreement with the test results for 6T SRAM cells processed using 90 nm process technology.

  15. Hardware Compilation of Application-Specific Memory-Access Interconnect

    DEFF Research Database (Denmark)

    Venkataramani, Girish; Bjerregaard, Tobias; Chelcea, Tiberiu

    2006-01-01

    operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative...... enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times...

  16. An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications

    Directory of Open Access Journals (Sweden)

    Arijit Banerjee

    2014-05-01

    Full Text Available Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM, leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.

  17. Self-Testing Static Random-Access Memory

    Science.gov (United States)

    Chau, Savio; Rennels, David

    1991-01-01

    Proposed static random-access memory for computer features improved error-detecting and -correcting capabilities. New self-testing scheme provides for detection and correction of errors at any time during normal operation - even while data being written into memory. Faults in equipment causing errors in output data detected by repeatedly testing every memory cell to determine whether it can still store both "one" and "zero", without destroying data stored in memory.

  18. Architectures for a quantum random access memory

    Science.gov (United States)

    Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

    2008-11-01

    A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with n -bit addresses can access 2n memory sites. Any design for a RAM or qRAM then requires O(2n) two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices impractical, due to the difficulty of constructing and operating coherent devices with large numbers of quantum logic gates. Here we analyze two different RAM architectures (the conventional fanout and the “bucket brigade”) and propose some proof-of-principle implementations, which show that, in principle, only O(n) two-qubit physical interactions need take place during each qRAM call. That is, although a qRAM needs O(2n) quantum logic gates, only O(n) need to be activated during a memory call. The resulting decrease in resources could give rise to the construction of large qRAMs that could operate without the need for extensive quantum error correction.

  19. Impact of NBTI Aging on the Single-Event Upset of SRAM Cells

    CERN Document Server

    Bagatin, M; Gerardin, Simone; Paccagnella, Alessandro; Bagatin, Marta

    2010-01-01

    We analyzed the impact of negative bias temperature instability (NBTI) on the single-event upset rate of SRAM cells through experiments and SPICE simulations. We performed critical charge simulations introducing different degradation patterns in the cells, in three technology nodes, from 180 to 90 nm. The simulations results were checked with alpha-particle and heavy-ion irradiations on a 130-nm technology. Both simulations and experimental results show that NBTI degradation does not significantly affect the single-event upset SRAM cell rate as long as the parametric drift induced by aging is within 10\\%.

  20. Notified Access: Extending Remote Memory Access Programming Models for Producer-Consumer Synchronization

    KAUST Repository

    Belli, Roberto; Hoefler, Torsten

    2015-01-01

    Remote Memory Access (RMA) programming enables direct access to low-level hardware features to achieve high performance for distributed-memory programs. However, the design of RMA programming schemes focuses on the memory access and less on the synchronization. For example, in contemporary RMA programming systems, the widely used producer-consumer pattern can only be implemented inefficiently, incurring in an overhead of an additional round-trip message. We propose Notified Access, a scheme where the target process of an access can receive a completion notification. This scheme enables direct and efficient synchronization with a minimum number of messages. We implement our scheme in an open source MPI-3 RMA library and demonstrate lower overheads (two cache misses) than other point-to-point synchronization mechanisms for each notification. We also evaluate our implementation on three real-world benchmarks, a stencil computation, a tree computation, and a Colicky factorization implemented with tasks. Our scheme always performs better than traditional message passing and other existing RMA synchronization schemes, providing up to 50% speedup on small messages. Our analysis shows that Notified Access is a valuable primitive for any RMA system. Furthermore, we provide guidance for the design of low-level network interfaces to support Notified Access efficiently.

  1. Notified Access: Extending Remote Memory Access Programming Models for Producer-Consumer Synchronization

    KAUST Repository

    Belli, Roberto

    2015-05-01

    Remote Memory Access (RMA) programming enables direct access to low-level hardware features to achieve high performance for distributed-memory programs. However, the design of RMA programming schemes focuses on the memory access and less on the synchronization. For example, in contemporary RMA programming systems, the widely used producer-consumer pattern can only be implemented inefficiently, incurring in an overhead of an additional round-trip message. We propose Notified Access, a scheme where the target process of an access can receive a completion notification. This scheme enables direct and efficient synchronization with a minimum number of messages. We implement our scheme in an open source MPI-3 RMA library and demonstrate lower overheads (two cache misses) than other point-to-point synchronization mechanisms for each notification. We also evaluate our implementation on three real-world benchmarks, a stencil computation, a tree computation, and a Colicky factorization implemented with tasks. Our scheme always performs better than traditional message passing and other existing RMA synchronization schemes, providing up to 50% speedup on small messages. Our analysis shows that Notified Access is a valuable primitive for any RMA system. Furthermore, we provide guidance for the design of low-level network interfaces to support Notified Access efficiently.

  2. Fast Magnetoresistive Random-Access Memory

    Science.gov (United States)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

  3. Direct Access to Working Memory Contents

    NARCIS (Netherlands)

    Bialkova, S.E.; Oberauer, K.

    2010-01-01

    Abstract. In two experiments participants held in working memory (WM) three digits in three different colors, and updated individual digits with the results of arithmetic equations presented in one of the colors. In the memory-access condition, a digit from WM had to be used as the first number in

  4. Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

    Directory of Open Access Journals (Sweden)

    Oliver Sander

    2012-01-01

    Full Text Available SRAM-based fingerprinting uses deviations in power-up behaviour caused by the CMOS fabrication process to identify distinct devices. This method is a promising technique for unique identification of physical devices. In the case of SRAM-based hardware reconfigurable devices such as FPGAs, the integrated SRAM cells are often initialized automatically at power-up, sweeping potential identification data. We demonstrate an approach to utilize unused parts of configuration memory space for device identification. Based on a total of over 200,000 measurements on nine Xilinx Virtex-5 FPGAs, we show that the retrieved values have promising properties with respect to consistency on one device, variety between different devices, and stability considering temperature variation and aging.

  5. Importance of ion energy on SEU in CMOS SRAMs

    Energy Technology Data Exchange (ETDEWEB)

    Dodd, P.E.; Shaneyfelt, M.R.; Sexton, F.W.; Hash, G.L.; Winokur, P.S. [Sandia National Labs., Albuquerque, NM (United States); Musseau, O.; Leray, J.L. [CEA-DAM, Bruyeres-le-Chatel (France)

    1998-03-01

    The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.

  6. Memory Circuit Fault Simulator

    Science.gov (United States)

    Sheldon, Douglas J.; McClure, Tucker

    2013-01-01

    Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

  7. Efficient accesses of data structures using processing near memory

    Science.gov (United States)

    Jayasena, Nuwan S.; Zhang, Dong Ping; Diez, Paula Aguilera

    2018-05-22

    Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

  8. Evaluating a radiation monitor for mixed-field environments based on SRAM technology

    CERN Document Server

    Tsiligiannis, G; Bosio, A; Girard, P; Pravossoudovitch, S; Todri, A; Virazel, A; Mekki, J; Brugger, M; Wrobel, F; Saigne, F

    2014-01-01

    Instruments operating in particle accelerators and colliders are exposed to radiations that are composed of particles of different types and energies. Several of these instruments often embed devices that are not hardened against radiation effects. Thus, there is a strong need for mon- itoring the levels of radiation inside the mixed-field radiation areas, throughout different positions. Different metrics exist for measuring the radiation damage induced to electronic devices, such as the Total Ionizing Dose (TID), the Displacement Damage (DD) and of course the fluence of parti- cles for estimating the error rates of the electronic devices among other applications. In this paper, we propose an SRAM based monitor, that is used to define the fluence of High Energy Hadrons (HEH) by detecting Single Event Upsets in the memory array. We evaluated the device by testing it inside the H4IRRAD area of CERN, a test area that reproduces the radiation conditions inside the Large Hadron Collider (LHC) tunnel and its shield...

  9. Interacting Memory Systems—Does EEG Alpha Activity Respond to Semantic Long-Term Memory Access in a Working Memory Task?

    Directory of Open Access Journals (Sweden)

    Barbara Berger

    2014-12-01

    Full Text Available Memory consists of various individual processes which form a dynamic system co-ordinated by central (executive functions. The episodic buffer as direct interface between episodic long-term memory (LTM and working memory (WM is fairly well studied but such direct interaction is less clear in semantic LTM. Here, we designed a verbal delayed-match-to-sample task specifically to differentiate between pure information maintenance and mental manipulation of memory traces with and without involvement of access to semantic LTM. Task-related amplitude differences of electroencephalographic (EEG oscillatory brain activity showed a linear increase in frontal-midline theta and linear suppression of parietal beta amplitudes relative to memory operation complexity. Amplitude suppression at upper alpha frequency, which was previously found to indicate access to semantic LTM, was only sensitive to mental manipulation in general, irrespective of LTM involvement. This suggests that suppression of upper EEG alpha activity might rather reflect unspecific distributed cortical activation during complex mental processes than accessing semantic LTM.

  10. Evaluation of External Memory Access Performance on a High-End FPGA Hybrid Computer

    Directory of Open Access Journals (Sweden)

    Konstantinos Kalaitzis

    2016-10-01

    Full Text Available The motivation of this research was to evaluate the main memory performance of a hybrid super computer such as the Convey HC-x, and ascertain how the controller performs in several access scenarios, vis-à-vis hand-coded memory prefetches. Such memory patterns are very useful in stencil computations. The theoretical bandwidth of the memory of the Convey is compared with the results of our measurements. The accurate study of the memory subsystem is particularly useful for users when they are developing their application-specific personality. Experiments were performed to measure the bandwidth between the coprocessor and the memory subsystem. The experiments aimed mainly at measuring the reading access speed of the memory from Application Engines (FPGAs. Different ways of accessing data were used in order to find the most efficient way to access memory. This way was proposed for future work in the Convey HC-x. When performing a series of accesses to memory, non-uniform latencies occur. The Memory Controller of the Convey HC-x in the coprocessor attempts to cover this latency. We measure memory efficiency as a ratio of the number of memory accesses and the number of execution cycles. The result of this measurement converges to one in most cases. In addition, we performed experiments with hand-coded memory accesses. The analysis of the experimental results shows how the memory subsystem and Memory Controllers work. From this work we conclude that the memory controllers do an excellent job, largely because (transparently to the user they seem to cache large amounts of data, and hence hand-coding is not needed in most situations.

  11. Accessibility Limits Recall from Visual Working Memory

    Science.gov (United States)

    Rajsic, Jason; Swan, Garrett; Wilson, Daryl E.; Pratt, Jay

    2017-01-01

    In this article, we demonstrate limitations of accessibility of information in visual working memory (VWM). Recently, cued-recall has been used to estimate the fidelity of information in VWM, where the feature of a cued object is reproduced from memory (Bays, Catalao, & Husain, 2009; Wilken & Ma, 2004; Zhang & Luck, 2008). Response…

  12. Assessment of read and write stability for 6T SRAM cell based on charge plasma DLTFET

    Science.gov (United States)

    Anju; Yadav, Shivendra; Sharma, Dheeraj

    2018-03-01

    To overcome the process variations due to random dopant fluctuations (RDFs) and complex annealing techniques a charge plasma based doping less TFET (CP-DLTFET) device has been proposed for designing of 6T SRAM cell. The proposed device also benefited by subthreshold slope, low leakage current, and low power supply. In this paper, to avoid the dependency of stability parameters of SRAM cell to supply voltage (Vdd), here N-curve metrics has been analyzed to determine read and write stability. Because N-curve provides stability analysis in terms of voltage and current as well as it gives combine stability analysis with the facility of an inline tester. Further, analyzing the N-curve metrics for different Vdd, cell ratio, and pull-up ratio assist in designing the configuration of transistors for the better read and write stability. Power metrics of N-curve gives the knowledge about read and write stability instead of using four metrics (SINM, SVNM, WTV, and WTI) of N-curve. Finally, in the 6T CP-DLTFET SRAM cell, read and write stability is tested by the interface trap charges (ITCs). The performance parameter of the 6T CP-DLTFET SRAM cell provides considerable read and write stability with less fabrication complexity.

  13. Extreme Ultraviolet Process Optimization for Contact Layer of 14 nm Node Logic and 16 nm Half Pitch Memory Devices

    Science.gov (United States)

    Tseng, Shih-En; Chen, Alek

    2012-06-01

    Extreme ultraviolet (EUV) lithography is considered the most promising single exposure technology at the 27 nm half-pitch node and beyond. The imaging performance of ASML TWINSCAN NXE:3100 has been demonstrated to be able to resolve 26 nm Flash gate layer and 16 nm static random access memory (SRAM) metal layer with a 0.25 numerical aperture (NA) and conventional illumination. Targeting for high volume manufacturing, ASML TWINSCAN NXE:3300B, featuring a 0.33 NA lens with off-axis illumination, will generate a higher contrast aerial image due to improved diffraction order collection efficiency and is expected to reduce target dose via mask biasing. This work performed a simulation to determine how EUV high NA imaging benefits the mask rule check trade-offs required to achieve viable lithography solutions in two device application scenarios: a 14 nm node 6T-SRAM contact layer and a 16 nm half-pitch NAND Flash staggered contact layer. In each application, the three-dimensional mask effects versus Kirchhoff mask were also investigated.

  14. The New S-RAM Air Variable Compressor/Expander for Heat Pump and Waste Heat to Power Application

    Energy Technology Data Exchange (ETDEWEB)

    Dehoff, Ryan R [ORNL; Jestings, Lee [S-RAM Dynamics; Conde, Ricardo [S-RAM Dynamics

    2016-05-23

    S-RAM Dynamics (S-RAM) has designed an innovative heat pump system targeted for commercial and industrial applications. This new heat pump system is more efficient than anything currently on the market and utilizes air as the refrigerant instead of hydrofluorocarbon (HFC) refrigerants, leading to lower operating costs, minimal environmental costs or concerns, and lower maintenance costs. The heat pumps will be manufactured in the United States. This project was aimed at determining the feasibility of utilizing additive manufacturing to make the heat exchanger device for the new heat pump system. ORNL and S-RAM Dynamics collaborated on determining the prototype performance and subsequently printing of the prototype using additive manufacturing. Complex heat exchanger designs were fabricated using the Arcam electron beam melting (EBM) powder bed technology using Ti-6Al-4V material. An ultrasonic welding system was utilized in order to remove the powder from the small openings of the heat exchanger. The majority of powder in the small chambers was removed, however, the amount of powder remaining in the heat exchanger was a function of geometry. Therefore, only certain geometries of heat exchangers could be fabricated. SRAM Dynamics evaluated a preliminary heat exchanger design. Although the results of the additive manufacturing of the heat exchanger were not optimum, a less complex geometry was demonstrated. A sleeve valve was used as a demonstration piece, as engine designs from S-RAM Dynamics require the engine to have a very high density. Preliminary designs of this geometry were successfully fabricated using the EBM technology.

  15. Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding

    Directory of Open Access Journals (Sweden)

    Sha Edwin Hsing-Mean

    2002-01-01

    Full Text Available This paper presents an iteration space partitioning scheme to reduce the CPU idle time due to the long memory access latency. We take into consideration both the data accesses of intermediate and initial data. An algorithm is proposed to find the largest overlap for initial data to reduce the entire memory traffic. In order to efficiently hide the memory latency, another algorithm is developed to balance the ALU and memory schedules. The experiments on DSP benchmarks show that the algorithms significantly outperform the known existing methods.

  16. A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

    International Nuclear Information System (INIS)

    Bai Na; Lü Baitao

    2012-01-01

    A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency. (semiconductor integrated circuits)

  17. Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off

    DEFF Research Database (Denmark)

    Gleerup, Thomas Møller; Holten-Lund, Hans Erik; Madsen, Jan

    2000-01-01

    . In software, forward differencing is usually better, but in this hardware implementation, the trade-off has made it possible to develop a very regular memory architecture with a buffering system, which can reach 95% bandwidth utilization using off-the-shelf SDRAM, This is achieved by changing the algorithm......This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance requirement of this application is a frame rate of 25 frames per second when rendering 3D models with 2 million triangles, i...... to use a memory access strategy with write-only and read-only phases, and a buffering system, which uses round-robin bank write-access combined with burst read-access....

  18. FinFET memory cell improvements for higher immunity against single event upsets

    Science.gov (United States)

    Sajit, Ahmed Sattar

    The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high

  19. An Investigation of Unified Memory Access Performance in CUDA

    Science.gov (United States)

    Landaverde, Raphael; Zhang, Tiansheng; Coskun, Ayse K.; Herbordt, Martin

    2015-01-01

    Managing memory between the CPU and GPU is a major challenge in GPU computing. A programming model, Unified Memory Access (UMA), has been recently introduced by Nvidia to simplify the complexities of memory management while claiming good overall performance. In this paper, we investigate this programming model and evaluate its performance and programming model simplifications based on our experimental results. We find that beyond on-demand data transfers to the CPU, the GPU is also able to request subsets of data it requires on demand. This feature allows UMA to outperform full data transfer methods for certain parallel applications and small data sizes. We also find, however, that for the majority of applications and memory access patterns, the performance overheads associated with UMA are significant, while the simplifications to the programming model restrict flexibility for adding future optimizations. PMID:26594668

  20. Comparison between ground tests and flight data for two static 32 KB memories

    International Nuclear Information System (INIS)

    Cheynet, Ph.; Velazco, R.; Cheynet, Ph.; Ecoffet, R.; Duzellier, S.; David, J.P.; Loquet, J.G.

    1999-01-01

    The study concerns two 32 K-byte static memories, one from Hitachi (HM62256) and the other (HM65756) from Matra-MHS. The results correspond to around one year of measurement in high radiation orbit and a total of 268 upsets were detected. As a preliminary conclusion it can be stated that the MHS SRAM is probably at least 4 times more sensitive to SEU (single event upset) than the Hitachi SRAM. The Hitachi memory has exhibited what we call ''stuck-at'' bit errors. This kind of event is identified when the same address and data is found in error (fixed read data) for several consecutive read cycles. A confrontation of SEU rates derived from predictions to those measured in flight has shown that: - error rate is underestimated for HM62256 using standard prediction models, - error rate can be under or over-estimated for HM65756 but the dispersion on heavy-ion ground results does not allow us to conclude. (A.C.)

  1. A Methodology for the Analysis of Memory Response to Radiation through Bitmap Superposition and Slicing

    CERN Document Server

    Bosser, A.; Tsiligiannis, G.; Ferraro, R.; Frost, C.; Javanainen, A.; Puchner, H.; Rossi, M.; Saigne, F.; Virtanen, A.; Wrobel, F.; Zadeh, A.; Dilillo, L.

    2015-01-01

    A methodology is proposed for the statistical analysis of memory radiation test data, with the aim of identifying trends in the single-even upset (SEU) distribution. The treated case study is a 65nm SRAM irradiated with neutrons, protons and heavy-ions.

  2. Individual differences in memory span: the contribution of rehearsal, access to lexical memory, and output speed.

    Science.gov (United States)

    Tehan, G; Lalor, D M

    2000-11-01

    Rehearsal speed has traditionally been seen to be the prime determinant of individual differences in memory span. Recent studies, in the main using young children as the subject population, have suggested other contributors to span performance, notably contributions from long-term memory and forgetting and retrieval processes occurring during recall. In the current research we explore individual differences in span with respect to measures of rehearsal, output time, and access to lexical memory. We replicate standard short-term phenomena; we show that the variables that influence children's span performance influence adult performance in the same way; and we show that lexical memory access appears to be a more potent source of individual differences in span than either rehearsal speed or output factors.

  3. Emerging memory technologies design, architecture, and applications

    CERN Document Server

    2014-01-01

    This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits. • Provides a comprehensive reference on designing modern circuits with emerging, non-volatile memory technologies, such as MRAM and PCRAM; • Explores new design opportunities offered by emerging memory technologies, from a holistic perspective; • Describes topics in technology, modeling, architecture and applications; • Enables circuit designers to ex...

  4. Memory Applications Using Resonant Tunneling Diodes

    Science.gov (United States)

    Shieh, Ming-Huei

    Resonant tunneling diodes (RTDs) producing unique folding current-voltage (I-V) characteristics have attracted considerable research attention due to their promising application in signal processing and multi-valued logic. The negative differential resistance of RTDs renders the operating points self-latching and stable. We have proposed a multiple -dimensional multiple-state RTD-based static random-access memory (SRAM) cell in which the number of stable states can significantly be increased to (N + 1)^ m or more for m number of N-peak RTDs connected in series. The proposed cells take advantage of the hysteresis and folding I-V characteristics of RTD. Several cell designs are presented and evaluated. A two-dimensional nine-state memory cell has been implemented and demonstrated by a breadboard circuit using two 2-peak RTDs. The hysteresis phenomenon in a series of RTDs is also further analyzed. The switch model provided in SPICE 3 can be utilized to simulate the hysteretic I-V characteristics of RTDs. A simple macro-circuit is described to model the hysteretic I-V characteristic of RTD for circuit simulation. A new scheme for storing word-wide multiple-bit information very efficiently in a single memory cell using RTDs is proposed. An efficient and inexpensive periphery circuit to read from and write into the cell is also described. Simulation results on the design of a 3-bit memory cell scheme using one-peak RTDs are also presented. Finally, a binary transistor-less memory cell which is only composed of a pair of RTDs and an ordinary rectifier diode is presented and investigated. A simple means for reading and writing information from or into the memory cell is also discussed.

  5. Hybrid caches: design and data management

    OpenAIRE

    Valero Bresó, Alejandro

    2013-01-01

    Cache memories have been usually implemented with Static Random-Access Memory (SRAM) technology since it is the fastest electronic memory technology. However, this technology consumes a high amount of leakage currents, which is a major design concern because leakage energy consumption increases as the transistor size shrinks. Alternative technologies are being considered to reduce this consumption. Among them, embedded Dynamic RAM (eDRAM) technology provides minimal area and le...

  6. SEU Prediction from SET modeling using multi-node collection in bulk transistors and SRAMs down to the 65 nm technology node

    International Nuclear Information System (INIS)

    Artola, L.; Hubert, G.; Duzellier, S.; Artola, L.; Bezerra, F.; Warren, K.M.; Massengill, L.W.; Gaillardin, M.; Paillet, Ph.; Raine, M.; Girard, S.; Schrimpf, R.D.; Reed, R.A.; Weller, R.A.; Ahlbin, J.R.

    2011-01-01

    A new methodology of prediction for SEU is proposed based on SET modeling. The modeling of multi-node charge collection is performed using the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm. The predicted single event upset cross sections agree well with experimental data for SRAMs. (authors)

  7. Database architecture optimized for the new bottleneck: Memory access

    NARCIS (Netherlands)

    P.A. Boncz (Peter); S. Manegold (Stefan); M.L. Kersten (Martin)

    1999-01-01

    textabstractIn the past decade, advances in speed of commodity CPUs have far out-paced advances in memory latency. Main-memory access is therefore increasingly a performance bottleneck for many computer applications, including database systems. In this article, we use a simple scan test to show the

  8. Optimizing Database Architecture for the New Bottleneck: Memory Access

    NARCIS (Netherlands)

    S. Manegold (Stefan); P.A. Boncz (Peter); M.L. Kersten (Martin)

    2000-01-01

    textabstractIn the past decade, advances in speed of commodity CPUs have far out-paced advances in memory latency. Main-memory access is therefore increasingly a performance bottleneck for many computer applications, including database systems. In this article, we use a simple scan test to show the

  9. Introduction to magnetic random-access memory

    CERN Document Server

    Dieny, Bernard; Lee, Kyung-Jin

    2017-01-01

    Magnetic random-access memory (MRAM) is poised to replace traditional computer memory based on complementary metal-oxide semiconductors (CMOS). MRAM will surpass all other types of memory devices in terms of nonvolatility, low energy dissipation, fast switching speed, radiation hardness, and durability. Although toggle-MRAM is currently a commercial product, it is clear that future developments in MRAM will be based on spin-transfer torque, which makes use of electrons’ spin angular momentum instead of their charge. MRAM will require an amalgamation of magnetics and microelectronics technologies. However, researchers and developers in magnetics and in microelectronics attend different technical conferences, publish in different journals, use different tools, and have different backgrounds in condensed-matter physics, electrical engineering, and materials science. This book is an introduction to MRAM for microelectronics engineers written by specialists in magnetic mat rials and devices. It presents the bas...

  10. Application of reactors for testing neutron-induced upsets in commercial SRAMs

    International Nuclear Information System (INIS)

    Griffin, P.J.; Luera, T.F.; Sexton, F.W.; Cooper, P.J.; Karr, S.G.; Hash, G.L.; Fuller, E.

    1997-01-01

    Reactor neutron environments can be used to test/screen the sensitivity of unhardened commercial SRAMs to low-LET neutron-induced upset. Tests indicate both thermal/epithermal (< 1 keV) and fast neutrons can cause upsets in unhardened parts. Measured upset rates in reactor environments can be used to model the upset rate for arbitrary neutron spectra

  11. Process informed accurate compact modelling of 14-nm FinFET variability and application to statistical 6T-SRAM simulations

    OpenAIRE

    Wang, Xingsheng; Reid, Dave; Wang, Liping; Millar, Campbell; Burenkov, Alex; Evanschitzky, Peter; Baer, Eberhard; Lorenz, Juergen; Asenov, Asen

    2016-01-01

    This paper presents a TCAD based design technology co-optimization (DTCO) process for 14nm SOI FinFET based SRAM, which employs an enhanced variability aware compact modeling approach that fully takes process and lithography simulations and their impact on 6T-SRAM layout into account. Realistic double patterned gates and fins and their impacts are taken into account in the development of the variability-aware compact model. Finally, global process induced variability and local statistical var...

  12. Paging memory from random access memory to backing storage in a parallel computer

    Science.gov (United States)

    Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

    2013-05-21

    Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

  13. Susceptibility of Redundant Versus Singular Clock Domains Implemented in SRAM-Based FPGA TMR Designs

    Science.gov (United States)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2016-01-01

    We present the challenges that arise when using redundant clock domains due to their clock-skew. Radiation data show that a singular clock domain (DTMR) provides an improved TMR methodology for SRAM-based FPGAs over redundant clocks.

  14. 75 FR 14467 - In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing...

    Science.gov (United States)

    2010-03-25

    ... Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of... semiconductors and products containing same, including memory modules, by reason of infringement of certain... importation of certain dynamic random access memory semiconductors or products containing the same, including...

  15. More than a feeling: Emotional cues impact the access and experience of autobiographical memories.

    Science.gov (United States)

    Sheldon, Signy; Donahue, Julia

    2017-07-01

    Remembering is impacted by several factors of retrieval, including the emotional content of a memory cue. Here we tested how musical retrieval cues that differed on two dimensions of emotion-valence (positive and negative) and arousal (high and low)-impacted the following aspects of autobiographical memory recall: the response time to access a past personal event, the experience of remembering (ratings of memory vividness), the emotional content of a cued memory (ratings of event arousal and valence), and the type of event recalled (ratings of event energy, socialness, and uniqueness). We further explored how cue presentation affected autobiographical memory retrieval by administering cues of similar arousal and valence levels in a blocked fashion to one half of the tested participants, and randomly to the other half. We report three main findings. First, memories were accessed most quickly in response to musical cues that were highly arousing and positive in emotion. Second, we observed a relation between a cue and the elicited memory's emotional valence but not arousal; however, both the cue valence and arousal related to the nature of the recalled event. Specifically, high cue arousal led to lower memory vividness and uniqueness ratings, but cues with both high arousal and positive valence were associated with memories rated as more social and energetic. Finally, cue presentation impacted both how quickly and specifically memories were accessed and how cue valence affected the memory vividness ratings. The implications of these findings for views of how emotion directs the access to memories and the experience of remembering are discussed.

  16. Semantic Dementia Shows both Storage and Access Disorders of Semantic Memory

    Directory of Open Access Journals (Sweden)

    Yumi Takahashi

    2014-01-01

    Full Text Available Objective. Previous studies have shown that some patients with semantic dementia (SD have memory storage disorders, while others have access disorders. Here, we report three SD cases with both disorders. Methods. Ten pictures and ten words were prepared as visual stimuli to determine if the patients could correctly answer names and select pictures after hearing the names of items (Card Presentation Task, assessing memory storage disorder. In a second task, the viewing time was set at 20 or 300 msec (Momentary Presentation Task, evaluating memory access disorder using items for which correct answers were given in the first task. The results were compared with those for 6 patients with Alzheimer’s disease (AD. Results. The SD patients had lower scores than the AD group for both tasks, suggesting both storage and access disorders. The AD group had almost perfect scores on the Card Presentation Task but showed impairment on the Momentary Presentation Task, although to a lesser extent than the SD cases. Conclusions. These results suggest that SD patients have both storage and access disorders and have more severe access disorder than patients with AD.

  17. Impact of process variations and long term degradation on 6T-SRAM cells

    Directory of Open Access Journals (Sweden)

    Th. Fischer

    2007-06-01

    Full Text Available In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area. The rising electrical fields bring up reliability problems, such as hot carrier injection. Also other long term degradation mechanisms like Negative Bias Temperature Instability (NBTI come into the focus of circuit design.

    Along with process device parameter variations (threshold voltage, mobility, variations due to the degradation of devices form a big challenge for designers to build circuits that both yield high under the influence of process variations and remain functional with respect to long term device drift.

    In this work we present the influence of long term degradation and process variations on the performance of SRAM core-cells and parametric yield of SRAM arrays. For different use cases we show the performance degradation depending on temperature and supply voltage.

  18. Effect of STI stress on leakage and Vccmin of a sub-65 nm node low-power SRAM

    International Nuclear Information System (INIS)

    Lee, T-H; Fang, Y-K; Chiang, Y-T; Chiu, H Y; Chen, M-S; Cheng, Osbert

    2008-01-01

    In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and V ccmin of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and V ccmin of the devices in a 65 nm node SRAM cell significantly

  19. Attentional priorities and access to short-term memory

    DEFF Research Database (Denmark)

    Gillebert, Celine; Dyrholm, Mads; Vangkilde, Signe Allerup

    2012-01-01

    The intraparietal sulcus (IPS) has been implicated in selective attention as well as visual short-term memory (VSTM). To contrast mechanisms of target selection, distracter filtering, and access to VSTM, we combined behavioral testing, computational modeling and functional magnetic resonance......, thereby displaying a significant interaction between the two factors. The interaction between target and distracter set size in IPS could not be accounted for by a simple explanation in terms of number of items accessing VSTM. Instead, it led us to a model where items accessing VSTM receive differential...

  20. Memory accessibility shapes explanation: Testing key claims of the inherence heuristic account.

    Science.gov (United States)

    Hussak, Larisa J; Cimpian, Andrei

    2018-01-01

    People understand the world by constructing explanations for what they observe. It is thus important to identify the cognitive processes underlying these judgments. According to a recent proposal, everyday explanations are often constructed heuristically: Because people need to generate explanations on a moment-by-moment basis, they cannot perform an exhaustive search through the space of possible reasons, but may instead use the information that is most easily accessible in memory (Cimpian & Salomon 2014a, b). In the present research, we tested two key claims of this proposal that have so far not been investigated. First, we tested whether-as previously hypothesized-the information about an entity that is most accessible in memory tends to consist of inherent or intrinsic facts about that entity, rather than extrinsic (contextual, historical, etc.) facts about it (Studies 1 and 2). Second, we tested the implications of this difference in the memory accessibility of inherent versus extrinsic facts for the process of generating explanations: Does the fact that inherent facts are more accessible than relevant extrinsic facts give rise to an inherence bias in the content of the explanations generated (Studies 3 and 4)? The findings supported the proposal that everyday explanations are generated in part via a heuristic process that relies on easily accessible-and often inherent-information from memory.

  1. Mechanism and modelling of source/drain asymmetry variation in 65 nm CMOS devices for SRAM and logic applications

    International Nuclear Information System (INIS)

    Lee, T H; Fang, Y K; Chiang, Y T; Lin, C T; Chen, M S; Cheng, O

    2008-01-01

    The source/drain asymmetry variation of 65 nm CMOS devices for SRAM and logic applications has been investigated in detail. For the first time, we observe that the asymmetry variation is proportional to the inverse of the root square of the device area. In other words, the asymmetry variation should become worse for future advanced CMOS technologies. Fortunately, through the T-CAD simulations and experiments, we find the variation can be improved significantly with the optimization of the poly-gate grain size, extra laser annealing and using a vertical profile poly-gate. Furthermore, the improvement in asymmetry variation leads to a better static noise margin of SRAM

  2. Dataflow models for shared memory access latency analysis

    NARCIS (Netherlands)

    Staschulat, Jan; Bekooij, Marco Jan Gerrit

    2009-01-01

    Performance analysis of applications in multi-core platforms is challenging because of temporal interference while accessing shared resources. Especially, memory arbiters introduce a non-constant delay which signicantly in uences the execution time of a task. In this paper, we selected a

  3. Novel memory architecture for video signal processor

    Science.gov (United States)

    Hung, Jen-Sheng; Lin, Chia-Hsing; Jen, Chein-Wei

    1993-11-01

    An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.

  4. Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy

    NARCIS (Netherlands)

    Glein, Robert; Rittner, Florian; Becher, Andreas; Ziener, Daniel; Frickel, Jürgen; Teich, Jürgen; Heuberger, Albert

    2015-01-01

    In this paper, we evaluate the suitability of different SRAM-based FPGAs for harsh radiation environments (e.g., space). In particular, we compare the space-grade and radiation-hardened by design Virtex-5QV (XQR5VFX130) with the commercial off-the-shelf Kintex-7 (KC7K325T) from Xilinx. The

  5. Capacity of a dual enrollment system with two keys based on an SRAM-PUF

    NARCIS (Netherlands)

    Kusters, L.; Willems, F.M.J.

    2018-01-01

    We investigate the capacity of an SRAM-PUF based secrecy system that produces two secret keys during two consecutive enrollments. We determined the region of secret-key rates that are achievable and show that the total secret-key capacity is larger than for a single enrollment system. In our

  6. Making working memory work: the effects of extended practice on focus capacity and the processes of updating, forward access, and random access.

    Science.gov (United States)

    Price, John M; Colflesh, Gregory J H; Cerella, John; Verhaeghen, Paul

    2014-05-01

    We investigated the effects of 10h of practice on variations of the N-Back task to investigate the processes underlying possible expansion of the focus of attention within working memory. Using subtractive logic, we showed that random access (i.e., Sternberg-like search) yielded a modest effect (a 50% increase in speed) whereas the processes of forward access (i.e., retrieval in order, as in a standard N-Back task) and updating (i.e., changing the contents of working memory) were executed about 5 times faster after extended practice. We additionally found that extended practice increased working memory capacity as measured by the size of the focus of attention for the forward-access task, but not for variations where probing was in random order. This suggests that working memory capacity may depend on the type of search process engaged, and that certain working-memory-related cognitive processes are more amenable to practice than others. Copyright © 2014 Elsevier B.V. All rights reserved.

  7. Aspects of GPU perfomance in algorithms with random memory access

    Science.gov (United States)

    Kashkovsky, Alexander V.; Shershnev, Anton A.; Vashchenkov, Pavel V.

    2017-10-01

    The numerical code for solving the Boltzmann equation on the hybrid computational cluster using the Direct Simulation Monte Carlo (DSMC) method showed that on Tesla K40 accelerators computational performance drops dramatically with increase of percentage of occupied GPU memory. Testing revealed that memory access time increases tens of times after certain critical percentage of memory is occupied. Moreover, it seems to be the common problem of all NVidia's GPUs arising from its architecture. Few modifications of the numerical algorithm were suggested to overcome this problem. One of them, based on the splitting the memory into "virtual" blocks, resulted in 2.5 times speed up.

  8. In-flight and ground testing of single event upset sensitivity in static RAMs

    International Nuclear Information System (INIS)

    Johansson, K.; Dyreklev, P.; Granbom, B.; Calvet, C.; Fourtine, S.; Feuillatre, O.

    1998-01-01

    This paper presents the results from in-flight measurements of single event upsets (SEU) in static random access memories (SRAM) caused by the atmospheric radiation environment at aircraft altitudes. The memory devices were carried on commercial airlines at high altitude and mainly high latitudes. The SEUs were monitored by a Component Upset Test Equipment (CUTE), designed for this experiment. The in flight results are compared to ground based testing with neutrons from three different sources

  9. Neutron detection using soft errors in dynamic Random Access Memories

    International Nuclear Information System (INIS)

    Darambara, D.G.; Spyrou, N.M.

    1994-01-01

    The purpose of this paper is to present results from experiments that have been performed to show the memory cycle time dependence of the soft errors produced by the interaction of alpha particles with dynamic random access memory devices, with a view to using these as position sensitive detectors. Furthermore, a preliminary feasibility study being carried out indicates the use of dynamic RAMs as neutron detectors by the utilization of (n, α) capture reactions in a Li converter placed on the top of the active area of the memory chip. ((orig.))

  10. Effect of STI stress on leakage and V{sub ccmin} of a sub-65 nm node low-power SRAM

    Energy Technology Data Exchange (ETDEWEB)

    Lee, T-H; Fang, Y-K; Chiang, Y-T; Chiu, H Y; Chen, M-S [VLSI technology Lab., Institute of Microelectronics, EE Department, National Cheng Kung University, No. 1 University Road, Tainan, Taiwan, 701 (China); Cheng, Osbert [Central R and D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd II, Hsin-Chu, Taiwan 300 (China)], E-mail: ykfang@eembox.ee.ncku.edu.tw

    2008-10-07

    In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and V{sub ccmin} of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and V{sub ccmin} of the devices in a 65 nm node SRAM cell significantly.

  11. 75 FR 44283 - In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same...

    Science.gov (United States)

    2010-07-28

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-707] In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of a... importation of certain dynamic random access memory semiconductors and products containing same, including...

  12. Complex dynamics of semantic memory access in reading.

    Science.gov (United States)

    Baggio, Giosué; Fonseca, André

    2012-02-07

    Understanding a word in context relies on a cascade of perceptual and conceptual processes, starting with modality-specific input decoding, and leading to the unification of the word's meaning into a discourse model. One critical cognitive event, turning a sensory stimulus into a meaningful linguistic sign, is the access of a semantic representation from memory. Little is known about the changes that activating a word's meaning brings about in cortical dynamics. We recorded the electroencephalogram (EEG) while participants read sentences that could contain a contextually unexpected word, such as 'cold' in 'In July it is very cold outside'. We reconstructed trajectories in phase space from single-trial EEG time series, and we applied three nonlinear measures of predictability and complexity to each side of the semantic access boundary, estimated as the onset time of the N400 effect evoked by critical words. Relative to controls, unexpected words were associated with larger prediction errors preceding the onset of the N400. Accessing the meaning of such words produced a phase transition to lower entropy states, in which cortical processing becomes more predictable and more regular. Our study sheds new light on the dynamics of information flow through interfaces between sensory and memory systems during language processing.

  13. Visual inspection requirements for high-reliability random-access memories

    International Nuclear Information System (INIS)

    Andrade, A.; McHenery, J.

    1981-09-01

    Visual inspection requirements are given for random-access memories for deep-space satellite electronics. The requirements, based primarily on Military Standard 883B, are illustrated in the order of their manufacturing operation to clarify and facilitate inspection procedures

  14. Accessibility versus accuracy in retrieving spatial memory: evidence for suboptimal assumed headings.

    Science.gov (United States)

    Yerramsetti, Ashok; Marchette, Steven A; Shelton, Amy L

    2013-07-01

    Orientation dependence in spatial memory has often been interpreted in terms of accessibility: Object locations are encoded relative to a reference orientation that affords the most accurate access to spatial memory. An open question, however, is whether people naturally use this "preferred" orientation whenever recalling the space. We tested this question by asking participants to locate buildings on a familiar campus from various imagined locations, without specifying the heading to be assumed. We then used these pointing judgments to infer the approximate heading participants assumed at each location. Surprisingly, each location showed a unique assumed heading that was consistent across participants and seemed to reflect episodic or visual properties of the space. This result suggests that although locations are encoded relative to a reference orientation, other factors may influence how people choose to access the stored information and whether they appeal to long-term spatial memory or other more sensory-based stores. PsycINFO Database Record (c) 2013 APA, all rights reserved.

  15. Taxing working memory during retrieval of emotional memories does not reduce memory accessibility when cued with reminders

    Directory of Open Access Journals (Sweden)

    Kevin eVan Schie

    2015-02-01

    Full Text Available Earlier studies have shown that when individuals recall an emotional memory while simultaneously doing a demanding dual-task (e.g., playing Tetris, mental arithmetic, making eye movements, this reduces self-reported vividness and emotionality of the memory. These effects have been found up to one week later, but have largely been confined to self-report ratings. This study examined whether this dual-tasking intervention reduces memory performance (i.e., accessibility of emotional memories. Undergraduates (N = 60 studied word-image pairs and rated the retrieved image on vividness and emotionality when cued with the word. Then they viewed the cues and recalled the images with or without making eye movements. Finally, they re-rated the images on vividness and emotionality. Additionally, fragments from images from all conditions were presented and participants identified which fragment was paired earlier with which cue. Findings showed no effect of the dual-task manipulation on self-reported ratings and latency responses. Cued recall may not have been sufficient to elicit specific and continuous target retrieval for memory blurring to occur. The study demonstrates boundaries to the effects of the dual-tasking procedure.

  16. The effects of enactment and intention accessibility on prospective memory performance.

    Science.gov (United States)

    Schult, Janette C; Steffens, Melanie C

    2017-05-01

    The intention-superiority effect denotes faster response latencies to stimuli linked with a prospective memory task compared to stimuli linked with no prospective task or with a cancelled task. It is generally assumed that the increased accessibility of intention-related materials contributes to successful execution of prospective memory tasks at an appropriate opportunity. In two experiments we investigated the relationship between the intention-superiority effect and actual prospective memory performance under relatively realistic conditions. We also manipulated enactment versus observation encoding to further investigate the similarity in representations of enacted and to-be-enacted tasks. Additionally, Experiment 1 included a control condition to investigate the development of the intention-superiority effect over time. Participants were asked to perform prospective tasks at the end of the experiment to prepare the room for the next participant. They studied these preparatory tasks at the beginning of the experiment either by enacting them themselves or by observing the experimenter perform them. In Experiment 2, participants in a control condition did not intend to perform prospective tasks. We observed a smaller intention-superiority effect after enactment encoding than after observation encoding, but only if response latencies were assessed immediately before the prospective memory task. In addition, Experiment 2 suggested that the size of the intention-superiority effect is related to successful prospective memory performance, thus providing evidence for a functional relationship between accessibility and memory.

  17. SEU-hardened silicon bipolar and GaAs MESFET SRAM cells using local redundancy techniques

    International Nuclear Information System (INIS)

    Hauser, J.R.

    1992-01-01

    Silicon bipolar and GaAs FET SRAM's have proven to be more difficult to harden with respect to single-event upset mechanisms than have silicon CMOS SRAM's. This is a fundamental property of bipolar and JFET or MESFET device technologies which do not have a high-impedance, nonactive isolation between the control electrode and the current or voltage being controlled. All SEU circuit level hardening techniques applied at the local level must use some type of information storage redundancy so that information loss on one node due to an SEU event can be recovered from information stored elsewhere in the cell. In CMOS technologies, this can be achieved by the use of simple cross-coupling resistors, whereas in bipolar and FET technologies, no such simple approach is possible. Several approaches to the use of local redundancy in bipolar and FET technologies are discussed in this paper. At the expense of increased cell complexity and increased power consumption and write time, several approaches are capable of providing complete SEU hardness at the local cell level

  18. Artificial intelligence applications of fast optical memory access

    Science.gov (United States)

    Henshaw, P. D.; Todtenkopf, A. B.

    The operating principles and performance of rapid laser beam-steering (LBS) techniques are reviewed and illustrated with diagrams; their applicability to fast optical-memory (disk) access is evaluated; and the implications of fast access for the design of expert systems are discussed. LBS methods examined include analog deflection (source motion, wavefront tilt, and phased arrays), digital deflection (polarization modulation, reflectivity modulation, interferometric switching, and waveguide deflection), and photorefractive LBS. The disk-access problem is considered, and typical LBS requirements are listed as 38,000 beam positions, rotational latency 25 ms, one-sector rotation time 1.5 ms, and intersector space 87 microsec. The value of rapid access for increasing the power of expert systems (by permitting better organization of blocks of information) is illustrated by summarizing the learning process of the MVP-FORTH system (Park, 1983).

  19. Accessing information in working memory: Can the focus of attention grasp two elements at the same time?

    NARCIS (Netherlands)

    Oberauer, K.; Bialkova, S.E.

    2009-01-01

    Processing information in working memory requires selective access to a subset of working-memory contents by a focus of attention. Complex cognition often requires joint access to 2 items in working memory. How does the focus select 2 items? Two experiments with an arithmetic task and 1 with a

  20. PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Sanam Shahla Rizvi

    2009-12-01

    Full Text Available Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS. This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  1. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    Science.gov (United States)

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  2. Device simulation of charge collection and single-event upset

    International Nuclear Information System (INIS)

    Dodd, P.E.

    1996-01-01

    In this paper the author reviews the current status of device simulation of ionizing-radiation-induced charge collection and single-event upset (SEU), with an emphasis on significant results of recent years. The author presents an overview of device-modeling techniques applicable to the SEU problem and the unique challenges this task presents to the device modeler. He examines unloaded simulations of radiation-induced charge collection in simple p/n diodes, SEU in dynamic random access memories (DRAM's), and SEU in static random access memories (SRAM's). The author concludes with a few thoughts on future issues likely to confront the SEU device modeler

  3. Study of radiation effects on semiconductor devices

    International Nuclear Information System (INIS)

    Kuboyama, Satoshi; Shindou, Hiroyuki; Ikeda, Naomi; Iwata, Yoshiyuki; Murakami, Takeshi

    2004-01-01

    Fine structure of the recent semiconductor devices has made them more sensitive to the space radiation environment with trapped high-energy protons and heavy ions. A new failure mode caused by bulk damage had been reported on such devices with small structure, and its effect on commercial synchronous dynamic random access memory (SDRAMs) was analyzed from the irradiation test results performed at Heavy ion Medical Accelerator in Chiba (HIMAC). Single event upset (SEU) data of static random access memory (SRAMs) were also collected to establish the method of estimating the proton-induced SEU rate from the results of heavy ion irradiation tests. (authors)

  4. Novel circuits for radiation hardened memories

    International Nuclear Information System (INIS)

    Haraszti, T.P.; Mento, R.P.; Moyer, N.E.; Grant, W.M.

    1992-01-01

    This paper reports on implementation of large storage semiconductor memories which combine radiation hardness with high packing density, operational speed, and low power dissipation and require both hardened circuit and hardened process technologies. Novel circuits, including orthogonal shuffle type of write-read arrays, error correction by weighted bidirectional codes and associative iterative repair circuits, are proposed for significant improvements of SRAMs' immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mbit and 10-Mbit monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrad and a projected SEU rate of 1 x 10 - 12 error/bit/day. Using radiation hardened processing improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate

  5. Two transistor cluster DICE Cells with the minimum area for a hardened 28-nm CMOS and 65-nm SRAM layout design

    International Nuclear Information System (INIS)

    Stenin, V.Ya.; Stepanov, P.V.

    2015-01-01

    A hardened DICE cell layout design is based on the two spaced transistor clusters of the DICE cell each consisting of four transistors. The larger the distance between these two CMOS transistor clusters, the more robust the hardened DICE SRAM to Single Event Upsets. Some versions of the 28-nm and 65-nm DICE CMOS SRAM block composition have been suggested with minimum cluster distances of 2.27-2.32 mkm. The area of hardened 28-nm DICE CMOS cells is larger than the area of 28-nm 6T CMOS cells by a factor of 2.1 [ru

  6. Dynamic computing random access memory

    International Nuclear Information System (INIS)

    Traversa, F L; Bonani, F; Pershin, Y V; Di Ventra, M

    2014-01-01

    The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200–2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology. (paper)

  7. Integrated Optical Content Addressable Memories (CAM and Optical Random Access Memories (RAM for Ultra-Fast Address Look-Up Operations

    Directory of Open Access Journals (Sweden)

    Christos Vagionas

    2017-07-01

    Full Text Available Electronic Content Addressable Memories (CAM implement Address Look-Up (AL table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM cell and a 4-bit Matchline (ML configuration, supporting a third state of the “logical X” value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM memory access requests.

  8. Boosting the FM-Index on the GPU: Effective Techniques to Mitigate Random Memory Access.

    Science.gov (United States)

    Chacón, Alejandro; Marco-Sola, Santiago; Espinosa, Antonio; Ribeca, Paolo; Moure, Juan Carlos

    2015-01-01

    The recent advent of high-throughput sequencing machines producing big amounts of short reads has boosted the interest in efficient string searching techniques. As of today, many mainstream sequence alignment software tools rely on a special data structure, called the FM-index, which allows for fast exact searches in large genomic references. However, such searches translate into a pseudo-random memory access pattern, thus making memory access the limiting factor of all computation-efficient implementations, both on CPUs and GPUs. Here, we show that several strategies can be put in place to remove the memory bottleneck on the GPU: more compact indexes can be implemented by having more threads work cooperatively on larger memory blocks, and a k-step FM-index can be used to further reduce the number of memory accesses. The combination of those and other optimisations yields an implementation that is able to process about two Gbases of queries per second on our test platform, being about 8 × faster than a comparable multi-core CPU version, and about 3 × to 5 × faster than the FM-index implementation on the GPU provided by the recently announced Nvidia NVBIO bioinformatics library.

  9. Accessing Information in Working Memory: Can the Focus of Attention Grasp Two Elements at the Same Time?

    Science.gov (United States)

    Oberauer, Klaus; Bialkova, Svetlana

    2009-01-01

    Processing information in working memory requires selective access to a subset of working-memory contents by a focus of attention. Complex cognition often requires joint access to 2 items in working memory. How does the focus select 2 items? Two experiments with an arithmetic task and 1 with a spatial task investigate time demands for successive…

  10. Zero-leakage multiple key-binding scenarios for SRAM-PUF systems based on the XOR-method

    NARCIS (Netherlands)

    Kusters, C.J.; Ignatenko, T.; Willems, F.M.J.

    2016-01-01

    We show that the XOR-method based on linear error-correcting codes can be applied to achieve the secret-key capacity of binary-symmetric SRAM-PUFs. Then we focus on multiple key-bindings. We prove that no information is leaked by all the helper data about a single secret key both in the case where

  11. Zero-leakage multiple key-binding scenarios for SRAM-PUF systems based on the XOR-Method

    NARCIS (Netherlands)

    Kusters, C.J.; Ignatenko, T.; Willems, F.M.J.

    2016-01-01

    We show that the XOR-method based on linear error-correcting codes can be applied to achieve the secret-key capacity of binary-symmetric SRAM-PUFs. Then we focus on multiple key-bindings. We prove that no information is leaked by all the helper data about a single secret key both in the case where

  12. What versus where: Investigating how autobiographical memory retrieval differs when accessed with thematic versus spatial information.

    Science.gov (United States)

    Sheldon, Signy; Chu, Sonja

    2017-09-01

    Autobiographical memory research has investigated how cueing distinct aspects of a past event can trigger different recollective experiences. This research has stimulated theories about how autobiographical knowledge is accessed and organized. Here, we test the idea that thematic information organizes multiple autobiographical events whereas spatial information organizes individual past episodes by investigating how retrieval guided by these two forms of information differs. We used a novel autobiographical fluency task in which participants accessed multiple memory exemplars to event theme and spatial (location) cues followed by a narrative description task in which they described the memories generated to these cues. Participants recalled significantly more memory exemplars to event theme than to spatial cues; however, spatial cues prompted faster access to past memories. Results from the narrative description task revealed that memories retrieved via event theme cues compared to spatial cues had a higher number of overall details, but those recalled to the spatial cues were recollected with a greater concentration on episodic details than those retrieved via event theme cues. These results provide evidence that thematic information organizes and integrates multiple memories whereas spatial information prompts the retrieval of specific episodic content from a past event.

  13. Large Capacity of Conscious Access for Incidental Memories in Natural Scenes.

    Science.gov (United States)

    Kaunitz, Lisandro N; Rowe, Elise G; Tsuchiya, Naotsugu

    2016-09-01

    When searching a crowd, people can detect a target face only by direct fixation and attention. Once the target is found, it is consciously experienced and remembered, but what is the perceptual fate of the fixated nontarget faces? Whereas introspection suggests that one may remember nontargets, previous studies have proposed that almost no memory should be retained. Using a gaze-contingent paradigm, we asked subjects to visually search for a target face within a crowded natural scene and then tested their memory for nontarget faces, as well as their confidence in those memories. Subjects remembered up to seven fixated, nontarget faces with more than 70% accuracy. Memory accuracy was correlated with trial-by-trial confidence ratings, which implies that the memory was consciously maintained and accessed. When the search scene was inverted, no more than three nontarget faces were remembered. These findings imply that incidental memory for faces, such as those recalled by eyewitnesses, is more reliable than is usually assumed. © The Author(s) 2016.

  14. 75 FR 20564 - Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit...

    Science.gov (United States)

    2010-04-20

    ... DEPARTMENT OF COMMERCE International Trade Administration [C-580-851] Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit for Preliminary Results of Countervailing Duty... access memory semiconductors from the Republic of Korea, covering the period January 1, 2008 through...

  15. History and the future perspective of the ferroelectric memory; Kyoyudentai memory no rekishiteki haikei to tenbo

    Energy Technology Data Exchange (ETDEWEB)

    Tarui, Y [Waseda University, Tokyo (Japan)

    1998-10-01

    Development work is in progress on ferroelectric memory. The memory is a most suitable non-volatile memory which can be incorporated into IC cards, with its higher speed, lower voltage operation, smaller power consumption, and greater number of rewriting times than EEPROM, DRAM and SRAM. Taking as an opportunity the announcement on an experiment as performed by the authors to control semiconductor charge by using electric depolarization of ferroelectric materials, reports have been made one after another on experiments on thin metal films on TGS or BaTiO3, and experiments on semiconductor films formed on ferroelectric crystals or ceramics substrates by using vacuum deposition. In order to solve problems in ferroelectric materials, thin films of PZT and PLZT have emerged, whose good hysteresis characteristics have also been reported. Thereafter, an announcement was made on a material with bismuth layer like perovskite structure. The material is characterized with having very little film fatigue degradation after rewriting of about 10 {sup 12} times. In scaling a ferroelectric memory, if voltage is decreased in proportion with the size, the operation can be reduced proportionately according to the voltage reduction. This paper introduces a method to constitute a ferroelectric memory. 22 refs., 11 figs., 2 tabs.

  16. NRAM: a disruptive carbon-nanotube resistance-change memory

    Science.gov (United States)

    Gilmer, D. C.; Rueckes, T.; Cleveland, L.

    2018-04-01

    Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

  17. A Strategic Analysis in Dynamic Random Access Memory Industry in Taiwan

    OpenAIRE

    Chen, Yen-Chun

    2009-01-01

    The credit crisis and global economic recession have severely impacted on Integrated Circuit (IC) industry particularly in Dynamic Random Access Memory (DRAM) industry. The average selling price declined below the cost of chip and almost all memory producers are lack of cash flow. One of the global three 3 producers has been driven out of this industry and all Taiwanese DRAM vendors are facing to a dilemma on how they can survive through the economic recession and oversupply circumstance. Thi...

  18. Shared random access memory resource for multiprocessor real-time systems

    International Nuclear Information System (INIS)

    Dimmler, D.G.; Hardy, W.H. II

    1977-01-01

    A shared random-access memory resource is described which is used within real-time data acquisition and control systems with multiprocessor and multibus organizations. Hardware and software aspects are discussed in a specific example where interconnections are done via a UNIBUS. The general applicability of the approach is also discussed

  19. Remote direct memory access over datagrams

    Science.gov (United States)

    Grant, Ryan Eric; Rashti, Mohammad Javad; Balaji, Pavan; Afsahi, Ahmad

    2014-12-02

    A communication stack for providing remote direct memory access (RDMA) over a datagram network is disclosed. The communication stack has a user level interface configured to accept datagram related input and communicate with an RDMA enabled network interface card (NIC) via an NIC driver. The communication stack also has an RDMA protocol layer configured to supply one or more data transfer primitives for the datagram related input of the user level. The communication stack further has a direct data placement (DDP) layer configured to transfer the datagram related input from a user storage to a transport layer based on the one or more data transfer primitives by way of a lower layer protocol (LLP) over the datagram network.

  20. Dessign and Implementation of Hardened Reconfiguration Controller for Self-Healing Systems on SRAM-Based FPGAs

    OpenAIRE

    DERAKHSHAN, NASER

    2013-01-01

    As digital systems become large and complex, their dependability is getting more important, particularly in mission-critical and safety‐critical applications. Among various available platforms for implementing a digital system, SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly adopted in embedded systems due to their flexibility in achieving multiple requirements such as low cost, high performance, and fast turnaround time compared to Fixed Application Specific Integrated Cir...

  1. Evaluation of 90nm 6T-SRAM as physical unclonable function for secure key generation in wireless sensor nodes

    NARCIS (Netherlands)

    Selimis, G.; Konijnenburg, M.; Ashouei, M.; Huisken, J.; de Groot, H.; van der Leest, V.; Schrijen, G.-J.; van Hulst, M.; Tuyls, P.

    2011-01-01

    Due to the unattended nature of WSN (Wireless Sensor Network) deployment, each sensor can be subject to physical capture, cloning and unauthorized device alteration. In this paper, we use the embedded SRAM, often available on a wireless sensor node, for secure data (cryptographic keys, IDs)

  2. Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

    International Nuclear Information System (INIS)

    Ando, K.; Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

    2014-01-01

    Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed

  3. Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

    Science.gov (United States)

    Natsui, Masanori; Hanyu, Takahiro

    2018-04-01

    In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

  4. Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode

    Science.gov (United States)

    Seung, Hyun-Min; Kwon, Kyoung-Cheol; Lee, Gon-Sub; Park, Jea-Gun

    2014-10-01

    Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 105 s with a memory margin of 9.2 × 105, program/erase endurance cycles of >102 with a memory margin of 8.4 × 105, and bending-fatigue-free cycles of ˜1 × 103 with a memory margin (Ion/Ioff) of 3.3 × 105.

  5. The special role of item-context associations in the direct-access region of working memory.

    Science.gov (United States)

    Campoy, Guillermo

    2017-09-01

    The three-embedded-component model of working memory (WM) distinguishes three representational states corresponding to three WM regions: activated long-term memory, direct-access region (DAR), and focus of attention. Recent neuroimaging research has revealed that access to the DAR is associated with enhanced hippocampal activity. Because the hippocampus mediates the encoding and retrieval of item-context associations, it has been suggested that this hippocampal activation is a consequence of the fact that item-context associations are particularly strong and accessible in the DAR. This study provides behavioral evidence for this view using an item-recognition task to assess the effect of non-intentional encoding and maintenance of item-location associations across WM regions. Five pictures of human faces were sequentially presented in different screen locations followed by a recognition probe. Visual cues immediately preceding the probe indicated the location thereof. When probe stimuli appeared in the same location that they had been presented within the memory set, the presentation of the cue was expected to elicit the activation of the corresponding WM representation through the just-established item-location association, resulting in faster recognition. Results showed this same-location effect, but only for items that, according to their serial position within the memory set, were held in the DAR.

  6. Remote direct memory access

    Science.gov (United States)

    Archer, Charles J.; Blocksome, Michael A.

    2012-12-11

    Methods, parallel computers, and computer program products are disclosed for remote direct memory access. Embodiments include transmitting, from an origin DMA engine on an origin compute node to a plurality target DMA engines on target compute nodes, a request to send message, the request to send message specifying a data to be transferred from the origin DMA engine to data storage on each target compute node; receiving, by each target DMA engine on each target compute node, the request to send message; preparing, by each target DMA engine, to store data according to the data storage reference and the data length, including assigning a base storage address for the data storage reference; sending, by one or more of the target DMA engines, an acknowledgment message acknowledging that all the target DMA engines are prepared to receive a data transmission from the origin DMA engine; receiving, by the origin DMA engine, the acknowledgement message from the one or more of the target DMA engines; and transferring, by the origin DMA engine, data to data storage on each of the target compute nodes according to the data storage reference using a single direct put operation.

  7. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems.

    Science.gov (United States)

    Shehzad, Danish; Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models.

  8. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

    Directory of Open Access Journals (Sweden)

    Danish Shehzad

    2016-01-01

    Full Text Available Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models.

  9. Chemical insight into origin of forming-free resistive random-access memory devices

    KAUST Repository

    Wu, X.; Fang, Z.; Li, K.; Bosman, M.; Raghavan, N.; Li, X.; Yu, H. Y.; Singh, N.; Lo, G. Q.; Zhang, Xixiang; Pey, K. L.

    2011-01-01

    We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOxmultilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission

  10. Nanostructure-property relations for phase-change random access memory (PCRAM) line cells

    NARCIS (Netherlands)

    Kooi, B. J.; Oosthoek, J. L. M.; Verheijen, M. A.; Kaiser, M.; Jedema, F. J.; Gravesteijn, D. J.

    2012-01-01

    Phase-change random access memory (PCRAM) cells have been studied extensively using electrical characterization and rather limited by detailed structure characterization. The combination of these two characterization techniques has hardly been exploited and it is the focus of the present work.

  11. Experimental study on heavy-ion single event effect on nanometer DDR SRAM

    International Nuclear Information System (INIS)

    Luo Yinhong; Zhang Fengqi; Guo Hongxia; Zhou Hui; Wang Yanping; Zhang Keying

    2013-01-01

    Single event effect experimental study on 90 nm and 65 nm DDR SRAM were carried out, single event upset (SEU) cross section was discussed as a function of several parameters such as feature size, test pattern, incidence angle, supply voltage. Key influence factors and effect rule were analyzed. Feasibility of the current test method was discussed. Results indicate that, SEU cross section reduces as technologies scale down; the influence of test pattern and power supply on SEU cross section is small; tilt angle increases SEU cross section due to multiple upset increasement. The applicability of cosine tilt test method is correlative to ion species and linear energy transfer (LET) values. (authors)

  12. Light sensitivity of a one transistor-one capacitor memory cell when used as a micromirror actuator in projector applications

    Science.gov (United States)

    Huffman, James Douglas

    2001-11-01

    The most important issue facing the future business success of the Digital Micromirror Device or DMD™ produced by Texas Instruments is the cost of the actual device. As the business and consumer markets call for higher resolution displays, the array size will have to be increased to incorporate more pixels. The manufacturing costs associated with building these higher resolution displays follow an exponential relation with the number of pixels due to yield loss and reduced number of chips per silicon wafer. Each pixel is actuated by electrostatics that are provided by a memory cell that is built in the underlying silicon substrate. One way to decrease cost of the wafer is to change the memory cell architecture from a static random access configuration or SRAM to a dynamic random access configuration or DRAM. This change has the benefits of having fewer components per area and a lower metal density. This reduction in the component count and metal density has a dramatic effect on the yield of the memory array by reducing the particle sensitivity of the underlying cell. The main drawback to using a DRAM configuration in a display application is the light sensitivity of a charge storage device built in the silicon substrate. As the photons pass through the mechanical micromirrors and illuminate the DRAM cell, the effective electrostatic potential of the memory element used for the mirror actuation is reduced. This dissertation outlines the issues associated with the light sensitivity of a DRAM memory cell as the actuation element for a micromirror. The concept of charge depletion on a silicon capacitor due to recombination of photogenerated carriers is explored and experimentally verified. The effects of the reduced potential on the capacitor on the micromirror are also explored. Optical modeling is used to determine the incoming photon flux to determine the benefits of adding a charge recombination region as part of the DRAM memory cell. Several options are explored

  13. The accessibility of memory items in children’s working memory

    OpenAIRE

    Roome, Hannah; Towse, John

    2016-01-01

    This thesis investigates the processes and systems that support recall in working memory. In particular it seeks to apply ideas from the adult-based dual-memory framework (Unsworth & Engle, 2007b) that claims primary memory and secondary memory are independent contributors to working memory capacity. These two memory systems are described as domain-general processes that combine control of attention and basic memory abilities to retain information. The empirical contribution comprises five ex...

  14. Materials and Physics Challenges for Spin Transfer Torque Magnetic Random Access Memories

    Energy Technology Data Exchange (ETDEWEB)

    Heinonen, O.

    2014-10-05

    Magnetic random access memories utilizing the spin transfer torque effect for writing information are a strong contender for non-volatile memories scalable to the 20 nm node, and perhaps beyond. I will here examine how these devices behave as the device size is scaled down from 70 nm size to 20 nm. As device sizes go below ~50 nm, the size becomes comparable to intrinsic magnetic length scales and the device behavior does not simply scale with size. This has implications for the device design and puts additional constraints on the materials in the device.

  15. Administering an epoch initiated for remote memory access

    Science.gov (United States)

    Blocksome, Michael A; Miller, Douglas R

    2012-10-23

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  16. A dual V t disturb-free subthreshold SRAM with write-assist and read isolation

    Science.gov (United States)

    Bhatnagar, Vipul; Kumar, Pradeep; Pandey, Neeta; Pandey, Sujata

    2018-02-01

    This paper presents a new dual V t 8T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation (WARI). Also a faster write back scheme is proposed for the half selected cells. A high V t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read. Static noise margins for data read (RSNM), write (WSNM), read delay, write delay, data retention voltage (DRV), leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells, which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.

  17. Adult age differences in memory in relation to availability and accessibility of knowledge-based schemas.

    Science.gov (United States)

    Arbuckle, T Y; Vanderleck, V F; Harsany, M; Lapidus, S

    1990-03-01

    Three experiments investigated whether, over adulthood, the use of schemas to process and remember new information increases (developmental shift hypothesis), decreases (production deficiency hypothesis) or remains constant (age-invariance hypothesis). Effects of schema access were studied by having young, middle-aged, and old music experts and nonexperts recall information that was relevant or irrelevant to music (Experiment 1) and by comparing young and old participants' memory for prose passages when they knew or did not know the subject of the passage (Experiments 2 and 3). In each case, schema access facilitated memory equally across age levels, supporting the age-invariance hypothesis and implying that the basic structures and operations of memory do not necessarily change with age. Possible limits on the independence of age and schema utilization were considered in relation to the conditions under which each of the two alternative hypotheses might hold.

  18. [Effects of construct accessibility and self-schema on person memory].

    Science.gov (United States)

    Kitamura, H

    1991-10-01

    The present study investigated the relationship among construct accessibility, self-schema and person memory. Three hundred and thirty-four subjects received 40 behavioral descriptions of a stimulus person, consisting of eight specific behaviors on each of five trait-dimensions. Subjects also rated personality traits of their acquaintances and themselves on nine-point bipolar scales and ranked the importance of the five trait-dimensions. Weights, which subjects assigned to each of the five dimensions, were calculated as indices of construct accessibility. Self-schema scores of each subject were also calculated based on his/her ratings. Multiple regression analyses indicated that the dimensional weights and self-schema scores were positively correlated with the recall performance of the descriptions of the stimulus person. The schematics recalled significantly more descriptions than the aschematics, whether their self-schema was positive or negative. Subjects who had positive self-schema showed higher construct accessibility than the aschematics. It was argued that the relationship between construct accessibility and self-schema might be affected by motivational factors such as self-esteem.

  19. Different Steric-Twist-Induced Ternary Memory Characteristics in Nonconjugated Copolymers with Pendant Naphthalene and 1,8-Naphthalimide Moieties.

    Science.gov (United States)

    Wang, Ming; Li, Zhuang; Li, Hua; He, Jinghui; Li, Najun; Xu, Qingfeng; Lu, Jianmei

    2017-10-18

    Herein, novel random copolymers PMNN and PMNB were designed and synthesized, and the memory devices Al/PMNN and PMNB/ITO both exhibited ternary memory performance. The switching voltages of the OFF-ON1 and ON1-ON2 transitions for both memory devices are around -2.0 and -3.5 V, respectively, and the ON1/OFF, ON2/ON1 current ratios are both up to 10 3 . The observed tristable electrical conductivity switching could be attributed to field-induced conformational ordering of the naphthalene rings in the side chains, and subsequent charge trapping by 1,8-naphthalimide moieties. More interestingly, by adjusting the connection sites of 1,8-naphthalimide moieties to tune the steric-twist effect, different memory properties were achieved (PMNN showed nonvolatile write once, read many (WORM) memory behavior, whereas PMNB showed volatile static RAM (SRAM) memory behavior). This result will offer a guideline for the design of different high-performance multilevel memory devices by tuning the steric effects of the chemical moieties. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    Science.gov (United States)

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

  1. Nanoscale memory devices

    International Nuclear Information System (INIS)

    Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M

    2010-01-01

    This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO 2 . (topical review)

  2. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    Science.gov (United States)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  3. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    Science.gov (United States)

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  4. The dynamics of access to groups in working memory.

    Science.gov (United States)

    Farrell, Simon; Lelièvre, Anna

    2012-11-01

    The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the temporal pattern at input merely suggesting a basis for the pattern of output buffering. Three experiments are presented here that disentangle input structure from output buffering in serial recall. In Experiment 1, participants were asked to recall a subset of visually presented digits from a temporally grouped list in their original order, where either within-group position or group position was kept constant. In Experiment 2, participants performed more standard serial recall of spoken digits, and input and output position were dissociated by asking participants to initiate recall from a post-cued position in the list. In Experiment 3, participants were asked to serially recall temporally grouped lists of visually presented digits where the grouping structure was unpredictable, under either articulatory suppression or silent conditions. The 3 experiments point to a tight linkage between implied memorial structures (i.e., the pattern of grouping at encoding) and the output structure implied by retrieval times and call into question a purely motoric account of the dynamics of recall.

  5. Cosmic and terrestrial single-event radiation effects in dynamic random access memories

    International Nuclear Information System (INIS)

    Massengill, L.W.

    1996-01-01

    A review of the literature on single-event radiation effects (SEE) on MOS integrated-circuit dynamic random access memories (DRAM's) is presented. The sources of single-event (SE) radiation particles, causes of circuit information loss, experimental observations of SE information upset, technological developments for error mitigation, and relationships of developmental trends to SE vulnerability are discussed

  6. Immigration, language proficiency, and autobiographical memories: Lifespan distribution and second-language access.

    Science.gov (United States)

    Esposito, Alena G; Baker-Ward, Lynne

    2016-08-01

    This investigation examined two controversies in the autobiographical literature: how cross-language immigration affects the distribution of autobiographical memories across the lifespan and under what circumstances language-dependent recall is observed. Both Spanish/English bilingual immigrants and English monolingual non-immigrants participated in a cue word study, with the bilingual sample taking part in a within-subject language manipulation. The expected bump in the number of memories from early life was observed for non-immigrants but not immigrants, who reported more memories for events surrounding immigration. Aspects of the methodology addressed possible reasons for past discrepant findings. Language-dependent recall was influenced by second-language proficiency. Results were interpreted as evidence that bilinguals with high second-language proficiency, in contrast to those with lower second-language proficiency, access a single conceptual store through either language. The final multi-level model predicting language-dependent recall, including second-language proficiency, age of immigration, internal language, and cue word language, explained ¾ of the between-person variance and (1)/5 of the within-person variance. We arrive at two conclusions. First, major life transitions influence the distribution of memories. Second, concept representation across multiple languages follows a developmental model. In addition, the results underscore the importance of considering language experience in research involving memory reports.

  7. Ga-doped indium oxide nanowire phase change random access memory cells

    International Nuclear Information System (INIS)

    Jin, Bo; Lee, Jeong-Soo; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I; Kim, Hyoung Seop; Meyyappan, M

    2014-01-01

    Phase change random access memory (PCRAM) devices are usually constructed using tellurium based compounds, but efforts to seek other materials providing desirable memory characteristics have continued. We have fabricated PCRAM devices using Ga-doped In 2 O 3 nanowires with three different Ga compositions (Ga/(In+Ga) atomic ratio: 2.1%, 11.5% and 13.0%), and investigated their phase switching properties. The nanowires (∼40 nm in diameter) can be repeatedly switched between crystalline and amorphous phases, and Ga concentration-dependent memory switching behavior in the nanowires was observed with ultra-fast set/reset rates of 80 ns/20 ns, which are faster than for other competitive phase change materials. The observations of fast set/reset rates and two distinct states with a difference in resistance of two to three orders of magnitude appear promising for nonvolatile information storage. Moreover, we found that increasing the Ga concentration can reduce the power consumption and resistance drift; however, too high a level of Ga doping may cause difficulty in achieving the phase transition. (paper)

  8. Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

    Science.gov (United States)

    Akkala, Arun Goud

    Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A

  9. Encoding and Retrieval Processes Involved in the Access of Source Information in the Absence of Item Memory

    Science.gov (United States)

    Ball, B. Hunter; DeWitt, Michael R.; Knight, Justin B.; Hicks, Jason L.

    2014-01-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were "related" to the target item but never actually studied.…

  10. Neutron-induced single event upsets in static RAMS observed at 10 km flight altitude

    International Nuclear Information System (INIS)

    Olsen, J.; Becher, P.E.; Fynbo, P.B.; Raaby, P. Schultz, J.

    1993-01-01

    Neutron induced single event upsets (SEUs) in static memory devices (SRAMs) have so far been seen only in laboratory environments. The authors report observations of 14 neutron induced SEUs at commercial aircraft flight altitudes as well. The observed SEU rate at 10 km flight altitude based on exposure of 160 standard 256 Kbit CMOS SRAMs is 4.8 · 10 -8 upsets/bit/day. In the laboratory 117 SRAMs of two different brands were irradiated with fast neutrons from a Pu-Be source. A total of 176 SEUs have been observed, among these are two SEU pairs. The upset rates from the laboratory tests are compared to those found in the airborne SRAMS

  11. DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

    Directory of Open Access Journals (Sweden)

    Sparsh Mittal

    2017-09-01

    Full Text Available To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM, spin transfer torque RAM (STT-RAM, phase change RAM (PCM and embedded DRAM (eDRAM and 2D memories designed using spin orbit torque RAM (SOT-RAM, domain wall memory (DWM and Flash memory. In addition to single-level cell (SLC designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2.

  12. ViSA: a neurodynamic model for visuo-spatial working memory, attentional blink, and conscious access.

    Science.gov (United States)

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-10-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one simultaneously in a spatially distributed fashion, the other sequentially at a single location. To understand their findings in a unified framework, we propose a neurodynamic model for Visual Selection and Awareness (ViSA). ViSA supports the view that neural representations for conscious access and visuo-spatial working memory are globally distributed and are based on recurrent interactions between perceptual and access control processors. Its flexible global workspace mechanisms enable a unitary account of a broad range of effects: It accounts for the limited storage capacity of visuo-spatial working memory, attentional cueing, and efficient selection with multi-object displays, as well as for the attentional blink and associated sparing and masking effects. In particular, the speed of consolidation for storage in visuo-spatial working memory in ViSA is not fixed but depends adaptively on the input and recurrent signaling. Slowing down of consolidation due to weak bottom-up and recurrent input as a result of brief presentation and masking leads to the attentional blink. Thus, ViSA goes beyond earlier 2-stage and neuronal global workspace accounts of conscious processing limitations. PsycINFO Database Record (c) 2012 APA, all rights reserved.

  13. Scandium doping brings speed improvement in Sb2Te alloy for phase change random access memory application.

    Science.gov (United States)

    Chen, Xin; Zheng, Yonghui; Zhu, Min; Ren, Kun; Wang, Yong; Li, Tao; Liu, Guangyu; Guo, Tianqi; Wu, Lei; Liu, Xianqiang; Cheng, Yan; Song, Zhitang

    2018-05-01

    Phase change random access memory (PCRAM) has gained much attention as a candidate for nonvolatile memory application. To develop PCRAM materials with better properties, especially to draw closer to dynamic random access memory (DRAM), the key challenge is to research new high-speed phase change materials. Here, Scandium (Sc) has been found it is helpful to get high-speed and good stability after doping in Sb 2 Te alloy. Sc 0.1 Sb 2 Te based PCRAM cell can achieve reversible switching by applying even 6 ns voltage pulse experimentally. And, Sc doping not only promotes amorphous stability but also improves the endurance ability comparing with pure Sb 2 Te alloy. Moreover, according to DFT calculations, strong Sc-Te bonds lead to the rigidity of Sc centered octahedrons, which may act as crystallization precursors in recrystallization process to boost the set speed.

  14. Shape memory alloy fixator system for suturing tissue in minimal access surgery.

    Science.gov (United States)

    Xu, W; Frank, T G; Stockham, G; Cuschieri, A

    1999-01-01

    A new technique for suturing human tissue is described in which tissue closure is achieved by means of small fixators made from shape memory alloy. The aim of the development is to provide an alternative to thread suturing in minimal access surgery, which is quicker and requires less skill to achieve the required suturing quality. The design of the fixators is described in terms of the thermal shape recovery of shape memory alloy and a novel form of finite element analysis, which uses a nonlinear elastic element for the material property. Thermal analysis of the fixators and surrounding tissue is used to predict the temperature distribution during and after the application of electric current heating. This was checked in an in vitro experiment, which confirmed that deployment caused no detectable collateral damage to surrounding tissue. In vivo animal studies on the use of the shape memory alloy fixator for suturing tissue are ongoing to establish safety and healing effects.

  15. Working memory capacity and controlled serial memory search.

    Science.gov (United States)

    Mızrak, Eda; Öztekin, Ilke

    2016-08-01

    The speed-accuracy trade-off (SAT) procedure was used to investigate the relationship between working memory capacity (WMC) and the dynamics of temporal order memory retrieval. High- and low-span participants (HSs, LSs) studied sequentially presented five-item lists, followed by two probes from the study list. Participants indicated the more recent probe. Overall, accuracy was higher for HSs compared to LSs. Crucially, in contrast to previous investigations that observed no impact of WMC on speed of access to item information in memory (e.g., Öztekin & McElree, 2010), recovery of temporal order memory was slower for LSs. While accessing an item's representation in memory can be direct, recovery of relational information such as temporal order information requires a more controlled serial memory search. Collectively, these data indicate that WMC effects are particularly prominent during high demands of cognitive control, such as serial search operations necessary to access temporal order information from memory. Copyright © 2016 Elsevier B.V. All rights reserved.

  16. Low-power resistive random access memory by confining the formation of conducting filaments

    International Nuclear Information System (INIS)

    Huang, Yi-Jen; Lee, Si-Chen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen

    2016-01-01

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO_x/silver nanoparticles/TiO_x/AlTiO_x, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO_x layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  17. Simulation of thermal-neutron-induced single-event upset using particle and heavy-ion transport code system

    International Nuclear Information System (INIS)

    Arita, Yutaka; Kihara, Yuji; Mitsuhasi, Junichi; Niita, Koji; Takai, Mikio; Ogawa, Izumi; Kishimoto, Tadafumi; Yoshihara, Tsutomu

    2007-01-01

    The simulation of a thermal-neutron-induced single-event upset (SEU) was performed on a 0.4-μm-design-rule 4 Mbit static random access memory (SRAM) using particle and heavy-ion transport code system (PHITS): The SEU rates obtained by the simulation were in very good agreement with the result of experiments. PHITS is a useful tool for simulating SEUs in semiconductor devices. To further improve the accuracy of the simulation, additional methods for tallying the energy deposition are required for PHITS. (author)

  18. Multiple social identities and stereotype threat: imbalance, accessibility, and working memory.

    Science.gov (United States)

    Rydell, Robert J; McConnell, Allen R; Beilock, Sian L

    2009-05-01

    In 4 experiments, the authors showed that concurrently making positive and negative self-relevant stereotypes available about performance in the same ability domain can eliminate stereotype threat effects. Replicating past work, the authors demonstrated that introducing negative stereotypes about women's math performance activated participants' female social identity and hurt their math performance (i.e., stereotype threat) by reducing working memory. Moving beyond past work, it was also demonstrated that concomitantly presenting a positive self-relevant stereotype (e.g., college students are good at math) increased the relative accessibility of females' college student identity and inhibited their gender identity, eliminating attendant working memory deficits and contingent math performance decrements. Furthermore, subtle manipulations in questions presented in the demographic section of a math test eliminated stereotype threat effects that result from women reporting their gender before completing the test. This work identifies the motivated processes through which people's social identities became active in situations in which self-relevant stereotypes about a stigmatized group membership and a nonstigmatized group membership were available. In addition, it demonstrates the downstream consequences of this pattern of activation on working memory and performance. Copyright (c) 2009 APA, all rights reserved.

  19. Main Memory

    OpenAIRE

    Boncz, Peter; Liu, Lei; Özsu, M.

    2008-01-01

    htmlabstractPrimary storage, presently known as main memory, is the largest memory directly accessible to the CPU in the prevalent Von Neumann model and stores both data and instructions (program code). The CPU continuously reads instructions stored there and executes them. It is also called Random Access Memory (RAM), to indicate that load/store instructions can access data at any location at the same cost, is usually implemented using DRAM chips, which are connected to the CPU and other per...

  20. Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

    International Nuclear Information System (INIS)

    Kim, Min-Hoi; Lee, Gyu Jeong; Keum, Chang-Min; Lee, Sin-Doo

    2014-01-01

    We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect transistor (OFET), being a selection transistor, and a ferroelectric OFET as a memory transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the selection transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on–off ratio and the high switching on–off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM. (paper)

  1. Random Access Memories: A New Paradigm for Target Detection in High Resolution Aerial Remote Sensing Images.

    Science.gov (United States)

    Zou, Zhengxia; Shi, Zhenwei

    2018-03-01

    We propose a new paradigm for target detection in high resolution aerial remote sensing images under small target priors. Previous remote sensing target detection methods frame the detection as learning of detection model + inference of class-label and bounding-box coordinates. Instead, we formulate it from a Bayesian view that at inference stage, the detection model is adaptively updated to maximize its posterior that is determined by both training and observation. We call this paradigm "random access memories (RAM)." In this paradigm, "Memories" can be interpreted as any model distribution learned from training data and "random access" means accessing memories and randomly adjusting the model at detection phase to obtain better adaptivity to any unseen distribution of test data. By leveraging some latest detection techniques e.g., deep Convolutional Neural Networks and multi-scale anchors, experimental results on a public remote sensing target detection data set show our method outperforms several other state of the art methods. We also introduce a new data set "LEarning, VIsion and Remote sensing laboratory (LEVIR)", which is one order of magnitude larger than other data sets of this field. LEVIR consists of a large set of Google Earth images, with over 22 k images and 10 k independently labeled targets. RAM gives noticeable upgrade of accuracy (an mean average precision improvement of 1% ~ 4%) of our baseline detectors with acceptable computational overhead.

  2. Atomic crystals resistive switching memory

    International Nuclear Information System (INIS)

    Liu Chunsen; Zhang David Wei; Zhou Peng

    2017-01-01

    Facing the growing data storage and computing demands, a high accessing speed memory with low power and non-volatile character is urgently needed. Resistive access random memory with 4F 2 cell size, switching in sub-nanosecond, cycling endurances of over 10 12 cycles, and information retention exceeding 10 years, is considered as promising next-generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory. (topical reviews)

  3. Daily Access to Sucrose Impairs Aspects of Spatial Memory Tasks Reliant on Pattern Separation and Neural Proliferation in Rats

    Science.gov (United States)

    Reichelt, Amy C.; Morris, Margaret J.; Westbrook, Reginald Frederick

    2016-01-01

    High sugar diets reduce hippocampal neurogenesis, which is required for minimizing interference between memories, a process that involves "pattern separation." We provided rats with 2 h daily access to a sucrose solution for 28 d and assessed their performance on a spatial memory task. Sucrose consuming rats discriminated between objects…

  4. Spectrotemporal processing drives fast access to memory traces for spoken words.

    Science.gov (United States)

    Tavano, A; Grimm, S; Costa-Faidella, J; Slabu, L; Schröger, E; Escera, C

    2012-05-01

    The Mismatch Negativity (MMN) component of the event-related potentials is generated when a detectable spectrotemporal feature of the incoming sound does not match the sensory model set up by preceding repeated stimuli. MMN is enhanced at frontocentral scalp sites for deviant words when compared to acoustically similar deviant pseudowords, suggesting that automatic access to long-term memory traces for spoken words contributes to MMN generation. Does spectrotemporal feature matching also drive automatic lexical access? To test this, we recorded human auditory event-related potentials (ERPs) to disyllabic spoken words and pseudowords within a passive oddball paradigm. We first aimed at replicating the word-related MMN enhancement effect for Spanish, thereby adding to the available cross-linguistic evidence (e.g., Finnish, English). We then probed its resilience to spectrotemporal perturbation by inserting short (20 ms) and long (120 ms) silent gaps between first and second syllables of deviant and standard stimuli. A significantly enhanced, frontocentrally distributed MMN to deviant words was found for stimuli with no gap. The long gap yielded no deviant word MMN, showing that prior expectations of word form limits in a given language influence deviance detection processes. Crucially, the insertion of a short gap suppressed deviant word MMN enhancement at frontocentral sites. We propose that spectrotemporal point-wise matching constitutes a core mechanism for fast serial computations in audition and language, bridging sensory and long-term memory systems. Copyright © 2012 Elsevier Inc. All rights reserved.

  5. Encoding and retrieval processes involved in the access of source information in the absence of item memory.

    Science.gov (United States)

    Ball, B Hunter; DeWitt, Michael R; Knight, Justin B; Hicks, Jason L

    2014-09-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were related to the target item but never actually studied. In Experiments 1 and 2, participants studied 1 category member (e.g., onion) from a variety of different categories and at test were presented with an unstudied category label (e.g., vegetable) to probe memory for item and source information. In Experiments 3 and 4, 1 member of unidirectional (e.g., credit or card) or bidirectional (e.g., salt or pepper) associates was studied, whereas the other unstudied member served as a test probe. When recall failed, source information was accessible only when items were processed deeply during encoding (Experiments 1 and 2) and when there was strong forward associative strength between the retrieval cue and target (Experiments 3 and 4). These findings suggest that a retrieval probe diagnostic of semantically related item information reinstantiates information bound in memory during encoding that results in reactivation of associated contextual information, contingent upon sufficient learning of the item itself and the association between the item and its context information.

  6. Materials selection for oxide-based resistive random access memories

    International Nuclear Information System (INIS)

    Guo, Yuzheng; Robertson, John

    2014-01-01

    The energies of atomic processes in resistive random access memories (RRAMs) are calculated for four typical oxides, HfO 2 , TiO 2 , Ta 2 O 5 , and Al 2 O 3 , to define a materials selection process. O vacancies have the lowest defect formation energy in the O-poor limit and dominate the processes. A band diagram defines the operating Fermi energy and O chemical potential range. It is shown how the scavenger metal can be used to vary the O vacancy formation energy, via controlling the O chemical potential, and the mean Fermi energy. The high endurance of Ta 2 O 5 RRAM is related to its more stable amorphous phase and the adaptive lattice rearrangements of its O vacancy

  7. 32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography

    Science.gov (United States)

    Greenway, Robert T.; Jeong, Kwangok; Kahng, Andrew B.; Park, Chul-Hong; Petersen, John S.

    2008-10-01

    As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography (HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that their electrical characteristics are comparable to those of existing bitcells.

  8. Random access dynamic memory device with capacity of 4Kx16 bytes

    International Nuclear Information System (INIS)

    Damatov, Ya.M.; Nikityuk, N.M.; Nomokonova, A.I.

    1980-01-01

    Random access dynamic memory devjce with capacity of 4Kx16 bytes is described. A block diagram, time diagrams and a general view of a unit are presented. Regimes os unit operation and ways of data regeneration are described. The analyser regime and a possibility of recording data from ''R'' buses of CAMAC dataway permit to use the unit efficiency in spectrometrical channels with a high intensity of experimental events arrival. The unit is developed on the basis of using large integral circuits

  9. Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

    Science.gov (United States)

    Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

    2018-04-01

    A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

  10. Direct access inter-process shared memory

    Science.gov (United States)

    Brightwell, Ronald B; Pedretti, Kevin; Hudson, Trammell B

    2013-10-22

    A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.

  11. Single memory with multiple shift register functionality

    NARCIS (Netherlands)

    2010-01-01

    The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A)

  12. Materials selection for oxide-based resistive random access memories

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Yuzheng; Robertson, John [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

    2014-12-01

    The energies of atomic processes in resistive random access memories (RRAMs) are calculated for four typical oxides, HfO{sub 2}, TiO{sub 2}, Ta{sub 2}O{sub 5}, and Al{sub 2}O{sub 3}, to define a materials selection process. O vacancies have the lowest defect formation energy in the O-poor limit and dominate the processes. A band diagram defines the operating Fermi energy and O chemical potential range. It is shown how the scavenger metal can be used to vary the O vacancy formation energy, via controlling the O chemical potential, and the mean Fermi energy. The high endurance of Ta{sub 2}O{sub 5} RRAM is related to its more stable amorphous phase and the adaptive lattice rearrangements of its O vacancy.

  13. Memory for Recently Accessed Visual Attributes

    Science.gov (United States)

    Jiang, Yuhong V.; Shupe, Joshua M.; Swallow, Khena M.; Tan, Deborah H.

    2016-01-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's…

  14. The contribution to immediate serial recall of rehearsal, search speed, access to lexical memory, and phonological coding: an investigation at the construct level.

    Science.gov (United States)

    Tehan, Gerald; Fogarty, Gerard; Ryan, Katherine

    2004-07-01

    Rehearsal speed has traditionally been seen to be the prime determinant of individual differences in memory span. Recent studies, in the main using young children as the participant population, have suggested other contributors to span performance. In the present research, we used structural equation modeling to explore, at the construct level, individual differences in immediate serial recall with respect to rehearsal, search, phonological coding, and speed of access to lexical memory. We replicated standard short-term phenomena; we showed that the variables that influence children's span performance influence adult performance in the same way; and we showed that speed of access to lexical memory and facility with phonological codes appear to be more potent sources of individual differences in immediate memory than is either rehearsal speed or search factors.

  15. Accessibility of observable and unobservable characteristics in autobiographical memories of recent and distant past.

    Science.gov (United States)

    Karylowski, Jerzy J; Mrozinski, Blazej

    2017-02-01

    Self-reports regarding how people visualise themselves during events that occurred in the past show that for events from the distant past individuals report assuming a more external perspective than for events from the recent past [Nigro, G., & Neisser, U. (1983). Point of view in personal memories. Cognitive Psychology, 15, 467-482; Pronin, E., & Ross, L. (2006). Temporal differences in trait self-ascription. Journal of Personality & Social Psychology, 90, 197-209]. Thus it appears that, with the passage of time, representations of self embodied in memories of past events lose their position of an insider and assume a more ordinary position of self as an object seen from the perspective of an outside observer. The purpose of the present experiment was to examine this shift using a performance-based measure of accessibility. Results showed that self-judgements regarding unobservable, covert characteristics were faster for recent-compared to more distant-autobiographical events. However, self-judgements regarding observable, overt characteristics were faster for more distant events. This suggests an accessibility-based mechanism underlying the shift from internal to the relatively more external perspective in forming self-images related to the distant past.

  16. 76 FR 2336 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Final Results of...

    Science.gov (United States)

    2011-01-13

    ... Semiconductors From the Republic of Korea: Final Results of Countervailing Duty Administrative Review AGENCY... administrative review of the countervailing duty order on dynamic random access memory semiconductors from the... to a change in the net subsidy rate. The final net subsidy rate for Hynix Semiconductor, Inc. is...

  17. Enabling Highly-Scalable Remote Memory Access Programming with MPI-3 One Sided

    Directory of Open Access Journals (Sweden)

    Robert Gerstenberger

    2014-01-01

    Full Text Available Modern interconnects offer remote direct memory access (RDMA features. Yet, most applications rely on explicit message passing for communications albeit their unwanted overheads. The MPI-3.0 standard defines a programming interface for exploiting RDMA networks directly, however, it's scalability and practicability has to be demonstrated in practice. In this work, we develop scalable bufferless protocols that implement the MPI-3.0 specification. Our protocols support scaling to millions of cores with negligible memory consumption while providing highest performance and minimal overheads. To arm programmers, we provide a spectrum of performance models for all critical functions and demonstrate the usability of our library and models with several application studies with up to half a million processes. We show that our design is comparable to, or better than UPC and Fortran Coarrays in terms of latency, bandwidth and message rate. We also demonstrate application performance improvements with comparable programming complexity.

  18. Emerging non-volatile memories

    CERN Document Server

    Hong, Seungbum; Wouters, Dirk

    2014-01-01

    This book is an introduction to the fundamentals of emerging non-volatile memories and provides an overview of future trends in the field. Readers will find coverage of seven important memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), Multiferroic RAM (MFRAM), Phase-Change Memories (PCM), Oxide-based Resistive RAM (RRAM), Probe Storage, and Polymer Memories. Chapters are structured to reflect diffusions and clashes between different topics. Emerging Non-Volatile Memories is an ideal book for graduate students, faculty, and professionals working in the area of non-volatile memory. This book also: Covers key memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), and Multiferroic RAM (MFRAM), among others. Provides an overview of non-volatile memory fundamentals. Broadens readers' understanding of future trends in non-volatile memories.

  19. Finite temperature simulation studies of spin-flop magnetic random access memory devices

    International Nuclear Information System (INIS)

    Chui, S.T.; Chang, C.-R.

    2006-01-01

    Spin-flop structures are currently being developed for magnetic random access memory devices. We report simulation studies of this system. We found the switching involves an intermediate edge-pinned domain state, similar to that observed in the single layer case. This switching scenario is quite different from that based on the coherent rotation picture. A significant temperature dependence of the switching field is observed. Our result suggests that the interplane coupling and thus the switching field has to be above a finite threshold for the spin-flop switching to be better than conventional switching methods

  20. Response of the Ubiquitin-Proteasome System to Memory Retrieval After Extended-Access Cocaine or Saline Self-Administration.

    Science.gov (United States)

    Werner, Craig T; Milovanovic, Mike; Christian, Daniel T; Loweth, Jessica A; Wolf, Marina E

    2015-12-01

    The ubiquitin-proteasome system (UPS) has been implicated in the retrieval-induced destabilization of cocaine- and fear-related memories in Pavlovian paradigms. However, nothing is known about its role in memory retrieval after self-administration of cocaine, an operant paradigm, or how the length of withdrawal from cocaine may influence retrieval mechanisms. Here, we examined UPS activity after an extended-access cocaine self-administration regimen that leads to withdrawal-dependent incubation of cue-induced cocaine craving. Controls self-administered saline. In initial experiments, memory retrieval was elicited via a cue-induced seeking/retrieval test on withdrawal day (WD) 50-60, when craving has incubated. We found that retrieval of cocaine- and saline-associated memories produced similar increases in polyubiquitinated proteins in the nucleus accumbens (NAc), compared with rats that did not undergo a seeking/retrieval test. Measures of proteasome catalytic activity confirmed similar activation of the UPS after retrieval of saline and cocaine memories. However, in a subsequent experiment in which testing was conducted on WD1, proteasome activity in the NAc was greater after retrieval of cocaine memory than saline memory. Analysis of other brain regions confirmed that effects of cocaine memory retrieval on proteasome activity, relative to saline memory retrieval, depend on withdrawal time. These results, combined with prior studies, suggest that the relationship between UPS activity and memory retrieval depends on training paradigm, brain region, and time elapsed between training and retrieval. The observation that mechanisms underlying cocaine memory retrieval change depending on the age of the memory has implications for development of memory destabilization therapies for cue-induced relapse in cocaine addicts.

  1. Fast, Accurate Memory Architecture Simulation Technique Using Memory Access Characteristics

    OpenAIRE

    小野, 貴継; 井上, 弘士; 村上, 和彰

    2007-01-01

    This paper proposes a fast and accurate memory architecture simulation technique. To design memory architecture, the first steps commonly involve using trace-driven simulation. However, expanding the design space makes the evaluation time increase. A fast simulation is achieved by a trace size reduction, but it reduces the simulation accuracy. Our approach can reduce the simulation time while maintaining the accuracy of the simulation results. In order to evaluate validity of proposed techniq...

  2. A Time-predictable Memory Network-on-Chip

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Chong, David VH; Puffitsch, Wolfgang

    2014-01-01

    To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for time-predictable memory...... arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without...

  3. Carbon nanomaterials for non-volatile memories

    Science.gov (United States)

    Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

    2018-03-01

    Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

  4. The content of visual working memory alters processing of visual input prior to conscious access: Evidence from pupillometry

    NARCIS (Netherlands)

    Gayet, S.; Paffen, C.L.E.; Guggenmos, M.; Sterzer, P.; Stigchel, S. van der

    2017-01-01

    Visual working memory (VWM) allows for keeping relevant visual information available after termination of its sensory input. Storing information in VWM, however, affects concurrent conscious perception of visual input: initially suppressed visual input gains prioritized access to consciousness when

  5. Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory

    Science.gov (United States)

    Yang, Xiang; Lu, Yang; Lee, Jongho; Chen, I.-Wei

    2016-01-01

    Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics for memory arrays.

  6. Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory

    International Nuclear Information System (INIS)

    Yang, Xiang; Lu, Yang; Lee, Jongho; Chen, I-Wei

    2016-01-01

    Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics for memory arrays

  7. Structural analysis of anodic porous alumina used for resistive random access memory

    International Nuclear Information System (INIS)

    Lee, Jeungwoo; Nigo, Seisuke; Kato, Seiichi; Kitazawa, Hideaki; Kido, Giyuu; Nakano, Yoshihiro

    2010-01-01

    Anodic porous alumina with duplex layers exhibits a voltage-induced switching effect and is a promising candidate for resistive random access memory. The nanostructural analysis of porous alumina is important for understanding the switching effect. We investigated the difference between the two layers of an anodic porous alumina film using transmission electron microscopy and electron energy-loss spectroscopy. Diffraction patterns showed that both layers are amorphous, and the electron energy-loss spectroscopy indicated that the inner layer contains less oxygen than the outer layer. We speculate that the conduction paths are mostly located in the oxygen-depleted area.

  8. An 'ADC-Memory' system based on a new principle in data access

    International Nuclear Information System (INIS)

    Pan Dajing; Wu Yongqing; Wang Shibo

    1990-01-01

    A new kind of 'ADC-Memory' (ADC-M) with real time correction of counting loss in dead time is now used in a multiuser data acquisition and processing system based on DUAL/68000 microcomputer. In data access, it replaces the 'DMA + 1' in classical MCA with the new method 'DMA + N', where N is weight factor of correction. The new method is based on the principle of virtual pulse generator. This method is superior to the correction by the software because the correction needn't take the computer time. Thus, this ADC-M can be used in the counting of high rate pulses

  9. State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

    Directory of Open Access Journals (Sweden)

    Yuanhui Ni

    2017-01-01

    Full Text Available Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.

  10. On the interplay between working memory consolidation and attentional selection in controlling conscious access : Parallel processing at a cost-a comment on 'The interplay of attention and consciousness in visual search, attentional blink and working memory consolidation'

    NARCIS (Netherlands)

    Wyble, Brad; Bowman, Howard; Nieuwenstein, Mark

    On the interplay between working memory consolidation and attentional selection in controlling conscious access: parallel processing at a cost-a comment on 'The interplay of attention and consciousness in visual search, attentional blink and working memory consolidation'

  11. NUMA obliviousness through memory mapping

    NARCIS (Netherlands)

    Gawade, M.; Kersten, M.; Pandis, I.; Kersten, M.

    2015-01-01

    With the rise of multi-socket multi-core CPUs a lot of effort is being put into how to best exploit their abundant CPU power. In a shared memory setting the multi-socket CPUs are equipped with their own memory module, and access memory modules across sockets in a non-uniform access pattern (NUMA).

  12. A novel multiplexer-based structure for random access memory cell in quantum-dot cellular automata

    Science.gov (United States)

    Naji Asfestani, Mazaher; Rasouli Heikalabad, Saeed

    2017-09-01

    Quantum-dot cellular automata (QCA) is a new technology in scale of nano and perfect replacement for CMOS circuits in the future. Memory is one of the basic components in any digital system, so designing the random access memory (RAM) with high speed and optimal in QCA is important. In this paper, by employing the structure of multiplexer, a novel RAM cell architecture is proposed. The proposed architecture is implemented without the coplanar crossover approach. The proposed architecture is simulated using the QCADesigner version 2.0.3 and QCAPro. The simulation results demonstrate that the proposed QCA RAM architecture has the best performance in terms of delay, circuit complexity, area, cell count and energy consumption in comparison with other QCA RAM architectures.

  13. Radiation Dosimetry Using Three-Dimensional Optical Random Access Memories

    International Nuclear Information System (INIS)

    Moscovitch, M.

    2001-01-01

    The ability to determine particle type and energy plays an important role in the dosimetry of heavy charged particles (HCP) and neutrons. A new approach to radiation dosimetry is presented, which is shown to be capable of particle type and energy discrimination. This method is based on utilizing radiation induced changes in the digital information stored on three-dimensional optical random access memories (3D ORAM). 3D ORAM is a small cube (a few mm 3 ) composed of poly(methyl methacrylate) doped with a photochromic dye, and it was originally proposed as a memory device in high speed parallel computers. A Nd:YAG laser system is used to write and read binary information (bits) on the ORAM, which functions as a charged particle detector. Both the read and the write processes use two laser beams that simultaneously strike the material to cause a color change at their intersection (similar to the darkening of light-sensitive sunglasses when exposed to sunlight.) The laser produces color changes in the ORAM, which then reverts to the original color (''bit-flips'') at sites where energy is deposited from interaction with incident HCP or neutron-recoil protons. The feasibility of this approach was demonstrated both theoretically and experimentally. Calculations based on track structure theory (TST) predict that when HCP interact with the ORAM material, the local energy deposition is capable of inducing measurable ''bit-flips''. These predictions were recently confirmed experimentally using two types of ORAM systems, one based on spirobenzopyran and the other on anthracene, as the photochromic dyes

  14. Radiation dosimetry using three-dimensional optical random access memories

    International Nuclear Information System (INIS)

    Moscovitch, M.; Phillips, G.W.; Cullum, B.M.; Mobley, J.; Bogard, J.S.; Emfietzoglou, D.; Vo-Dinh, T.

    2002-01-01

    The ability to determine particle type and energy plays an important role in the dosimetry of heavy charged particles (HCP) and neutrons. A new approach to radiation dosimetry is presented, which is shown to be capable of particle type and energy discrimination. This method is based on utilising radiation induced changes in the digital information stored on three-dimensional optical random access memories (3D ORAM). 3D ORAM is a small cube (a few mm 3 ) composed of poly(methyl methacrylate) doped with a photochromic dye, and it was originally proposed as a memory device in high speed parallel computers. A Nd:YAG laser system is used to write and read binary information (bits) on the ORAM, which functions as a charged particle detector. Both the read and the write processes use two laser beams that simultaneously strike the material to cause a colour change at their intersection (similar to the darkening of light-sensitive sunglasses when exposed to sunlight). The laser produces colour changes in the ORAM, which then reverts to the original colour ('bit-flips') at sites where energy is deposited from interaction with incident HCP or neutron-recoil protons. The feasibility of this approach was demonstrated both theoretically and experimentally. Calculations based on track structure theory predict that when HCP interact with the ORAM material, the local energy deposition is capable of inducing measurable 'bit-flips'. These predictions were recently confirmed experimentally using two types of ORAM systems, one based on spirobenzopyran and the other on anthracene, as the photochromic dyes. (author)

  15. Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

    Science.gov (United States)

    MacLeod, Todd; Ho, Fat D.

    2012-01-01

    The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere

  16. A model for Intelligent Random Access Memory architecture (IRAM) cellular automata algorithms on the Associative String Processing machine (ASTRA)

    CERN Document Server

    Rohrbach, F; Vesztergombi, G

    1997-01-01

    In the near future, the computer performance will be completely determined by how long it takes to access memory. There are bottle-necks in memory latency and memory-to processor interface bandwidth. The IRAM initiative could be the answer by putting Processor-In-Memory (PIM). Starting from the massively parallel processing concept, one reached a similar conclusion. The MPPC (Massively Parallel Processing Collaboration) project and the 8K processor ASTRA machine (Associative String Test bench for Research \\& Applications) developed at CERN \\cite{kuala} can be regarded as a forerunner of the IRAM concept. The computing power of the ASTRA machine, regarded as an IRAM with 64 one-bit processors on a 64$\\times$64 bit-matrix memory chip machine, has been demonstrated by running statistical physics algorithms: one-dimensional stochastic cellular automata, as a simple model for dynamical phase transitions. As a relevant result for physics, the damage spreading of this model has been investigated.

  17. Surface effects of electrode-dependent switching behavior of resistive random-access memory

    KAUST Repository

    Ke, Jr Jian

    2016-09-26

    The surface effects of ZnO-based resistive random-access memory (ReRAM) were investigated using various electrodes. Pt electrodes were found to have better performance in terms of the device\\'s switching functionality. A thermodynamic model of the oxygen chemisorption process was proposed to explain this electrode-dependent switching behavior. The temperature-dependent switching voltage demonstrates that the ReRAM devices fabricated with Pt electrodes have a lower activation energy for the chemisorption process, resulting in a better resistive switching performance. These findings provide an in-depth understanding of electrode-dependent switching behaviors and can serve as design guidelines for future ReRAM devices.

  18. Random access memory immune to single event upset using a T-resistor

    Science.gov (United States)

    Ochoa, Jr., Agustin

    1989-01-01

    In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

  19. Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs)

    Science.gov (United States)

    Sharma, Ashok K.; Teverovsky, Alexander

    2001-01-01

    Data retention and fatigue characteristics of 64 Kb lead zirconate titanate (PZT)-based Ferroelectric Random Access Memories (FRAMs) microcircuits manufactured by Ramtron were examined over temperature range from -85 C to +310 C for ceramic packaged parts and from -85 C to +175 C for plastic parts, during retention periods up to several thousand hours. Intrinsic failures, which were caused by a thermal degradation of the ferroelectric cells, occurred in ceramic parts after tens or hundreds hours of aging at temperatures above 200 C. The activation energy of the retention test failures was 1.05 eV and the extrapolated mean-time-to-failure (MTTF) at room temperature was estimated to be more than 280 years. Multiple write-read cycling (up to 3x10(exp 7)) during the fatigue testing of plastic and ceramic parts did not result in any parametric or functional failures. However, operational currents linearly decreased with the logarithm of number of cycles thus indicating fatigue process in PZT films. Plastic parts, that had more recent date code as compared to ceramic parts, appeared to be using die with improved process technology and showed significantly smaller changes in operational currents and data access times.

  20. A radiation-hardened 1K-bit dielectrically isolated random access memory

    International Nuclear Information System (INIS)

    Sandors, T.J.; Boarman, J.W.; Kasten, A.J.; Wood, G.M.

    1982-01-01

    Dielectric Isolation has been used for many years as the bipolar technology for latch-up free, radiation hardened integrated circuits in strategic systems. The state-of-the-art up to this point has been the manufacture of MSI functions containing a maximum of several hundred isolated components. This paper discusses a 1024 Bit Random Access Memory chip containing over 4000 dielectrically isolated components which has been designed for strategic radiation environments. The process utilized and the circuit design of the 1024 Bit RAM have been previously discussed. The techniques used are similar to those employed for the MX digital integrated circuits except for specific items required to make this a true LSI technology. These techniques, along with electrical and radiation data for the RAM, are presented

  1. High density submicron magnetoresistive random access memory (invited)

    Science.gov (United States)

    Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

    1999-04-01

    Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

  2. Selective memory retrieval can impair and improve retrieval of other memories.

    Science.gov (United States)

    Bäuml, Karl-Heinz T; Samenieh, Anuscheh

    2012-03-01

    Research from the past decades has shown that retrieval of a specific memory (e.g., retrieving part of a previous vacation) typically attenuates retrieval of other memories (e.g., memories for other details of the event), causing retrieval-induced forgetting. More recently, however, it has been shown that retrieval can both attenuate and aid recall of other memories (K.-H. T. Bäuml & A. Samenieh, 2010). To identify the circumstances under which retrieval aids recall, the authors examined retrieval dynamics in listwise directed forgetting, context-dependent forgetting, proactive interference, and in the absence of any induced memory impairment. They found beneficial effects of selective retrieval in listwise directed forgetting and context-dependent forgetting but detrimental effects in all the other conditions. Because context-dependent forgetting and listwise directed forgetting arguably reflect impaired context access, the results suggest that memory retrieval aids recall of memories that are subject to impaired context access but attenuates recall in the absence of such circumstances. The findings are consistent with a 2-factor account of memory retrieval and suggest the existence of 2 faces of memory retrieval. 2012 APA, all rights reserved

  3. Neutron detection using soft errors in dynamic random access memories

    International Nuclear Information System (INIS)

    Darambara, D.G.; Spyrou, N.M.

    1992-01-01

    The fact that energetic alpha particles have been observed to be capable of inducing single-event upsets in integrated circuit memories has become a topic of considerable interest in the past few years. One recognized difficulty with dynamic random access memory devices (dRAMs) is that the alpha-particle 'contamination' present within the dRAM encapsulating material interact sufficiently as to corrupt stored data. The authors essentially utilized the fact that these corruptions may be induced in dRAMs by the interaction of charged particles with the chip of the dRAM itself as a basis of a hardware system for neutron detection with a view to applications in neutron imaging and elemental analysis. The design incorporates a bank of dRAMs on which the particles are incident. Initially, these particles were alpha particles from an appropriate alpha-emitting source employed to assess system parameters. The sensitivity of the device to logic state upsets by ionizing radiation is a function of design and technology parameters, inducing storage node area, node capacitance, operating voltage, minority carrier lifetime, electric fields pattern in the bulk silicon, and specific device geometry. The soft error rate of the device in a given package depends on the flux of alphas, the energy spectrum, the distribution of incident angles, the target area, the total stored charge, the collection efficiency, the cell geometry, the supply voltage, the cycle and refreshing time, and the noise margin

  4. Nonvolatile memory design magnetic, resistive, and phase change

    CERN Document Server

    Li, Hai

    2011-01-01

    The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances,

  5. Information matching the content of visual working memory is prioritized for conscious access.

    Science.gov (United States)

    Gayet, Surya; Paffen, Chris L E; Van der Stigchel, Stefan

    2013-12-01

    Visual working memory (VWM) is used to retain relevant information for imminent goal-directed behavior. In the experiments reported here, we found that VWM helps to prioritize relevant information that is not yet available for conscious experience. In five experiments, we demonstrated that information matching VWM content reaches visual awareness faster than does information not matching VWM content. Our findings suggest a functional link between VWM and visual awareness: The content of VWM is recruited to funnel down the vast amount of sensory input to that which is relevant for subsequent behavior and therefore requires conscious access.

  6. An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

    Science.gov (United States)

    Cho, Hwasuk; Son, Hyunwoo; Seong, Kihwan; Kim, Byungsub; Park, Hong-June; Sim, Jae-Yoon

    2018-02-01

    This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine. The IC is fabricated using 28-nm CMOS process and is verified in a three-layer network of encoder-decoder pair for training and recovery of images with two-dimensional pixels. With a dataset of 50 digits, the IC shows a normalized root mean square error of 0.078. Measured energy efficiencies are 4.46 pJ per synaptic operation for inference and 19.26 pJ per synaptic weight update for learning, respectively. The learning performance is also estimated by simulations if the proposed hardware architecture is extended to apply to a batch training of 60 000 MNIST datasets.

  7. Chemical insight into origin of forming-free resistive random-access memory devices

    KAUST Repository

    Wu, X.

    2011-09-29

    We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOxmultilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission electron microscopy (HRTEM), along with electron energy loss spectroscopy(EELS)analysis has been carried out to identify the distribution and the role played by Ti in the RRAM stack. Our results show that Ti out-diffusion into the HfOx layer is the chemical cause of forming-free behavior. Moreover, the capability of Ti to change its ionic state in HfOx eases the reduction-oxidation (redox) reaction, thus lead to the RRAM devices performance improvements.

  8. Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM

    Science.gov (United States)

    Seo, Youngsoo; Kim, Shinkeun; Ko, Kyul; Woo, Changbeom; Kim, Minsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

    2018-02-01

    In this paper, electrical characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were analyzed for single transistor and 6T-SRAM cell through 3D technology computer-aided design (TCAD) simulation. In VFET, gate and extension lengths are not limited by the area of device because theses lengths are vertically located. The height of NP is assumed in 40 nm considering device fabrication method (top-down approach). According to the sizes of devices, we analyzed the performances of device such as total resistance, capacitance, intrinsic gate delay, sub-threshold swing (S.S), drain-induced barrier lowering (DIBL) and static noise margin (SNM). As the gate length becomes larger, the resistance should be smaller because the total height of NP is fixed in 40 nm. Also, when the channel thickness becomes thicker, the total resistance becomes smaller since the sheet resistances of channel and extension become smaller and the contact resistance becomes smaller due to the increasing contact area. In addition, as the length of channel pitch increases, the parasitic capacitance comes to be larger due to the increasing area of gate-drain and gate-source. The performance of RC delay is best in the shortest gate length (12 nm), the thickest channel (6 nm) and the shortest channel pitch (17 nm) owing to the reduced resistance and parasitic capacitance. However, the other performances such as DIBL, S.S, on/off ratio and SNM are worst because the short channel effect is highest in this situation. Also, we investigated the performance of the multi-channel device. As the number of channels increases, the performance of device and the reliability of SRAM improve because of reduced contact resistance, increased gate dimension and multi-channel compensation effect.

  9. Main Memory

    NARCIS (Netherlands)

    P.A. Boncz (Peter); L. Liu (Lei); M. Tamer Özsu

    2008-01-01

    htmlabstractPrimary storage, presently known as main memory, is the largest memory directly accessible to the CPU in the prevalent Von Neumann model and stores both data and instructions (program code). The CPU continuously reads instructions stored there and executes them. It is also called Random

  10. The Plateau de Bure ASTEP Platform Test in natural radiation environment of electronic components and circuits

    International Nuclear Information System (INIS)

    Autran, J.L.; Munteanu, D.; Sauze, S.; Roche, Ph.; Gasiot, G.; Borel, J.

    2010-01-01

    Reducing the size of microelectronic devices and increasing the integration density of circuits lead (following the famous Moore's law) to an increased sensitivity of circuits to natural terrestrial radiation environment. - Such sensitivity to atmospheric particles (mainly neutrons) can cause non-destructive (soft-errors) or destructive (latch-up) failures in most electronic circuits, including volatile static memories (SRAM), object of the research work carried out since 2004 on the European Test Platform ASTER. - This paper presents in details the ASTEP platform, its location, the instruments (neutron monitor of the Plateau de Bure) and the experiences (memory tester) currently installed on the Plateau de Bure. In a second part, we also report a synthesis of the key results concerning the natural radiation sensitivity of SRAM fabricated in 130 nm and 65 nm bulk silicon technologies. (authors)

  11. Fast memory with direct access for nuclear physics

    International Nuclear Information System (INIS)

    Alexandre, B.; Riou, C.; Veler, J.C.

    1967-07-01

    This memory with thin ferromagnetic layers initially devoted to code the spatial position of sparkles in a sonic chamber must allow to give a more general interest in nuclear physics. We study the organisation of the memory and we present a summary of its technical characteristics [fr

  12. Taxing Working Memory during Retrieval of Emotional Memories Does Not Reduce Memory Accessibility When Cued with Reminders

    NARCIS (Netherlands)

    van Schie, Kevin; Engelhard, Iris M; van den Hout, Marcel A

    2015-01-01

    Earlier studies have shown that when individuals recall an emotional memory while simultaneously doing a demanding dual-task [e.g., playing Tetris, mental arithmetic, making eye movements (EM)], this reduces self-reported vividness and emotionality of the memory. These effects have been found up to

  13. Overview of radiation effects on emerging non-volatile memory technologies

    Directory of Open Access Journals (Sweden)

    Fetahović Irfan S.

    2017-01-01

    Full Text Available In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. 171007

  14. Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory

    International Nuclear Information System (INIS)

    Huang Da; Wu Jun-Jie; Tang Yu-Hua

    2013-01-01

    With the progress of the semiconductor industry, the resistive random-access memory (RAM) has drawn increasing attention. The discovery of the memristor has brought much attention to this study. Research has focused on the resistive switching characteristics of different materials and the analysis of resistive switching mechanisms. We discuss the resistive switching mechanisms of different materials in this paper and analyze the differences of those mechanisms from the view point of circuitry to establish their respective circuit models. Finally, simulations are presented. We give the prospect of using different materials in resistive RAM on account of their resistive switching mechanisms, which are applied to explain their resistive switchings

  15. A random access memory immune to single event upset using a T-Resistor

    Science.gov (United States)

    Ochoa, A. Jr.

    1987-10-28

    In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

  16. Memory states in small arrays of Josephson junctions

    Energy Technology Data Exchange (ETDEWEB)

    Braiman, Yehuda [ORNLOak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Neschke, Brendan [ORNLOak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Nair, Niketh S. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Imam, Neena [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computing and Computational Science Directorat; Glowinski, R. [Univ. of Houston, TX (United States). Dept. of Mathematics

    2017-11-30

    Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

  17. Soft-error tolerance and energy consumption evaluation of embedded computer with magnetic random access memory in practical systems using computer simulations

    Science.gov (United States)

    Nebashi, Ryusuke; Sakimura, Noboru; Sugibayashi, Tadahiko

    2017-08-01

    We evaluated the soft-error tolerance and energy consumption of an embedded computer with magnetic random access memory (MRAM) using two computer simulators. One is a central processing unit (CPU) simulator of a typical embedded computer system. We simulated the radiation-induced single-event-upset (SEU) probability in a spin-transfer-torque MRAM cell and also the failure rate of a typical embedded computer due to its main memory SEU error. The other is a delay tolerant network (DTN) system simulator. It simulates the power dissipation of wireless sensor network nodes of the system using a revised CPU simulator and a network simulator. We demonstrated that the SEU effect on the embedded computer with 1 Gbit MRAM-based working memory is less than 1 failure in time (FIT). We also demonstrated that the energy consumption of the DTN sensor node with MRAM-based working memory can be reduced to 1/11. These results indicate that MRAM-based working memory enhances the disaster tolerance of embedded computers.

  18. Affect, accessibility of material in memory, and behavior: a cognitive loop?

    Science.gov (United States)

    Isen, A M; Shalker, T E; Clark, M; Karp, L

    1978-01-01

    Two studies investigated the effect of good mood on cognitive processes. In the first study, conducted in a shopping mall, a positive feeling state was induced by giving subjects a free gift, and good mood, thus induced, was found to improve subjects' evaluations of the performance and service records of products they owned. In the second study, in which affect was induced by having subjects win or lose a computer game in a laboratory setting, subjects who had won the game were found to be better able to recall positive material in memory. The results of the two studies are discussed in terms of the effect that feelings have on accessibility of cognitions. In addition, the nature of affect and the relationship between good mood and behavior (such as helping) are discussed in terms of this proposed cognitive process.

  19. Stream specificity and asymmetries in feature binding and content-addressable access in visual encoding and memory.

    Science.gov (United States)

    Huynh, Duong L; Tripathy, Srimant P; Bedell, Harold E; Ögmen, Haluk

    2015-01-01

    Human memory is content addressable-i.e., contents of the memory can be accessed using partial information about the bound features of a stored item. In this study, we used a cross-feature cuing technique to examine how the human visual system encodes, binds, and retains information about multiple stimulus features within a set of moving objects. We sought to characterize the roles of three different features (position, color, and direction of motion, the latter two of which are processed preferentially within the ventral and dorsal visual streams, respectively) in the construction and maintenance of object representations. We investigated the extent to which these features are bound together across the following processing stages: during stimulus encoding, sensory (iconic) memory, and visual short-term memory. Whereas all features examined here can serve as cues for addressing content, their effectiveness shows asymmetries and varies according to cue-report pairings and the stage of information processing and storage. Position-based indexing theories predict that position should be more effective as a cue compared to other features. While we found a privileged role for position as a cue at the stimulus-encoding stage, position was not the privileged cue at the sensory and visual short-term memory stages. Instead, the pattern that emerged from our findings is one that mirrors the parallel processing streams in the visual system. This stream-specific binding and cuing effectiveness manifests itself in all three stages of information processing examined here. Finally, we find that the Leaky Flask model proposed in our previous study is applicable to all three features.

  20. On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

    Science.gov (United States)

    Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

    2018-02-01

    In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

  1. A viable on-chip FPGA configuration memory scrubbing approach for CBM-ToF

    Energy Technology Data Exchange (ETDEWEB)

    Oancea, Andrei-Dumitru; Stuellein, Christian; Manz, Sebastian; Gebelein, Jano; Kebschull, Udo [Infrastruktur und Rechnersysteme in der Informationsverarbeitung (IRI), Goethe-Universitaet, Senckenberganlage 31, 60325 Frankfurt am Main (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    The ToF Detector of the CBM Experiment will be equipped with FPGA-based read-out boards (ROBs). These ROBs will be operated in a radiation environment, and therefore need a mitigation mechanism against soft errors in the SRAM-based configuration memories of the FPGAs. The proposed approach combines intrinsic on-chip single upset correction with extrinsic selective frame scrubbing for multiple-bit upsets. The slow control is realized using the GBT-SCA, which is capable of handling interrupts. This enables the new approach of event-driven configuration frame correction. While conventional blind scrubbing leads to a continuous load on the control path, the selective frame scrubbing reduces this load to a minimum. For verification purposes, radiation tests with a proton beam were performed at COSY, Juelich. The occurred soft errors were classified into single and multiple- bit upsets, enabling an estimation of the rate at which extrinsic intervention is necessary.

  2. One bipolar transistor selector - One resistive random access memory device for cross bar memory array

    Science.gov (United States)

    Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

    2017-09-01

    A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

  3. Dual representation of item positions in verbal short-term memory: Evidence for two access modes.

    Science.gov (United States)

    Lange, Elke B; Verhaeghen, Paul; Cerella, John

    Memory sets of N = 1~5 digits were exposed sequentially from left-to-right across the screen, followed by N recognition probes. Probes had to be compared to memory list items on identity only (Sternberg task) or conditional on list position. Positions were probed randomly or in left-to-right order. Search functions related probe response times to set size. Random probing led to ramped, "Sternbergian" functions whose intercepts were elevated by the location requirement. Sequential probing led to flat search functions-fast responses unaffected by set size. These results suggested that items in STM could be accessed either by a slow search-on-identity followed by recovery of an associated location tag, or in a single step by following item-to-item links in study order. It is argued that this dual coding of location information occurs spontaneously at study, and that either code can be utilised at retrieval depending on test demands.

  4. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    International Nuclear Information System (INIS)

    Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

    2002-01-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

  5. Remote Memory Access Protocol Target Node Intellectual Property

    Science.gov (United States)

    Haddad, Omar

    2013-01-01

    The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

  6. Working memory retrieval differences between medial temporal lobe epilepsy patients and controls: a three memory layer approach.

    Science.gov (United States)

    López-Frutos, José María; Poch, Claudia; García-Morales, Irene; Ruiz-Vargas, José María; Campo, Pablo

    2014-02-01

    Multi-store models of working memory (WM) have given way to more dynamic approaches that conceive WM as an activated subset of long-term memory (LTM). The resulting framework considers that memory representations are governed by a hierarchy of accessibility. The activated part of LTM holds representations in a heightened state of activation, some of which can reach a state of immediate accessibility according to task demands. Recent neuroimaging studies have studied the neural basis of retrieval information with different states of accessibility. It was found that the medial temporal lobe (MTL) was involved in retrieving information within immediate access store and outside this privileged zone. In the current study we further explored the contribution of MTL to WM retrieval by analyzing the consequences of MTL damage to this process considering the state of accessibility of memory representations. The performance of a group of epilepsy patients with left hippocampal sclerosis in a 12-item recognition task was compared with that of a healthy control group. We adopted an embedded model of WM that distinguishes three components: the activated LTM, the region of direct access, and a single-item focus of attention. Groups did not differ when retrieving information from single-item focus, but patients were less accurate retrieving information outside focal attention, either items from LTM or items expected to be in the WM range. Analyses focused on items held in the direct access buffer showed that consequences of MTL damage were modulated by the level of accessibility of memory representations, producing a reduced capacity. Copyright © 2013 The Authors. Published by Elsevier Inc. All rights reserved.

  7. Large-scale particle simulations in a virtual-memory computer

    International Nuclear Information System (INIS)

    Gray, P.C.; Wagner, J.S.; Tajima, T.; Million, R.

    1982-08-01

    Virtual memory computers are capable of executing large-scale particle simulations even when the memory requirements exceed the computer core size. The required address space is automatically mapped onto slow disc memory by the operating system. When the simulation size is very large, frequent random accesses to slow memory occur during the charge accumulation and particle pushing processes. Accesses to slow memory significantly reduce the execution rate of the simulation. We demonstrate in this paper that with the proper choice of sorting algorithm, a nominal amount of sorting to keep physically adjacent particles near particles with neighboring array indices can reduce random access to slow memory, increase the efficiency of the I/O system, and hence, reduce the required computing time

  8. Hand Shape Affects Access to Memories

    NARCIS (Netherlands)

    K. Dijkstra (Katinka); M.P. Kaschak; R.A. Zwaan (Rolf)

    2008-01-01

    textabstractThe present study examined the ways that body posture facilitated retrieval of autobiographical memories in more detail by focusing on two aspects of congruence in position of a specific body part: hand shape and hand orientation. Hand shape is important in the tactile perception and

  9. Feasibility of a neutron detector-dosemeter based on single-event upsets in dynamic random-access memories

    International Nuclear Information System (INIS)

    Phillips, G.W.; August, R.A.; Campbell, A.B.; Nelson, M.E.; Guardala, N.A.; Price, J.L.; Moscovitch, M.

    2002-01-01

    The feasibility was investigated of a solid-state neutron detector/dosemeter based on single-event upset (SEU) effects in dynamic random-access memories (DRAMs), commonly used in computer memories. Such a device, which uses a neutron converter material to produce a charged particle capable of causing an upset, would be light-weight, low-power, and could be read simply by polling the memory for bit flips. It would have significant advantages over standard solid-state neutron dosemeters which require off-line processing for track etching and analysis. Previous efforts at developing an SEU neutron detector/dosemeter have suffered from poor response, which can be greatly enhanced by selecting a modern high-density DRAM chip for SEU sensitivity and by using a thin 10 B film as a converter. Past attempts to use 10 B were not successful because the average alpha particle energy was insufficient to penetrate to the sensitive region of the memory. This can be overcome by removing the surface passivation layer before depositing the 10 B film or by implanting 10B directly into the chip. Previous experimental data show a 10 3 increase in neutron sensitivity by chips containing borosilicate glass, which could be used in an SEU detector. The results are presented of simulations showing that the absolute efficiency of an SEU neutron dosemeter can be increased by at least a factor of 1000 over earlier designs. (author)

  10. A Pilot Memory Café for People with Learning Disabilities and Memory Difficulties

    Science.gov (United States)

    Kiddle, Hannah; Drew, Neil; Crabbe, Paul; Wigmore, Jonathan

    2016-01-01

    Memory cafés have been found to normalise experiences of dementia and provide access to an accepting social network. People with learning disabilities are at increased risk of developing dementia, but the possible benefits of attending a memory café are not known. This study evaluates a 12-week pilot memory café for people with learning…

  11. System and method for programmable bank selection for banked memory subsystems

    Energy Technology Data Exchange (ETDEWEB)

    Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton on Hudson, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Hoenicke, Dirk (Seebruck-Seeon, DE); Ohmacht, Martin (Yorktown Heights, NY); Salapura, Valentina (Chappaqua, NY); Sugavanam, Krishnan (Mahopac, NY)

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  12. Attention, working memory, and phenomenal experience of WM content: memory levels determined by different types of top-down modulation

    OpenAIRE

    Jacob, Jane; Jacobs, Christianne; Silvanto, Juha

    2015-01-01

    What is the role of top-down attentional modulation in consciously accessing working memory (WM) content? In influential WM models, information can exist in different states, determined by allocation of attention; placing the original memory representation in the center of focused attention gives rise to conscious access. Here we discuss various lines of evidence indicating that such attentional modulation is not sufficient for memory content to be phenomenally experienced. We propose that, i...

  13. Uncorrelated multiple conductive filament nucleation and rupture in ultra-thin high-κ dielectric based resistive random access memory

    KAUST Repository

    Wu, Xing

    2011-08-29

    Resistive switching in transition metal oxides could form the basis for next-generation non-volatile memory (NVM). It has been reported that the current in the high-conductivity state of several technologically relevant oxide materials flows through localized filaments, but these filaments have been characterized only individually, limiting our understanding of the possibility of multiple conductive filaments nucleation and rupture and the correlation kinetics of their evolution. In this study, direct visualization of uncorrelated multiple conductive filaments in ultra-thin HfO2-based high-κ dielectricresistive random access memory (RRAM) device has been achieved by high-resolution transmission electron microscopy (HRTEM), along with electron energy loss spectroscopy(EELS), for nanoscale chemical analysis. The locations of these multiple filaments are found to be spatially uncorrelated. The evolution of these microstructural changes and chemical properties of these filaments will provide a fundamental understanding of the switching mechanism for RRAM in thin oxide films and pave way for the investigation into improving the stability and scalability of switching memory devices.

  14. Charge-Domain Signal Processing of Direct RF SamplingMixer with Discrete-Time Filters in Bluetooth and GSM Receivers

    NARCIS (Netherlands)

    Ho, Y.C.; Staszewski, R.B.; Muhammad, K.; Hung, C.M.; Leipold, D.; Maggio, K.

    2006-01-01

    RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental

  15. Attention, working memory, and phenomenal experience of WM content: memory levels determined by different types of top-down modulation.

    Science.gov (United States)

    Jacob, Jane; Jacobs, Christianne; Silvanto, Juha

    2015-01-01

    What is the role of top-down attentional modulation in consciously accessing working memory (WM) content? In influential WM models, information can exist in different states, determined by allocation of attention; placing the original memory representation in the center of focused attention gives rise to conscious access. Here we discuss various lines of evidence indicating that such attentional modulation is not sufficient for memory content to be phenomenally experienced. We propose that, in addition to attentional modulation of the memory representation, another type of top-down modulation is required: suppression of all incoming visual information, via inhibition of early visual cortex. In this view, there are three distinct memory levels, as a function of the top-down control associated with them: (1) Nonattended, nonconscious associated with no attentional modulation; (2) attended, phenomenally nonconscious memory, associated with attentional enhancement of the actual memory trace; (3) attended, phenomenally conscious memory content, associated with enhancement of the memory trace and top-down suppression of all incoming visual input.

  16. Transparent Memory For Harsh Electronics

    KAUST Repository

    Ho, C. H.; Duran Retamal, Jose Ramon; Yang, P. K.; Lee, C. P.; Tsai, M. L.; Kang, C. F.; He, Jr-Hau

    2017-01-01

    As a new class of non-volatile memory, resistive random access memory (RRAM) offers not only superior electronic characteristics, but also advanced functionalities, such as transparency and radiation hardness. However, the environmental tolerance

  17. NUMA obliviousness through memory mapping

    NARCIS (Netherlands)

    M.M. Gawade (Mrunal); M.L. Kersten (Martin)

    2015-01-01

    htmlabstractWith the rise of multi-socket multi-core CPUs a lot of effort is being put into how to best exploit their abundant CPU power. In a shared memory setting the multi-socket CPUs are equipped with their own memory module, and access memory modules across sockets in a non-uniform

  18. How intention and monitoring your thoughts influence characteristics of autobiographical memories.

    Science.gov (United States)

    Barzykowski, Krystian; Staugaard, Søren Risløv

    2018-05-01

    Involuntary autobiographical memories come to mind effortlessly and unintended, but the mechanisms of their retrieval are not fully understood. We hypothesize that involuntary retrieval depends on memories that are highly accessible (e.g., intense, unusual, recent, rehearsed), while the elaborate search that characterizes voluntary retrieval also produces memories that are mundane, repeated or distant - memories with low accessibility. Previous research provides some evidence for this 'threshold hypothesis'. However, in almost every prior study, participants have been instructed to report only memories while ignoring other thoughts. It is possible that such an instruction can modify the phenomenological characteristics of involuntary memories. This study aimed to investigate the effects of retrieval intentionality (i.e., wanting to retrieve a memory) and selective monitoring (i.e., instructions to report only memories) on the phenomenology of autobiographical memories. Participants were instructed to (1) intentionally retrieve autobiographical memories, (2) intentionally retrieve any type of thought (3) wait for an autobiographical memory to spontaneously appear, or (4) wait for any type of thought to spontaneously appear. They rated the mental content on a number of phenomenological characteristics both during retrieval and retrospectively following retrieval. The results support the prediction that highly accessible memories mostly enter awareness unintended and without selective monitoring, while memories with low accessibility rely on intention and selective monitoring. We discuss the implications of these effects. © 2017 The British Psychological Society.

  19. Retrieval Practice Enhances the Accessibility but not the Quality of Memory

    OpenAIRE

    Sutterer, David W.; Awh, Edward

    2016-01-01

    Numerous studies have demonstrated that retrieval from long term memory (LTM) can enhance subsequent memory performance, a phenomenon labeled the retrieval practice effect. However, the almost exclusive reliance on categorical stimuli in this literature leaves open a basic question about the nature of this improvement in memory performance. It has not yet been determined whether retrieval practice improves the probability of successful memory retrieval or the quality of the retrieved represen...

  20. Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

    Science.gov (United States)

    Tian, He; Chen, Hong-Yu; Ren, Tian-Ling; Li, Cheng; Xue, Qing-Tang; Mohammad, Mohammad Ali; Wu, Can; Yang, Yi; Wong, H-S Philip

    2014-06-11

    Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

  1. Neural Correlates of Conceptual Implicit Memory and Their Contamination of Putative Neural Correlates of Explicit Memory

    Science.gov (United States)

    Voss, Joel L.; Paller, Ken A.

    2007-01-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the…

  2. A multi-channel time-to-digital converter chip for drift chamber readout

    International Nuclear Information System (INIS)

    Santos, D.M.; Chau, A.; DeBusshere, D.; Dow, S.; Flasck, J.; Levi, M.; Kirsten, F.; Su, E.

    1995-12-01

    A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8μ triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz

  3. Stable switching of resistive random access memory on the nanotip array electrodes

    KAUST Repository

    Tsai, Kun-Tong

    2016-09-13

    The formation/rupture of conducting filaments (CFs) in resistive random access memory (ReRAM) materials tune the electrical conductivities non-volatilely and are largely affected by its material composition [1], internal configurations [2] and external environments [3,4]. Therefore, controlling repetitive formation/rupture of CF as well as the spatial uniformity of formed CF are fundamentally important for improving the resistive switching (RS) performance. In this context, we have shown that by adding a field initiator, typically a textured electrode, both performance and switching uniformity of ReRAMs can be improved dramatically [5]. In addition, despite its promising characteristics, the scalable fabrication and structural homogeneity of such nanostructured electrodes are still lacking or unattainable, making miniaturization of ReRAM devices an exceeding challenge. Here, we employ nanostructured electrode (nanotip arrays, extremely uniform) formed spontaneously via a self-organized process to improve the ZnO ReRAM switching characteristics.

  4. Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

    Science.gov (United States)

    Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

    2016-04-01

    The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

  5. Impact of thermal and intermediate energy neutrons on the semiconductor memories for the CERN accelerators

    CERN Document Server

    Cecchetto, Matteo; Gerardin, Simone

    A wide quantity of SRAM memories are employed along the Large Hadron Collider (LHC), the main CERN accelerator, and they are subjected to high levels of ionizing radiations which compromise the reliability of these devices. The Single Event Effect (SEE) qualification for components to be used in the complex high-energy accelerator at CERN relies on the characterization of two cross sections: 200-MeV protons and thermal neutrons. However, due to cost and time constraints, it is not always possible to characterize the SEE response of components to thermal neutrons, which is often regarded as negligible for components without borophosphosilicate glass (BPSG). Nevertheless, as recent studies show, the sensitivity of deep sub-micron technologies to thermal neutrons has increased owing to the presence of Boron 10 as a dopant and contact contaminant. The very large thermal neutron fluxes relative to high-energy hadron fluxes in some of the heavily shielded accelerator areas imply that even comparatively small therm...

  6. Massive parallel optical pattern recognition and retrieval via a two-stage high-capacity multichannel holographic random access memory system

    International Nuclear Information System (INIS)

    Cai, Luzhong; Liu, Hua-Kuang

    2000-01-01

    The multistage holographic optical random access memory (HORAM) system reported recently by Liu et al. provides a new degree of freedom for improving storage capacity. We further present a theoretical and practical analysis of the HORAM system with experimental results. Our discussions include the system design and geometrical requirements, its applications for multichannel pattern recognition and associative memory, the 2-D and 3-D information storage capacity, and multichannel image storage and retrieval via VanderLugt correlator (VLC) filters and joint transform holograms. A series of experiments are performed to demonstrate the feasibility of the multichannel pattern recognition and image retrieval with both the VLC and joint transform correlator (JTC) architectures. The experimental results with as many as 2025 channels show good agreement with the theoretical analysis. (c) 2000 Society of Photo-Optical Instrumentation Engineers

  7. Software Prefetching for Indirect Memory Accesses

    OpenAIRE

    Ainsworth, Sam; Jones, Timothy

    2017-01-01

    Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads are used to bring data into the cache hierarchy just before being required. However, these are difficult to insert to effectively improve performance, and techniques for automatic insertion are currently limited. This paper develops a novel compiler pass to automatically generate software prefetches for indirect mem...

  8. Retrieval practice enhances the accessibility but not the quality of memory.

    Science.gov (United States)

    Sutterer, David W; Awh, Edward

    2016-06-01

    Numerous studies have demonstrated that retrieval from long-term memory (LTM) can enhance subsequent memory performance, a phenomenon labeled the retrieval practice effect. However, the almost exclusive reliance on categorical stimuli in this literature leaves open a basic question about the nature of this improvement in memory performance. It has not yet been determined whether retrieval practice improves the probability of successful memory retrieval or the quality of the retrieved representation. To answer this question, we conducted three experiments using a mixture modeling approach (Zhang & Luck, 2008) that provides a measure of both the probability of recall and the quality of the recalled memories. Subjects attempted to memorize the color of 400 unique shapes. After every 10 images were presented, subjects either recalled the last 10 colors (the retrieval practice condition) by clicking on a color wheel with each shape as a retrieval cue or they participated in a control condition that involved no further presentations (Experiment 1) or restudy of the 10 shape/color associations (Experiments 2 and 3). Performance in a subsequent delayed recall test revealed a robust retrieval practice effect. Subjects recalled a significantly higher proportion of items that they had previously retrieved relative to items that were untested or that they had restudied. Interestingly, retrieval practice did not elicit any improvement in the precision of the retrieved memories. The same empirical pattern also was observed following delays of greater than 24 hours. Thus, retrieval practice increases the probability of successful memory retrieval but does not improve memory quality.

  9. Decoupled Access-Execute on ARM big.LITTLE

    OpenAIRE

    Weber, Anton

    2016-01-01

    Decoupled Access-Execute (DAE) presents a novel approach to improve power efficiency with a combination of compile-time transformations and Dynamic Voltage Frequency Scaling (DVFS). DAE splits regions of the program into two distinct phases: a memory-bound access phase and a compute-bound execute phase. DVFS is used to run the phases at different frequencies, thus conserving energy while caching data from main memory and performing computations at maximum performance. This project analyses th...

  10. Disk access controller for Multi 8 computer

    International Nuclear Information System (INIS)

    Segalard, Jean

    1970-01-01

    After having presented the initial characteristics and weaknesses of the software provided for the control of a memory disk coupled with a Multi 8 computer, the author reports the development and improvement of this controller software. He presents the different constitutive parts of the computer and the operation of the disk coupling and of the direct access to memory. He reports the development of the disk access controller: software organisation, loader, subprograms and statements

  11. Application of phase-change materials in memory taxonomy.

    Science.gov (United States)

    Wang, Lei; Tu, Liang; Wen, Jing

    2017-01-01

    Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other types of memory devices are rarely reported. Here we review the physical principles of phase-change materials and devices aiming to help researchers understand the concept of phase-change memory. We classify phase-change memory devices into phase-change optical disc, phase-change scanning probe memory, phase-change random access memory, and phase-change nanophotonic device, according to their locations in memory hierarchy. For each device type we discuss the physical principles in conjunction with merits and weakness for data storage applications. We also outline state-of-the-art technologies and future prospects.

  12. Context controls access to working and reference memory in the pigeon (Columba livia).

    Science.gov (United States)

    Roberts, William A; Macpherson, Krista; Strang, Caroline

    2016-01-01

    The interaction between working and reference memory systems was examined under conditions in which salient contextual cues were presented during memory retrieval. Ambient colored lights (red or green) bathed the operant chamber during the presentation of comparison stimuli in delayed matching-to-sample training (working memory) and during the presentation of the comparison stimuli as S+ and S- cues in discrimination training (reference memory). Strong competition between memory systems appeared when the same contextual cue appeared during working and reference memory training. When different contextual cues were used, however, working memory was completely protected from reference memory interference. © 2016 Society for the Experimental Analysis of Behavior.

  13. Memory hierarchy using row-based compression

    Science.gov (United States)

    Loh, Gabriel H.; O'Connor, James M.

    2016-10-25

    A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

  14. LHCb: Radiation tolerance tests of SRAM-based FPGAs for the possible usage in the readout electronics for the LHCb experiment

    CERN Multimedia

    Faerber, C; Wiedner, D; Leveringzon, B; Ekelhof, R

    2013-01-01

    This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfils the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of 10$^{-6}$ Hz makes the chip viable for the LHCb Upgrade.

  15. Large scale particle simulations in a virtual memory computer

    International Nuclear Information System (INIS)

    Gray, P.C.; Million, R.; Wagner, J.S.; Tajima, T.

    1983-01-01

    Virtual memory computers are capable of executing large-scale particle simulations even when the memory requirements exceeds the computer core size. The required address space is automatically mapped onto slow disc memory the the operating system. When the simulation size is very large, frequent random accesses to slow memory occur during the charge accumulation and particle pushing processes. Assesses to slow memory significantly reduce the excecution rate of the simulation. We demonstrate in this paper that with the proper choice of sorting algorithm, a nominal amount of sorting to keep physically adjacent particles near particles with neighboring array indices can reduce random access to slow memory, increase the efficiency of the I/O system, and hence, reduce the required computing time. (orig.)

  16. A Shared Scratchpad Memory with Synchronization Support

    DEFF Research Database (Denmark)

    Hansen, Henrik Enggaard; Maroun, Emad Jacob; Kristensen, Andreas Toftegaard

    2017-01-01

    Multicore processors usually communicate via shared memory, which is backed up by a shared level 2 cache and a cache coherence protocol. However, this solution is not a good fit for real-time systems, where we need to provide tight guarantees on execution and memory access times. In this paper, we...... propose a shared scratchpad memory as a time-predictable communication and synchronization structure, instead of the level 2 cache. The shared on-chip memory is accessed via a time division multiplexing arbiter, isolating the execution time of load and store instructions between processing cores....... Furthermore, the arbiter supports an extended time slot where an atomic load and store instruction can be executed to implement synchronization primitives. In the evaluation we show that a shared scratchpad memory is an efficient communication structure for a small number of processors; in our setup, 9 cores...

  17. Solution-processed flexible NiO resistive random access memory device

    Science.gov (United States)

    Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

    2018-04-01

    Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

  18. Measuring autobiographical fluency in the self-memory system.

    Science.gov (United States)

    Rathbone, Clare J; Moulin, Chris J A

    2014-01-01

    Autobiographical memory is widely considered to be fundamentally related to concepts of self and identity. However, few studies have sought to test models of self and memory directly using experimental designs. Using a novel autobiographical fluency paradigm, the present study investigated memory accessibility for different levels of self-related knowledge. Forty participants generated 20 "I am" statements about themselves, from which the 1st, 5th, 10th, 15th, and 20th were used as cues in a two-minute autobiographical fluency task. The most salient aspects of the self, measured by both serial position and ratings of personal significance, were associated with more accessible sets of autobiographical memories. This finding supports theories that view the self as a powerful organizational structure in memory. Results are discussed with reference to models of self and memory.

  19. Oscillatory mechanisms of process binding in memory.

    Science.gov (United States)

    Klimesch, Wolfgang; Freunberger, Roman; Sauseng, Paul

    2010-06-01

    A central topic in cognitive neuroscience is the question, which processes underlie large scale communication within and between different neural networks. The basic assumption is that oscillatory phase synchronization plays an important role for process binding--the transient linking of different cognitive processes--which may be considered a special type of large scale communication. We investigate this question for memory processes on the basis of different types of oscillatory synchronization mechanisms. The reviewed findings suggest that theta and alpha phase coupling (and phase reorganization) reflect control processes in two large memory systems, a working memory and a complex knowledge system that comprises semantic long-term memory. It is suggested that alpha phase synchronization may be interpreted in terms of processes that coordinate top-down control (a process guided by expectancy to focus on relevant search areas) and access to memory traces (a process leading to the activation of a memory trace). An analogous interpretation is suggested for theta oscillations and the controlled access to episodic memories. Copyright (c) 2009 Elsevier Ltd. All rights reserved.

  20. Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

    Directory of Open Access Journals (Sweden)

    James Boley

    2012-04-01

    Full Text Available The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write VMIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4–13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the unassisted test case.

  1. Forgetting: availability, accessibility, and intentional control problem

    Directory of Open Access Journals (Sweden)

    Veronika V. Nourkova

    2016-09-01

    Full Text Available The paper focuses on the phenomenon of forgetting as a primal and generally productive memory process. The cases that require a temporary and permanent forgetting of the material stored in the long-term memory are contrasted. The main methodological obstacle in forgetting research is identified as arising from the logical prohibition to argument from the negative, i.e. “the evidence of absence is not the evidence of absence”. Two mechanisms of forgetting are discussed in the paper: transformation of the memory trace and modulation of trace accessibility. The former mechanism of forgetting consists of memory trace destruction (memory trace decay, retroactive and proactive interference, and «catastrophic» interference or its transformation that leads to forming a new memory representation. We speculate that the most promising way to legitimize the trace destruction mechanism is narrowing the further research to episodic memory subsystem. The latter mechanism of forgetting consists of both passive failure in access to appropriate memory content (the tip of the tongue phenomenon, the category size effect, the fan effect and the process of active retrieval inhibition. This phenomenon represents temporary inhibition of competing semantically similar responses in semantic memory, and motivational inhibition of self-deprecating memories in autobiographical memory. Then we put into consideration a variety of experimental paradigms in intentional forgetting research. Contrary to the common claim that forgetting is а universal and homogeneous phenomenon, we propose that forgetting strategies might vary in different memory subsystems, and also depend on activity characteristics during encoding, storage and retrieval.

  2. Consciousness: physiological dependence on rapid memory access.

    Science.gov (United States)

    Hudson, Arthur J

    2009-01-01

    Consciousness develops from birth during the early months as the senses and other nervous system functions mature sufficiently to receive, process and store information. Among these is the ascending reticular activating (arousal) system in the brain stem that is responsible for wakefulness and was proposed by Penfield and Jasper more than 50 years ago as the "controlling mechanism for states of consciousness". This concept has remained the most advanced physiological interpretation of consciousness although recent developments offer greater insights into its nature. The ascending arousal system is the source of activation of the thalamocortical and cortical mechanisms for sensory input and facilitates the rapid matching of sensory input and the binding of memory during cognitive processing. Nonetheless, it is proposed that memory is the critical element through which our connection with the world exists without which, despite a fully functional arousal system, consciousness as we know it could not exist. Evidence is presented in support of this concept in addition to the physiological difficulties that must be resolved if consciousness is to be understood.

  3. Pattern imprinting in CMOS static RAMs from Co-60 irradiation

    International Nuclear Information System (INIS)

    Schott, J.T.; Zugich, M.H.

    1987-01-01

    Total dose irradiation of various CMOS SRAMs is shown to imprint the pattern stored in the memory during irradiation. This imprinted pattern is the preferred state of the memory at subsequent power-up. Imprinting can occur at dose levels significantly below the failure level of the devices and is consistent with the bias dependent radiation induced threshold shifts of the individual transistors of the memory cells. However, before total imprinting occurs, other unusual imprinting phenomena can occur, such as a reverse imprinting effect seen in SOS memories, which is probably related to the bias dependence of back-channel leakage

  4. Ion beam synthesis of indium-oxide nanocrystals for improvement of oxide resistive random-access memories

    Science.gov (United States)

    Bonafos, C.; Benassayag, G.; Cours, R.; Pécassou, B.; Guenery, P. V.; Baboux, N.; Militaru, L.; Souifi, A.; Cossec, E.; Hamga, K.; Ecoffey, S.; Drouin, D.

    2018-01-01

    We report on the direct ion beam synthesis of a delta-layer of indium oxide nanocrystals (In2O3-NCs) in silica matrices by using ultra-low energy ion implantation. The formation of the indium oxide phase can be explained by (i) the affinity of indium with oxygen, (ii) the generation of a high excess of oxygen recoils generated by the implantation process in the region where the nanocrystals are formed and (iii) the proximity of the indium-based nanoparticles with the free surface and oxidation from the air. Taking advantage of the selective diffusivity of implanted indium in SiO2 with respect to Si3N4, In2O3-NCs have been inserted in the SiO2 switching oxide of micrometric planar oxide-based resistive random access memory (OxRAM) devices fabricated using the nanodamascene process. Preliminary electrical measurements show switch voltage from high to low resistance state. The devices with In2O3-NCs have been cycled 5 times with identical operating voltages and RESET current meanwhile no switch has been observed for non implanted devices. This first measurement of switching is very promising for the concept of In2O3-NCs based OxRAM memories.

  5. Doped SbTe phase change material in memory cells

    NARCIS (Netherlands)

    in ‘t Zandt, M.A.A.; Jedema, F.J.; Gravesteijn, Dirk J; Gravesteijn, D.J.; Attenborough, K.; Wolters, Robertus A.M.

    2009-01-01

    Phase Change Random Access Memory (PCRAM) is investigated as replacement for Flash. The memory concept is based on switching a chalcogenide from the crystalline (low ohmic) to the amorphous (high ohmic) state and vice versa. Basically two memory cell concepts exist: the Ovonic Unified Memory (OUM)

  6. Aristotle: A performance Impact Indicator for the OpenCL Kernels Using Local Memory

    Directory of Open Access Journals (Sweden)

    Jianbin Fang

    2014-01-01

    Full Text Available Due to the increasing complexity of multi/many-core architectures (with their mix of caches and scratch-pad memories and applications (with different memory access patterns, the performance of many workloads becomes increasingly variable. In this work, we address one of the main causes for this performance variability: the efficiency of the memory system. Specifically, based on an empirical evaluation driven by memory access patterns, we qualify and partially quantify the performance impact of using local memory in multi/many-core processors. To do so, we systematically describe memory access patterns (MAPs in an application-agnostic manner. Next, for each identified MAP, we use OpenCL (for portability reasons to generate two microbenchmarks: a “naive” version (without local memory and “an optimized” version (using local memory. We then evaluate both of them on typically used multi-core and many-core platforms, and we log their performance. What we eventually obtain is a local memory performance database, indexed by various MAPs and platforms. Further, we propose a set of composing rules for multiple MAPs. Thus, we can get an indicator of whether using local memory is beneficial in the presence of multiple memory access patterns. This indication can be used to either avoid the hassle of implementing optimizations with too little gain or, alternatively, give a rough prediction of the performance gain.

  7. Individual differences in susceptibility to false memories: The effect of memory specificity.

    Science.gov (United States)

    Dewhurst, Stephen A; Anderson, Rachel J; Berry, Donna M; Garner, Sarah R

    2017-06-25

    Previous research has highlighted the wide individual variability in susceptibility to the false memories produced by the Deese/Roediger-McDermott (DRM) procedure [Deese, J. (1959). On the prediction of occurrence of particular verbal intrusions in immediate recall. Journal of Experimental Psychology, 58, 17-22; Roediger, H. L., III, & McDermott, K. B. (1995). Creating false memories: Remembering words not presented in lists. Journal of Experimental Psychology: Learning, Memory, & Cognition, 21, 803-814]. The current study investigated whether susceptibility to false memories is influenced by individual differences in the specificity of autobiographical memory retrieval. Memory specificity was measured using the Sentence Completion for Events from the Past Test (SCEPT) [Raes, F., Hermans, D., Williams, J. M. G., & Eelen, P. (2007). A sentence completion procedure as an alternative to the Autobiographical Memory Test for assessing overgeneral memory in non-clinical populations. Memory, 15, 495-507]. Memory specificity did not correlate with correct recognition, but a specific retrieval style was positively correlated with levels of false recognition. It is proposed that the contextual details that frequently accompany false memories of nonstudied lures are more accessible in individuals with specific retrieval styles.

  8. One-way shared memory

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    Standard multicore processors use the shared main memory via the on-chip caches for communication between cores. However, this form of communication has two limitations: (1) it is hardly time-predictable and therefore not a good solution for real-time systems and (2) this single shared memory...... is a bottleneck in the system. This paper presents a communication architecture for time-predictable multicore systems where core-local memories are distributed on the chip. A network-on-chip constantly copies data from a sender core-local memory to a receiver core-local memory. As this copying is performed...... in one direction we call this architecture a one-way shared memory. With the use of time-division multiplexing for the memory accesses and the network-on-chip routers we achieve a time-predictable solution where the communication latency and bandwidth can be bounded. An example architecture for a 3...

  9. A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

    Institute of Scientific and Technical Information of China (English)

    Mei-Ying Bian; Su-Kyung Yoon; Jeong-Geun Kim; Sangjae Nam; Shin-Dug Kim

    2016-01-01

    This research proposes a phase-change memory (PCM) based main memory system with an effective combi-nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

  10. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    International Nuclear Information System (INIS)

    Khan, Asif; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-01-01

    A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  11. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    Science.gov (United States)

    Khan, Asif; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-01

    A spintronic device, called the "strain assisted spin transfer torque (STT) random access memory (RAM)," is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  12. How intention and monitoring your thoughts influence characteristics of autobiographical memories

    DEFF Research Database (Denmark)

    Barzykowski, Krystian; Staugaard, Søren Risløv

    2018-01-01

    Involuntary autobiographical memories come to mind effortlessly and unintended, but the mechanisms of their retrieval are not fully understood. We hypothesize that involuntary retrieval depends on memories that are highly accessible (e.g., intense, unusual, recent, rehearsed), while the elaborate...... search that characterizes voluntary retrieval also produces memories that are mundane, repeated or distant – memories with low accessibility. Previous research provides some evidence for this ‘threshold hypothesis’. However, in almost every prior study, participants have been instructed to report only...... memories while ignoring other thoughts. It is possible that such an instruction can modify the phenomenological characteristics of involuntary memories. This study aimed to investigate the effects of retrieval intentionality (i.e., wanting to retrieve a memory) and selective monitoring (i.e., instructions...

  13. Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

    Science.gov (United States)

    Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

    2017-09-01

    Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  14. Nanoscale chemical state analysis of resistance random access memory device reacting with Ti

    Science.gov (United States)

    Shima, Hisashi; Nakano, Takashi; Akinaga, Hiro

    2010-05-01

    The thermal stability of the resistance random access memory material in the reducing atmosphere at the elevated temperature was improved by the addition of Ti. The unipolar resistance switching before and after the postdeposition annealing (PDA) process at 400 °C was confirmed in Pt/CoO/Ti(5 nm)/Pt device, while the severe degradation of the initial resistance occurs in the Pt/CoO/Pt and Pt/CoO/Ti(50 nm)/Pt devices. By investigating the chemical bonding states of Co, O, and Ti using electron energy loss spectroscopy combined with transmission electron microscopy, it was revealed that excess Ti induces the formation of metallic Co, while the thermal stability was improved by trace Ti. Moreover, it was indicated that the filamentary conduction path can be thermally induced after PDA in the oxide layer by analyzing electrical properties of the degraded devices. The adjustment of the reducing elements is quite essential in order to participate in their profits.

  15. Asymmetrical access to color and location in visual working memory.

    Science.gov (United States)

    Rajsic, Jason; Wilson, Daryl E

    2014-10-01

    Models of visual working memory (VWM) have benefitted greatly from the use of the delayed-matching paradigm. However, in this task, the ability to recall a probed feature is confounded with the ability to maintain the proper binding between the feature that is to be reported and the feature (typically location) that is used to cue a particular item for report. Given that location is typically used as a cue-feature, we used the delayed-estimation paradigm to compare memory for location to memory for color, rotating which feature was used as a cue and which was reported. Our results revealed several novel findings: 1) the likelihood of reporting a probed object's feature was superior when reporting location with a color cue than when reporting color with a location cue; 2) location report errors were composed entirely of swap errors, with little to no random location reports; and 3) both colour and location reports greatly benefitted from the presence of nonprobed items at test. This last finding suggests that it is uncertainty over the bindings between locations and colors at memory retrieval that drive swap errors, not at encoding. We interpret our findings as consistent with a representational architecture that nests remembered object features within remembered locations.

  16. A multi-channel time-to-digital converter chip for drift chamber readout

    International Nuclear Information System (INIS)

    Chau, A.; DeBusschere, D.; Dow, S.F.; Flasck, J.; Levi, M.E.; Kirsten, F.; Su, E.; Santos, D.M.

    1996-01-01

    A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e., 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 microm triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral nonlinearities of the TDC and the FADC are 230 ps and 9 mV, respectively

  17. Physical principles and current status of emerging non-volatile solid state memories

    Science.gov (United States)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  18. Active non-volatile memory post-processing

    Energy Technology Data Exchange (ETDEWEB)

    Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

    2017-04-11

    A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

  19. Magnetic vortex racetrack memory

    Science.gov (United States)

    Geng, Liwei D.; Jin, Yongmei M.

    2017-02-01

    We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

  20. Short-term memory to long-term memory transition in a nanoscale memristor.

    Science.gov (United States)

    Chang, Ting; Jo, Sung-Hyun; Lu, Wei

    2011-09-27

    "Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories. © 2011 American Chemical Society

  1. Influence of Thermal Annealing Treatment on Bipolar Switching Properties of Vanadium Oxide Thin-Film Resistance Random-Access Memory Devices

    Science.gov (United States)

    Chen, Kai-Huang; Cheng, Chien-Min; Kao, Ming-Cheng; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Wu, Sean; Su, Feng-Yi

    2017-04-01

    The bipolar switching properties and electrical conduction mechanism of vanadium oxide thin-film resistive random-access memory (RRAM) devices obtained using a rapid thermal annealing (RTA) process have been investigated in high-resistive status/low-resistive status (HRS/LRS) and are discussed herein. In addition, the resistance switching properties and quality improvement of the vanadium oxide thin-film RRAM devices were measured by x-ray diffraction (XRD) analysis, x-ray photoelectron spectrometry (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and current-voltage ( I- V) measurements. The activation energy of the hopping conduction mechanism in the devices was investigated based on Arrhenius plots in HRS and LRS. The hopping conduction distance and activation energy barrier were obtained as 12 nm and 45 meV, respectively. The thermal annealing process is recognized as a candidate method for fabrication of thin-film RRAM devices, being compatible with integrated circuit technology for nonvolatile memory devices.

  2. Age, memory type, and the phenomenology of autobiographical memory: findings from an Italian sample.

    Science.gov (United States)

    Montebarocci, Ornella; Luchetti, Martina; Sutin, Angelina R

    2014-01-01

    The present research explored differences in phenomenology between two types of memories, a general self-defining memory and an earliest childhood memory. A sample of 76 Italian participants were selected and categorised into two age groups: 20-30 years and 31-40 years. The Memory Experiences Questionnaire (MEQ) was administered, taking note of latency and duration times of the narratives. Consistent with the literature, the self-defining memory differed significantly from the earliest childhood memory in terms of phenomenology, with the recency of the memory associated with more intense phenomenological experience. The self-defining memory took longer to retrieve and narrate than the earliest childhood memory. Meaningful differences also emerged between the two age groups: Participants in their 30s rated their self-defining memory as more vivid, coherent, and accessible than participants in their 20s. According to latency findings, these differences suggest an expanded period of identity consolidation for younger adults. Further applications of the MEQ should be carried out to replicate these results with other samples of young adults.

  3. A 0.18-μm 3.3 V 16 k Bits 1R1T Phase Change Random Access Memory (PCRAM) Chip

    International Nuclear Information System (INIS)

    Sheng, Ding; Zhi-Tang, Song; Bo, Liu; Min, Zhu; Xiao-Gang, Chen; Yi-Feng, Chen; Ju, Shen; Cong, Fu; Song-Lin, Feng

    2008-01-01

    Using standard 0.18-μm CMOS process and the special platform for 8-inch phase change random access memory (PCRAM), the first Chinese 16k bits PCRAM chip has been successfully achieved. A 1R1T structure has been designed for low voltage drop and low cost compared to the 1R1D structure and the BJT-switch structure. Full integration of the 16k bits PCRAM chip, including memory cell, array structure, critical circuit module, and physical layout, has been designed and verified. The critical integration technology of the phase change material (PCM) fabrication and the standard CMOS process has been solved. Test results about PCM in a large-scale array have been generated for the next research of PCRAM chip

  4. Impact of Smoke Exposure on Digital Instrumentation and Control

    International Nuclear Information System (INIS)

    Tanaka, Tina J.; Nowlen, Steven P.; Korsah, Kofi; Wood, Richard T.; Antonescu, Christina E.

    2003-01-01

    Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke has been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All

  5. Providing the Public with Online Access to Large Bibliographic Data Bases.

    Science.gov (United States)

    Firschein, Oscar; Summit, Roger K.

    DIALOG, an interactive, computer-based information retrieval language, consists of a series of computer programs designed to make use of direct access memory devices in order to provide the user with a rapid means of identifying records within a specific memory bank. Using the system, a library user can be provided access to sixteen distinct and…

  6. Memory consolidation

    NARCIS (Netherlands)

    Takashima, A.; Bakker, I.; Schmid, H.-J.

    2016-01-01

    In order to make use of novel experiences and knowledge to guide our future behavior, we must keep large amounts of information accessible for retrieval. The memory system that stores this information needs to be flexible in order to rapidly incorporate incoming information, but also requires that

  7. Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

    Science.gov (United States)

    Tambara, Lucas Antunes; Tonfat, Jorge; Santos, André; Kastensmidt, Fernanda Lima; Medina, Nilberto H.; Added, Nemitala; Aguiar, Vitor A. P.; Aguirre, Fernando; Silveira, Marcilei A. G.

    2017-02-01

    The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.

  8. Multichannel analyzer using the direct-memory-access channel in a personal computer; Mnogokanal`nyj analizator v personal`nom komp`yutere, ispol`zuyushchij kanal pryamogo dostupa k pamyati

    Energy Technology Data Exchange (ETDEWEB)

    Georgiev, G; Vankov, I; Dimitrov, L [Incn. Yadernykh Issledovanij i Yadernoj Ehnergetiki Bolgarskoj Akademii Nuk, Sofiya (Bulgaria); Peev, I [Firma TOIVEL, Sofiya (Bulgaria)

    1996-12-31

    Paper describes a multichannel analyzer of the spectrometry data developed on the basis of a personal computer memory and a controlled channel of direct access. Analyzer software covering a driver and program of spectrum display control is studied. 2 figs.

  9. Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

    Science.gov (United States)

    Tonfat, Jorge; Kastensmidt, Fernanda Lima; Artola, Laurent; Hubert, Guillaume; Medina, Nilberto H.; Added, Nemitala; Aguiar, Vitor A. P.; Aguirre, Fernando; Macchione, Eduardo L. A.; Silveira, Marcilei A. G.

    2017-08-01

    This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

  10. Efficient Management for Hybrid Memory in Managed Language Runtime

    OpenAIRE

    Wang , Chenxi; Cao , Ting; Zigman , John; Lv , Fang; Zhang , Yunquan; Feng , Xiaobing

    2016-01-01

    Part 1: Memory: Non-Volatile, Solid State Drives, Hybrid Systems; International audience; Hybrid memory, which leverages the benefits of traditional DRAM and emerging memory technologies, is a promising alternative for future main memory design. However popular management policies through memory-access recording and page migration may invoke non-trivial overhead in execution time and hardware space. Nowadays, managed language applications are increasingly dominant in every kind of platform. M...

  11. Impulse: Memory System Support for Scientific Applications

    Directory of Open Access Journals (Sweden)

    John B. Carter

    1999-01-01

    Full Text Available Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application‐specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can improve the performance of memory‐bound scientific applications. For instance, Impulse decreases the running time of the NAS conjugate gradient benchmark by 67%. We expect that Impulse will also benefit regularly strided, memory‐bound applications of commercial importance, such as database and multimedia programs.

  12. Eye movement monitoring reveals differential influences of emotion on memory

    Directory of Open Access Journals (Sweden)

    Lily Riggs

    2010-11-01

    Full Text Available Research shows that memory for emotional aspects of an event may be enhanced at the cost of impaired memory for surrounding peripheral details. However, this has only been assessed directly via verbal reports which reveal the outcome of a long stream of processing but cannot shed light on how/when emotion may affect the retrieval process. In the present experiment, eye movement monitoring was used as an indirect measure of memory as it can reveal aspects of online memory processing. For example, do emotions modulate the nature of memory representations or the speed with which such memories can be accessed? Participants viewed central negative and neutral scenes surrounded by three neutral objects and after a brief delay, memory was assessed indirectly via eye movement monitoring and then directly via verbal reports. Consistent with the previous literature, emotion enhanced central and impaired peripheral memory as indexed by eye movement scanning and verbal reports. This suggests that eye movement scanning may contribute and/or is related to conscious access of memory. However, the central/peripheral tradeoff effect was not observed in an early measure of eye movement behavior, i.e. participants were faster to orient to a critical region of change in the periphery irrespective of whether it was previously studied in a negative or neutral context. These findings demonstrate emotion’s differential influences on different aspects of retrieval. In particular, emotion appears to affect the detail within, and/or the evaluation of, stored memory representations, but it may not affect the initial access to those representations.

  13. Magnetic vortex racetrack memory

    Energy Technology Data Exchange (ETDEWEB)

    Geng, Liwei D.; Jin, Yongmei M., E-mail: ymjin@mtu.edu

    2017-02-01

    We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications. - Highlights: • Advance fundamental knowledge of current-driven magnetic vortex phenomena. • Report appealing new magnetic racetrack memory based on current-controlled magnetic vortices in nanowires. • Provide a novel approach to adjust current magnitude for data propagation. • Overcome the limitations of domain wall racetrack memory.

  14. Customizable Memory Schemes for Data Parallel Architectures

    NARCIS (Netherlands)

    Gou, C.

    2011-01-01

    Memory system efficiency is crucial for any processor to achieve high performance, especially in the case of data parallel machines. Processing capabilities of parallel lanes will be wasted, when data requests are not accomplished in a sustainable and timely manner. Irregular vector memory accesses

  15. Full-switching FSF-type superconducting spin-triplet magnetic random access memory element

    Science.gov (United States)

    Lenk, D.; Morari, R.; Zdravkov, V. I.; Ullrich, A.; Khaydukov, Yu.; Obermeier, G.; Müller, C.; Sidorenko, A. S.; von Nidda, H.-A. Krug; Horn, S.; Tagirov, L. R.; Tidecks, R.

    2017-11-01

    In the present work a superconducting Co/CoOx/Cu41Ni59 /Nb/Cu41Ni59 nanoscale thin film heterostructure is investigated, which exhibits a superconducting transition temperature, Tc, depending on the history of magnetic field applied parallel to the film plane. In more detail, around zero applied field, Tc is lower when the field is changed from negative to positive polarity (with respect to the cooling field), compared to the opposite case. We interpret this finding as the result of the generation of the odd-in-frequency triplet component of superconductivity arising at noncollinear orientation of the magnetizations in the Cu41Ni59 layer adjacent to the CoOx layer. This interpretation is supported by superconducting quantum interference device magnetometry, which revealed a correlation between details of the magnetic structure and the observed superconducting spin-valve effects. Readout of information is possible at zero applied field and, thus, no permanent field is required to stabilize both states. Consequently, this system represents a superconducting magnetic random access memory element for superconducting electronics. By applying increased transport currents, the system can be driven to the full switching mode between the completely superconducting and the normal state.

  16. Simulation of Hamming Coding and Decoding for Microcontroller Radiation Hardening

    OpenAIRE

    Rehab I. Abdul Rahman; Mazhar B. Tayel

    2015-01-01

    This paper presents a method of hardening the 8051 micro-controller, able to assure reliable operation in the presence of bit flips caused by radiation. Aiming at avoiding such faults in the 8051 micro-controller, Hamming code protection was used in its SRAM memory and registers. A VHDL code has been used for this hamming code protection.

  17. Breaking the memory wall in MonetDB

    NARCIS (Netherlands)

    P.A. Boncz (Peter); M.L. Kersten (Martin); S. Manegold (Stefan)

    2008-01-01

    textabstractIn the past decades, advances in speed of commodity CPUs have far outpaced advances in RAM latency. Main-memory access has therefore become a performance bottleneck for many computer applications; a phenomenon that is widely known as the "memory wall." In this paper, we report how

  18. Generic database cost models for hierarchical memory systems

    NARCIS (Netherlands)

    S. Manegold (Stefan); P.A. Boncz (Peter); M.L. Kersten (Martin)

    2002-01-01

    textabstractAccurate prediction of operator execution time is a prerequisite fordatabase query optimization. Although extensively studied for conventionaldisk-based DBMSs, cost modeling in main-memory DBMSs is still an openissue. Recent database research has demonstrated that memory access ismore

  19. Difference in Subjective Accessibility of On Demand Recall of Visual, Taste, and Olfactory Memories

    Directory of Open Access Journals (Sweden)

    Petr Zach

    2018-01-01

    Full Text Available We present here significant difference in the evocation capability between sensory memories (visual, taste, and olfactory throughout certain categories of the population. As object for this memory recall we selected French fries that are simple and generally known. From daily life we may intuitively feel that there is much better recall of the visual and auditory memory compared to the taste and olfactory ones. Our results in young (age 12–21 years mostly females and some males show low capacity for smell and taste memory recall compared to far greater visual memory recall. This situation raises question whether we could train smell and taste memory recall so that it could become similar to visual or auditory ones. In our article we design technique of the volunteers training that could potentially lead to an increase in the capacity of their taste and olfactory memory recollection.

  20. A 32-bit computer for large memory applications on the FASTBUS

    International Nuclear Information System (INIS)

    Kellner, R.; Blossom, J.M.; Hung, J.P.

    1985-01-01

    A FASTBUS based 32-bit computer is being built at Los Alamos National Laboratory for use in systems requiring large fast memory in the FASTBUS environment. A separate local execution bus allows data reduction to proceed concurrently with other FASTBUS operations. The computer, which can operate in either master or slave mode, includes the National Semiconductor NS32032 chip set with demand paged memory management, floating point slave processor, interrupt control unit, timers, and time-of-day clock. The 16.0 megabytes of random access memory are interleaved to allow windowed direct memory access on and off the FASTBUS at 80 megabytes per second

  1. Breaking the memory wall in MonetDB

    NARCIS (Netherlands)

    Boncz, P.A.; Kersten, M.L.; Manegold, S.

    2008-01-01

    In the past decades, advances in speed of commodity CPUs have far outpaced advances in RAM latency. Main-memory access has therefore become a performance bottleneck for many computer applications; a phenomenon that is widely known as the "memory wall." In this paper, we report how research around

  2. Improving the Performance and Energy Efficiency of Phase Change Memory Systems

    Institute of Scientific and Technical Information of China (English)

    王琪; 李佳芮; 王东辉

    2015-01-01

    Phase change memory (PCM) is a promising technology for future memory thanks to its better scalability and lower leakage power than DRAM (dynamic random-access memory). However, adopting PCM as main memory needs to overcome its write issues, such as long write latency and high write power. In this paper, we propose two techniques to improve the performance and energy-efficiency of PCM memory systems. First, we propose a victim cache technique utilizing the existing buffer in the memory controller to reduce PCM memory accesses. The key idea is reorganizing the buffer into a victim cache structure (RBC) to provide additional hits for the LLC (last level cache). Second, we propose a chip parallelism-aware replacement policy (CPAR) for the victim cache to further improve performance. Instead of evicting one cache line once, CPAR evicts multiple cache lines that access different PCM chips. CPAR can reduce the frequent victim cache eviction and improve the write parallelism of PCM chips. The evaluation results show that, compared with the baseline, RBC can improve PCM memory system performance by up to 9.4% and 5.4% on average. Combing CPAR with RBC (RBC+CPAR) can improve performance by up to 19.0% and 12.1% on average. Moreover, RBC and RBC+CPAR can reduce memory energy consumption by 8.3%and 6.6%on average, respectively.

  3. Generic Database Cost Models for Hierarchical Memory Systems

    NARCIS (Netherlands)

    S. Manegold (Stefan); P.A. Boncz (Peter); M.L. Kersten (Martin)

    2002-01-01

    textabstractAccurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in main-memory DBMSs is still an open issue. Recent database research has demonstrated that memory access is

  4. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    International Nuclear Information System (INIS)

    Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

    2006-01-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

  5. 45 CFR 2490.150 - Program accessibility: Existing facilities.

    Science.gov (United States)

    2010-10-01

    ... 45 Public Welfare 4 2010-10-01 2010-10-01 false Program accessibility: Existing facilities. 2490.150 Section 2490.150 Public Welfare Regulations Relating to Public Welfare (Continued) JAMES MADISON... ACTIVITIES CONDUCTED BY THE JAMES MADISON MEMORIAL FELLOWSHIP FOUNDATION § 2490.150 Program accessibility...

  6. A review of emerging non-volatile memory (NVM) technologies and applications

    Science.gov (United States)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  7. Routes to the past: Neural substrates of direct and generative autobiographical memory retrieval

    OpenAIRE

    Addis, Donna Rose; Knapp, Katie; Roberts, Reece P.; Schacter, Daniel L.

    2011-01-01

    Models of autobiographical memory propose two routes to retrieval depending on cue specificity. When available cues are specific and personally-relevant, a memory can be directly accessed. However, when available cues are generic, one must engage a generative retrieval process to produce more specific cues to successfully access a relevant memory. The current study sought to characterize the neural bases of these retrieval processes. During functional magnetic resonance imaging (fMRI), partic...

  8. An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

    Science.gov (United States)

    Liu, Chen; Han, Runze; Zhou, Zheng; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

    2018-04-01

    In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

  9. Improved characteristics of amorphous indium-gallium-zinc-oxide-based resistive random access memory using hydrogen post-annealing

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Dae Yun; Lee, Tae-Ho; Kim, Tae Geun, E-mail: tgkim1@korea.ac.kr [School of Electrical Engineering, Korea University, Seoul 02841 (Korea, Republic of)

    2016-08-15

    The authors report an improvement in resistive switching (RS) characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO)-based resistive random access memory devices using hydrogen post-annealing. Because this a-IGZO thin film has oxygen off-stoichiometry in the form of deficient and excessive oxygen sites, the film properties can be improved by introducing hydrogen atoms through the annealing process. After hydrogen post-annealing, the device exhibited a stable bipolar RS, low-voltage set and reset operation, long retention (>10{sup 5 }s), good endurance (>10{sup 6} cycles), and a narrow distribution in each current state. The effect of hydrogen post-annealing is also investigated by analyzing the sample surface using X-ray photon spectroscopy and atomic force microscopy.

  10. Recollection Rejection: How Children Edit Their False Memories.

    Science.gov (United States)

    Brainerd, C. J.; Reyna, V. F.

    2002-01-01

    Presents new measure of children's use of an editing operation that suppresses false memories by accessing verbatim traces of true events. Application of the methodology showed that false-memory editing increased dramatically between early and middle childhood. Measure reacted appropriately to experimental manipulations. Developmental reductions…

  11. Gender Barriers to Access to Antiretroviral Therapy and its Link to ...

    African Journals Online (AJOL)

    Gender Barriers to Access to Antiretroviral Therapy and its Link to ... to assess executive function, verbal fluency, working memory, learning memory, recall, ... there were no gender differences in performance in the neuropsychological testing.

  12. Forgetting: the availability, accessibility, and intentional control problem. Part 2

    Directory of Open Access Journals (Sweden)

    Veronika V. Nourkova

    2016-12-01

    Full Text Available The paper focuses on the phenomenon of forgetting as a primal and generally productive memory process. The cases that require temporary and permanent forgetting of the data stored in the long-term memory are contrasted. The main methodological obstacle in forgetting research is identified as arising from the logical prohibition to argument from the negative, i.e. “the evidence of absence is not the evidence of absence”. Two mechanisms of forgetting are discussed in the paper: transformation of the memory trace and modulation of trace accessibility. The former mechanism of forgetting consists of memory trace destruction (memory trace decay, retroactive and proactive interference, and «catastrophic» interference or its transformation that leads to forming a new memory representation. The most promising way to legitimize the trace destruction mechanism is narrowing the further research to episodic memory subsystem. The latter mechanism of forgetting consists of both passive failure in access to appropriate memory content (the tip of the tongue phenomenon, the category size effect, the fan effect and the process of active retrieval inhibition. This phenomenon represents temporary inhibition of competing semantically similar responses in semantic memory, and motivational inhibition of self-deprecating memories in autobiographical memory. Thus, a variety of experimental paradigms in intentional forgetting research are considered. Contrary to the common claim that forgetting is а universal and homogeneous phenomenon, we propose that forgetting strategies might vary in different memory subsystems, and also depend on activity characteristics during encoding, storage and retrieval.

  13. The aftermath of memory retrieval for recycling visual working memory representations.

    Science.gov (United States)

    Park, Hyung-Bum; Zhang, Weiwei; Hyun, Joo-Seok

    2017-07-01

    We examined the aftermath of accessing and retrieving a subset of information stored in visual working memory (VWM)-namely, whether detection of a mismatch between memory and perception can impair the original memory of an item while triggering recognition-induced forgetting for the remaining, untested items. For this purpose, we devised a consecutive-change detection task wherein two successive testing probes were displayed after a single set of memory items. Across two experiments utilizing different memory-testing methods (whole vs. single probe), we observed a reliable pattern of poor performance in change detection for the second test when the first test had exhibited a color change. The impairment after a color change was evident even when the same memory item was repeatedly probed; this suggests that an attention-driven, salient visual change made it difficult to reinstate the previously remembered item. The second change detection, for memory items untested during the first change detection, was also found to be inaccurate, indicating that recognition-induced forgetting had occurred for the unprobed items in VWM. In a third experiment, we conducted a task that involved change detection plus continuous recall, wherein a memory recall task was presented after the change detection task. The analyses of the distributions of recall errors with a probabilistic mixture model revealed that the memory impairments from both visual changes and recognition-induced forgetting are explained better by the stochastic loss of memory items than by their degraded resolution. These results indicate that attention-driven visual change and recognition-induced forgetting jointly influence the "recycling" of VWM representations.

  14. Storage and binding of object features in visual working memory

    OpenAIRE

    Bays, Paul M; Wu, Emma Y; Husain, Masud

    2010-01-01

    An influential conception of visual working memory is of a small number of discrete memory “slots”, each storing an integrated representation of a single visual object, including all its component features. When a scene contains more objects than there are slots, visual attention controls which objects gain access to memory.

  15. Classic and contemporary perspectives on memory

    Directory of Open Access Journals (Sweden)

    Bentosela, Mariana

    2009-06-01

    Full Text Available Humans organize past events as “memories”, i.e. what we learn is encoded and stored in the brain, and by accumulating relevant environmental information we better cope with similar situations in the future. The main research on memory began in the 70s and the most important conclusions have been derived, on the one hand, from animal experiments, and on the other hand, from clinical studies of amnesic patients. Many classification systems of memory have been proposed. First, authors have distinguished among the different phases involved in the process of memory formation: short-term and long-term memory. Second, declarative and non-declarative memories have been recognized. Last, researchers have conceived the need to evaluate memory in a systematic manner through behavioral as well as pharmacological means, in different moments or times to be able to have independent access to the study of the different memory phases or types of memory. This approach to the study of memory has allowed evaluating drug effects on memory and also understanding the molecular mechanisms involved in memory processes. In addition, this research has also aimed at studying brain regions implicated in the diverse memory phenomena under investigation.

  16. An Account of the Accessioned Specimens in the Jose Vera Santos Memorial Herbarium, University of the Philippines Diliman

    Directory of Open Access Journals (Sweden)

    Sandra L. Yap

    2013-12-01

    Full Text Available The University of the Philippines Herbarium was established in 1908 and originally located in Ermita, Manila. The majority of its pre-war collections were destroyed during World War II, and no formal records of its specimens were preserved. Since then, multiple efforts to restore and improve the Herbarium have been proposed and implemented, most notably its move to the UP Diliman campus. In 1999, the Herbarium was off icially renamed as the Jose Vera Santos Memorial Herbarium after the noted grass expert, who initiated rehabilitation work in the Herbarium after the war. The Herbarium is registered with the international code PUH in the Index Herbariorum, a global directory of public herbaria managed by the New York Botanical Garden. To assess the accessioned (uniquely numbered and recorded collection of the Herbarium, an electronic database of its accessions was created.The Herbarium currently contains 14,648 accessions, 12,681 (86.6% of which were collected in the Philippines. This is comprised of 309 families, 1903 genera, and 4485 distinct species. Thirty-nine type specimens form part of the collection, only one of which is a holotype. On the basis of major plant groups, angiosperms make up 71% of the collection. Unsurprisingly, Family Poaceae has the largest number of specimens at 2,759 accessions. The earliest dated Philippine specimen was collected by E.D. Merrill in 1902, and roughly half of the total accessioned specimens were collected in the 1950s and 1970s. The two most prolif ic collectors were Santos and Leonardo L. Co, with 2,320 and 2,147 specimens, respectively. Luzon is the most well-represented island group with 2,752 specimens collected in Metro Manila alone. At present, PUH Curator James V. LaFrankie is working on the expansion of the collection and upgrading of the herbarium to encourage future educational and research activities.

  17. Event memory and moving in a well-known environment.

    Science.gov (United States)

    Tamplin, Andrea K; Krawietz, Sabine A; Radvansky, Gabriel A; Copeland, David E

    2013-11-01

    Research in narrative comprehension has repeatedly shown that when people read about characters moving in well-known environments, the accessibility of object information follows a spatial gradient. That is, the accessibility of objects is best when they are in the same room as the protagonist, and it becomes worse the farther away they are see, e.g., Morrow, Greenspan, & Bower, (Journal of Memory and Language, 26, 165-187, 1987). In the present study, we assessed this finding using an interactive environment in which we had people memorize a map and navigate a virtual simulation of the area. During navigation, people were probed with pairs of object names and indicated whether both objects were in the same room. In contrast to the narrative studies described above, several experiments showed no evidence of a clear spatial gradient. Instead, memory for objects in currently occupied locations (e.g., the location room) was more accessible, especially after a small delay, but no clear decline was evident in the accessibility of information in memory with increased distance. Also, memory for objects along the pathway of movement (i.e., rooms that a person only passed through) showed a transitory suppression effect that was present immediately after movement, but attenuated over time. These results were interpreted in light of the event horizon model of event cognition.

  18. Single Event Upset Rate Estimates for a 16-K CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory).

    Science.gov (United States)

    1986-09-30

    4 . ~**..ft.. ft . - - - ft SI TABLES 9 I. SA32~40 Single Event Upset Test, 1140-MeV Krypton, 9/l8/8~4. . .. .. .. .. .. .16 II. CRUP Simulation...cosmic ray interaction analysis described in the remainder of this report were calculated using the CRUP computer code 3 modified for funneling. The... CRUP code requires, as inputs, the size of a depletion region specified as a retangular parallel piped with dimensions a 9 b S c, the effective funnel

  19. Beyond the magic number four: Remapping high-capacity, pre-attentive, fragile working memory

    NARCIS (Netherlands)

    Zerr, P.; Gayet, S.; Mulder, K.T.; Sligte, I.G.; Stigchel, S. van der

    2017-01-01

    Visual short term memory allows us to access visual information after termination of its retinal input. Generally, a distinction is made between a robust, capacity-limited form (working memory, WM) and high-capacity, pre-attentive, maskable forms (sensory memory, e.g. fragile memory, FM). Eye

  20. Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

    International Nuclear Information System (INIS)

    Lin, Chun-Cheng; Tang, Jian-Fu; Su, Hsiu-Hsien; Hong, Cheng-Shong; Huang, Chih-Yu; Chu, Sheng-Yuan

    2016-01-01

    The multi-step resistive switching (RS) behavior of a unipolar Pt/Li 0.06 Zn 0.94 O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li + ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

  1. Chromatin accessibility prediction via convolutional long short-term memory networks with k-mer embedding.

    Science.gov (United States)

    Min, Xu; Zeng, Wanwen; Chen, Ning; Chen, Ting; Jiang, Rui

    2017-07-15

    Experimental techniques for measuring chromatin accessibility are expensive and time consuming, appealing for the development of computational approaches to predict open chromatin regions from DNA sequences. Along this direction, existing methods fall into two classes: one based on handcrafted k -mer features and the other based on convolutional neural networks. Although both categories have shown good performance in specific applications thus far, there still lacks a comprehensive framework to integrate useful k -mer co-occurrence information with recent advances in deep learning. We fill this gap by addressing the problem of chromatin accessibility prediction with a convolutional Long Short-Term Memory (LSTM) network with k -mer embedding. We first split DNA sequences into k -mers and pre-train k -mer embedding vectors based on the co-occurrence matrix of k -mers by using an unsupervised representation learning approach. We then construct a supervised deep learning architecture comprised of an embedding layer, three convolutional layers and a Bidirectional LSTM (BLSTM) layer for feature learning and classification. We demonstrate that our method gains high-quality fixed-length features from variable-length sequences and consistently outperforms baseline methods. We show that k -mer embedding can effectively enhance model performance by exploring different embedding strategies. We also prove the efficacy of both the convolution and the BLSTM layers by comparing two variations of the network architecture. We confirm the robustness of our model to hyper-parameters by performing sensitivity analysis. We hope our method can eventually reinforce our understanding of employing deep learning in genomic studies and shed light on research regarding mechanisms of chromatin accessibility. The source code can be downloaded from https://github.com/minxueric/ismb2017_lstm . tingchen@tsinghua.edu.cn or ruijiang@tsinghua.edu.cn. Supplementary materials are available at

  2. Breaking the current density threshold in spin-orbit-torque magnetic random access memory

    Science.gov (United States)

    Zhang, Yin; Yuan, H. Y.; Wang, X. S.; Wang, X. R.

    2018-04-01

    Spin-orbit-torque magnetic random access memory (SOT-MRAM) is a promising technology for the next generation of data storage devices. The main bottleneck of this technology is the high reversal current density threshold. This outstanding problem is now solved by a new strategy in which the magnitude of the driven current density is fixed while the current direction varies with time. The theoretical limit of minimal reversal current density is only a fraction (the Gilbert damping coefficient) of the threshold current density of the conventional strategy. The Euler-Lagrange equation for the fastest magnetization reversal path and the optimal current pulse is derived for an arbitrary magnetic cell and arbitrary spin-orbit torque. The theoretical limit of minimal reversal current density and current density for a GHz switching rate of the new reversal strategy for CoFeB/Ta SOT-MRAMs are, respectively, of the order of 105 A/cm 2 and 106 A/cm 2 far below 107 A/cm 2 and 108 A/cm 2 in the conventional strategy. Furthermore, no external magnetic field is needed for a deterministic reversal in the new strategy.

  3. Role of an encapsulating layer for reducing resistance drift in phase change random access memory

    Directory of Open Access Journals (Sweden)

    Bo Jin

    2014-12-01

    Full Text Available Phase change random access memory (PCRAM devices exhibit a steady increase in resistance in the amorphous phase upon aging and this resistance drift phenomenon directly affects the device reliability. A stress relaxation model is used here to study the effect of a device encapsulating layer material in addressing the resistance drift phenomenon in PCRAM. The resistance drift can be increased or decreased depending on the biaxial moduli of the phase change material (YPCM and the encapsulating layer material (YELM according to the stress relationship between them in the drift regime. The proposed model suggests that the resistance drift can be effectively reduced by selecting a proper material as an encapsulating layer. Moreover, our model explains that reducing the size of the phase change material (PCM while fully reset and reducing the amorphous/crystalline ratio in PCM help to improve the resistance drift, and thus opens an avenue for highly reliable multilevel PCRAM applications.

  4. Read method compensating parasitic sneak currents in a crossbar memristive memory

    KAUST Repository

    Zidan, Mohammed A.

    2017-03-02

    Methods are provided for mitigating problems caused by sneak- paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: -reading a value of the target memory cell; and -calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an "initial bits" strategy or a "dummy bits" strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.

  5. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    Directory of Open Access Journals (Sweden)

    A. Schmitz

    2005-01-01

    Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  6. Saying What's on Your Mind: Working Memory Effects on Sentence Production

    Science.gov (United States)

    Slevc, L. Robert

    2011-01-01

    The role of working memory (WM) in sentence comprehension has received considerable interest, but little work has investigated how sentence production relies on memory mechanisms. Three experiments investigated speakers' tendency to produce syntactic structures that allow for early production of material that is accessible in memory. In Experiment…

  7. With sadness comes accuracy; with happiness, false memory: mood and the false memory effect.

    Science.gov (United States)

    Storbeck, Justin; Clore, Gerald L

    2005-10-01

    The Deese-Roediger-McDermott paradigm lures people to produce false memories. Two experiments examined whether induced positive or negative moods would influence this false memory effect. The affect-as-information hypothesis predicts that, on the one hand, positive affective cues experienced as task-relevant feedback encourage relational processing during encoding, which should enhance false memory effects. On the other hand, negative affective cues are hypothesized to encourage item-specific processing at encoding, which should discourage such effects. The results of Experiment 1 are consistent with these predictions: Individuals in negative moods were significantly less likely to show false memory effects than those in positive moods or those whose mood was not manipulated. Experiment 2 introduced inclusion instructions to investigate whether moods had their effects at encoding or retrieval. The results replicated the false memory finding of Experiment 1 and provide evidence that moods influence the accessibility of lures at encoding, rather than influencing monitoring at retrieval of whether lures were actually presented.

  8. Unstructured Adaptive Meshes: Bad for Your Memory?

    Science.gov (United States)

    Biswas, Rupak; Feng, Hui-Yu; VanderWijngaart, Rob

    2003-01-01

    This viewgraph presentation explores the need for a NASA Advanced Supercomputing (NAS) parallel benchmark for problems with irregular dynamical memory access. This benchmark is important and necessary because: 1) Problems with localized error source benefit from adaptive nonuniform meshes; 2) Certain machines perform poorly on such problems; 3) Parallel implementation may provide further performance improvement but is difficult. Some examples of problems which use irregular dynamical memory access include: 1) Heat transfer problem; 2) Heat source term; 3) Spectral element method; 4) Base functions; 5) Elemental discrete equations; 6) Global discrete equations. Nonconforming Mesh and Mortar Element Method are covered in greater detail in this presentation.

  9. Conglomerate memory and cosmopolitanism

    Directory of Open Access Journals (Sweden)

    Susannah Ryan

    2016-01-01

    Full Text Available Under what conditions do countries and cultures considered radically different find a basis for allegiance and kinship? What part does memory play in this process? This article responds to these questions in two ways: 1 Through Emmanuel Levinas and Hannah Arendt, I propose that when an other appears in empathetic discourses that both honor difference and cite shared human experiences, seemingly irreconcilable people can develop a sense of mutual responsibility and 2 Conglomerate memory, memories that fuse together others through common pains, contributes to such an appearance. To illustrate this point, I turn to Congolese voices as they are articulated in online American discourses; although currently, authors of online texts typically rely on traditional narrative forms that position Central Africa as incommensurate to Western civilizations, the Internet's worldwide accessibility and intertextual capacities render it a place primed for developing international collectives by connecting memories while maintaining difference.

  10. Generic Database Cost Models for Hierarchical Memory Systems

    OpenAIRE

    Manegold, Stefan; Boncz, Peter; Kersten, Martin

    2002-01-01

    textabstractAccurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in main-memory DBMSs is still an open issue. Recent database research has demonstrated that memory access is more and more becoming a significant---if not the major---cost component of database operations. If used properly, fast but small cache memories---usually organized in cascading hierarchy between CPU ...

  11. Working Memory Underpins Cognitive Development, Learning, and Education

    Science.gov (United States)

    Cowan, Nelson

    2014-01-01

    Working memory is the retention of a small amount of information in a readily accessible form. It facilitates planning, comprehension, reasoning, and problem solving. I examine the historical roots and conceptual development of the concept and the theoretical and practical implications of current debates about working memory mechanisms. Then, I…

  12. All-printed paper memory

    KAUST Repository

    Lien, Derhsien

    2014-08-26

    We report the memory device on paper by means of an all-printing approach. Using a sequence of inkjet and screen-printing techniques, a simple metal-insulator-metal device structure is fabricated on paper as a resistive random access memory with a potential to reach gigabyte capacities on an A4 paper. The printed-paper-based memory devices (PPMDs) exhibit reproducible switching endurance, reliable retention, tunable memory window, and the capability to operate under extreme bending conditions. In addition, the PBMD can be labeled on electronics or living objects for multifunctional, wearable, on-skin, and biocompatible applications. The disposability and the high-security data storage of the paper-based memory are also demonstrated to show the ease of data handling, which are not achievable for regular silicon-based electronic devices. We envision that the PPMDs manufactured by this cost-effective and time-efficient all-printing approach would be a key electronic component to fully activate a paper-based circuit and can be directly implemented in medical biosensors, multifunctional devices, and self-powered systems. © 2014 American Chemical Society.

  13. High capacity, high speed histogramming data acquisition memory

    International Nuclear Information System (INIS)

    Epstein, A.; Boulin, C.

    1996-01-01

    A double width CAMAC DRAM store module was developed for use as a histogramming memory in fast time-resolved synchrotron radiation applications to molecular biology. High speed direct memory modify (3 MHz) is accomplished by using a discrete DRAM controller and fast page mode access. The module can be configured using standard SIMMs to sizes of up to 64M-words. The word width is 16 bit and the module can handle overflows by storing the overflow addresses in a dedicated FIFO. Simultaneous front panel DMM/DMI access and CAMAC readout of the overflow addresses is supported

  14. Multiple Memory Stores and Operant Conditioning: A Rationale for Memory's Complexity

    Science.gov (United States)

    Meeter, Martijn; Veldkamp, Rob; Jin, Yaochu

    2009-01-01

    Why does the brain contain more than one memory system? Genetic algorithms can play a role in elucidating this question. Here, model animals were constructed containing a dorsal striatal layer that controlled actions, and a ventral striatal layer that controlled a dopaminergic learning signal. Both layers could gain access to three modeled memory…

  15. Are there multiple visual short-term memory stores?

    Science.gov (United States)

    Sligte, Ilja G; Scholte, H Steven; Lamme, Victor A F

    2008-02-27

    Classic work on visual short-term memory (VSTM) suggests that people store a limited amount of items for subsequent report. However, when human observers are cued to shift attention to one item in VSTM during retention, it seems as if there is a much larger representation, which keeps additional items in a more fragile VSTM store. Thus far, it is not clear whether the capacity of this fragile VSTM store indeed exceeds the traditional capacity limits of VSTM. The current experiments address this issue and explore the capacity, stability, and duration of fragile VSTM representations. We presented cues in a change-detection task either just after off-set of the memory array (iconic-cue), 1,000 ms after off-set of the memory array (retro-cue) or after on-set of the probe array (post-cue). We observed three stages in visual information processing 1) iconic memory with unlimited capacity, 2) a four seconds lasting fragile VSTM store with a capacity that is at least a factor of two higher than 3) the robust and capacity-limited form of VSTM. Iconic memory seemed to depend on the strength of the positive after-image resulting from the memory display and was virtually absent under conditions of isoluminance or when intervening light masks were presented. This suggests that iconic memory is driven by prolonged retinal activation beyond stimulus duration. Fragile VSTM representations were not affected by light masks, but were completely overwritten by irrelevant pattern masks that spatially overlapped the memory array. We find that immediately after a stimulus has disappeared from view, subjects can still access information from iconic memory because they can see an after-image of the display. After that period, human observers can still access a substantial, but somewhat more limited amount of information from a high-capacity, but fragile VSTM that is overwritten when new items are presented to the eyes. What is left after that is the traditional VSTM store, with a limit of

  16. Are there multiple visual short-term memory stores?

    Directory of Open Access Journals (Sweden)

    Ilja G Sligte

    Full Text Available BACKGROUND: Classic work on visual short-term memory (VSTM suggests that people store a limited amount of items for subsequent report. However, when human observers are cued to shift attention to one item in VSTM during retention, it seems as if there is a much larger representation, which keeps additional items in a more fragile VSTM store. Thus far, it is not clear whether the capacity of this fragile VSTM store indeed exceeds the traditional capacity limits of VSTM. The current experiments address this issue and explore the capacity, stability, and duration of fragile VSTM representations. METHODOLOGY/PRINCIPAL FINDINGS: We presented cues in a change-detection task either just after off-set of the memory array (iconic-cue, 1,000 ms after off-set of the memory array (retro-cue or after on-set of the probe array (post-cue. We observed three stages in visual information processing 1 iconic memory with unlimited capacity, 2 a four seconds lasting fragile VSTM store with a capacity that is at least a factor of two higher than 3 the robust and capacity-limited form of VSTM. Iconic memory seemed to depend on the strength of the positive after-image resulting from the memory display and was virtually absent under conditions of isoluminance or when intervening light masks were presented. This suggests that iconic memory is driven by prolonged retinal activation beyond stimulus duration. Fragile VSTM representations were not affected by light masks, but were completely overwritten by irrelevant pattern masks that spatially overlapped the memory array. CONCLUSIONS/SIGNIFICANCE: We find that immediately after a stimulus has disappeared from view, subjects can still access information from iconic memory because they can see an after-image of the display. After that period, human observers can still access a substantial, but somewhat more limited amount of information from a high-capacity, but fragile VSTM that is overwritten when new items are presented

  17. Physically Transient Memory on a Rapidly Dissoluble Paper for Security Application

    Science.gov (United States)

    Bae, Hagyoul; Lee, Byung-Hyun; Lee, Dongil; Seol, Myeong-Lok; Kim, Daewon; Han, Jin-Woo; Kim, Choong-Ki; Jeon, Seung-Bae; Ahn, Daechul; Park, Sang-Jae; Park, Jun-Young; Choi, Yang-Kyu

    2016-12-01

    We report the transient memory device by means of a water soluble SSG (solid sodium with glycerine) paper. This material has a hydroscopic property hence it can be soluble in water. In terms of physical security of memory devices, prompt abrogation of a memory device which stored a large number of data is crucial when it is stolen because all of things have identified information in the memory device. By utilizing the SSG paper as a substrate, we fabricated a disposable resistive random access memory (RRAM) which has good data retention of longer than 106 seconds and cycling endurance of 300 cycles. This memory device is dissolved within 10 seconds thus it can never be recovered or replicated. By employing direct printing but not lithography technology to aim low cost and disposable applications, the memory capacity tends to be limited less than kilo-bits. However, unlike high memory capacity demand for consumer electronics, the proposed device is targeting for security applications. With this regards, the sub-kilobit memory capacity should find the applications such as one-time usable personal identification, authentication code storage, cryptography key, and smart delivery tag. This aspect is attractive for security and protection system against unauthorized accessibility.

  18. Web based dosimetry system for reading and monitoring dose through internet access

    International Nuclear Information System (INIS)

    Perle, S.C.; Bennett, K.; Kahilainen, J.; Vuotila, M.

    2010-01-01

    The Instadose TM dosemeter from Mirion Technologies is a small, rugged device based on patented direct ion storage technology and is accredited by the National Voluntary Laboratory Accreditation Program (NVLAP) through NIST, bringing radiation monitoring into the digital age. Smaller than a flash drive, this dosemeter provides an instant read-out when connected to any computer with internet access and a USB connection. Instadose devices provide radiation workers with more flexibility than today's dosemeters. Non Volatile Analog Memory Cell surrounded by a Gas Filled Ion Chamber. Dose changes the amount of Electric Charge in the DIS Analog Memory. The total charge storage capacity of the memory determines the available dose range. The state of the Analog Memory is determined by measuring the voltage across the memory cell. AMP (Account Management Program) provides secure real time access to account details, device assignments, reports and all pertinent account information. Access can be restricted based on the role assignment assigned to an individual. A variety of reports are available for download and customizing. The Advantages of the Instadose dosemeter are: - Unlimited reading capability, - Concerns about a possible exposure can be addressed immediately, - Re-readability without loss of exposure data, with cumulative exposure maintained. (authors)

  19. Web based dosimetry system for reading and monitoring dose through internet access

    Energy Technology Data Exchange (ETDEWEB)

    Perle, S.C.; Bennett, K.; Kahilainen, J.; Vuotila, M. [Mirion Technologies (United States); Mirion Technologies (Finland)

    2010-07-01

    The Instadose{sup TM} dosemeter from Mirion Technologies is a small, rugged device based on patented direct ion storage technology and is accredited by the National Voluntary Laboratory Accreditation Program (NVLAP) through NIST, bringing radiation monitoring into the digital age. Smaller than a flash drive, this dosemeter provides an instant read-out when connected to any computer with internet access and a USB connection. Instadose devices provide radiation workers with more flexibility than today's dosemeters. Non Volatile Analog Memory Cell surrounded by a Gas Filled Ion Chamber. Dose changes the amount of Electric Charge in the DIS Analog Memory. The total charge storage capacity of the memory determines the available dose range. The state of the Analog Memory is determined by measuring the voltage across the memory cell. AMP (Account Management Program) provides secure real time access to account details, device assignments, reports and all pertinent account information. Access can be restricted based on the role assignment assigned to an individual. A variety of reports are available for download and customizing. The Advantages of the Instadose dosemeter are: - Unlimited reading capability, - Concerns about a possible exposure can be addressed immediately, - Re-readability without loss of exposure data, with cumulative exposure maintained. (authors)

  20. Marijuana effects on long-term memory assessment and retrieval.

    Science.gov (United States)

    Darley, C F; Tinklenberg, J R; Roth, W T; Vernon, S; Kopell, B S

    1977-05-09

    The ability of 16 college-educated male subjects to recall from long-term memory a series of common facts was tested during intoxication with marijuana extract calibrated to 0.3 mg/kg delta-9-tetrahydrocannabinol and during placebo conditions. The subjects' ability to assess their memory capabilities was then determined by measuring how certain they were about the accuracy of their recall performance and by having them predict their performance on a subsequent recognition test involving the same recall items. Marijuana had no effect on recall or recognition performance. These results do not support the view that marijuana provides access to facts in long-term storage which are inaccessible during non-intoxication. During both marijuana and placebo conditions, subjects could accurately predict their recognition memory performance. Hence, marijuana did not alter the subjects' ability to accurately assess what information resides in long-term memory even though they did not have complete access to that information.

  1. Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

    International Nuclear Information System (INIS)

    Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

    2005-01-01

    Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

  2. In-memory interconnect protocol configuration registers

    Energy Technology Data Exchange (ETDEWEB)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  3. In-memory interconnect protocol configuration registers

    Science.gov (United States)

    Cheng, Kevin Y.; Roberts, David A.

    2017-09-19

    Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

  4. Scaling Non-Regular Shared-Memory Codes by Reusing Custom Loop Schedules

    Directory of Open Access Journals (Sweden)

    Dimitrios S. Nikolopoulos

    2003-01-01

    Full Text Available In this paper we explore the idea of customizing and reusing loop schedules to improve the scalability of non-regular numerical codes in shared-memory architectures with non-uniform memory access latency. The main objective is to implicitly setup affinity links between threads and data, by devising loop schedules that achieve balanced work distribution within irregular data spaces and reusing them as much as possible along the execution of the program for better memory access locality. This transformation provides a great deal of flexibility in optimizing locality, without compromising the simplicity of the shared-memory programming paradigm. In particular, the programmer does not need to explicitly distribute data between processors. The paper presents practical examples from real applications and experiments showing the efficiency of the approach.

  5. Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

    Energy Technology Data Exchange (ETDEWEB)

    Lin, Chun-Cheng [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Department of Mathematic and Physical Sciences, R.O.C. Air Force Academy, Kaohsiung 820, Taiwan (China); Tang, Jian-Fu; Su, Hsiu-Hsien [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Hong, Cheng-Shong; Huang, Chih-Yu [Department of Electronic Engineering, National Kaohsiung Normal University, Kaohsiung 802, Taiwan (China); Chu, Sheng-Yuan, E-mail: chusy@mail.ncku.edu.tw [Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (China); Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan 701, Taiwan (China)

    2016-06-28

    The multi-step resistive switching (RS) behavior of a unipolar Pt/Li{sub 0.06}Zn{sub 0.94}O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li{sup +} ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

  6. Biodegradable Shape Memory Polymers in Medicine.

    Science.gov (United States)

    Peterson, Gregory I; Dobrynin, Andrey V; Becker, Matthew L

    2017-11-01

    Shape memory materials have emerged as an important class of materials in medicine due to their ability to change shape in response to a specific stimulus, enabling the simplification of medical procedures, use of minimally invasive techniques, and access to new treatment modalities. Shape memory polymers, in particular, are well suited for such applications given their excellent shape memory performance, tunable materials properties, minimal toxicity, and potential for biodegradation and resorption. This review provides an overview of biodegradable shape memory polymers that have been used in medical applications. The majority of biodegradable shape memory polymers are based on thermally responsive polyesters or polymers that contain hydrolyzable ester linkages. These materials have been targeted for use in applications pertaining to embolization, drug delivery, stents, tissue engineering, and wound closure. The development of biodegradable shape memory polymers with unique properties or responsiveness to novel stimuli has the potential to facilitate the optimization and development of new medical applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Synaptic Correlates of Working Memory Capacity.

    Science.gov (United States)

    Mi, Yuanyuan; Katkov, Mikhail; Tsodyks, Misha

    2017-01-18

    Psychological studies indicate that human ability to keep information in readily accessible working memory is limited to four items for most people. This extremely low capacity severely limits execution of many cognitive tasks, but its neuronal underpinnings remain unclear. Here we show that in the framework of synaptic theory of working memory, capacity can be analytically estimated to scale with characteristic time of short-term synaptic depression relative to synaptic current time constant. The number of items in working memory can be regulated by external excitation, enabling the system to be tuned to the desired load and to clear the working memory of currently held items to make room for new ones. Copyright © 2017 Elsevier Inc. All rights reserved.

  8. High Temperature Memories in SiC Technology

    OpenAIRE

    Ekström, Mattias

    2014-01-01

    This thesis is part of the Working On Venus (WOV) project. The aim of the project is to design electronics in silicon carbide (SiC) that can withstand the extreme surface environmen  of Venus. This thesis investigates some possible computer memory technologies that could survive on the surface of Venus. A memory must be able to function at 460 °C and after a total radiation dose of at least 200 Gy (SiC). This thesis is a literature survey. The thesis covers several Random-Access Memory (RAM) ...

  9. Rapid influences of cued visual memories on attentional guidance

    NARCIS (Netherlands)

    van Moorselaar, D.; Battistoni, E.; Theeuwes, J.; Olivers, C.N.L.

    2015-01-01

    There is evidence that the deployment of attention can be biased by the content of visual working memory. Recently, it has been shown that focusing internal attention to a specific item in memory not only increases the accessibility of that specific item for retrieval, but also results in increased

  10. A Survey of Phase Change Memory Systems

    Institute of Scientific and Technical Information of China (English)

    夏飞; 蒋德钧; 熊劲; 孙凝晖

    2015-01-01

    As the scaling of applications increases, the demand of main memory capacity increases in order to serve large working set. It is difficult for DRAM (dynamic random access memory) based memory system to satisfy the memory capacity requirement due to its limited scalability and high energy consumption. Compared to DRAM, PCM (phase change memory) has better scalability, lower energy leakage, and non-volatility. PCM memory systems have become a hot topic of academic and industrial research. However, PCM technology has the following three drawbacks: long write latency, limited write endurance, and high write energy, which raises challenges to its adoption in practice. This paper surveys architectural research work to optimize PCM memory systems. First, this paper introduces the background of PCM. Then, it surveys research efforts on PCM memory systems in performance optimization, lifetime improving, and energy saving in detail, respectively. This paper also compares and summarizes these techniques from multiple dimensions. Finally, it concludes these optimization techniques and discusses possible research directions of PCM memory systems in future.

  11. HFB : A FASTBUS multi event double port buffer memory

    International Nuclear Information System (INIS)

    Cerrito, L.; Lebbolo, H.

    1986-01-01

    The authors describe here the FB double port buffer memory developed at the LPNHE of the University Paris VI. Its purposes are to make available same features useful in the High Energy environment, to reduce, for a given amount of memory, the dead time data collection in a large size (in term of read-out channels) High Energy experiment and to get a buffer of memory as cheap and reliable as possible. The FB protocol, on the crate and cable side, is exploited using the coupler on 4 PAL's developed by G.Fremont and E.Sanchis. The DATA-Space is divided in 4 independent smaller blocks in a way such that a block can be accessed from a port while a different block is accessed from the other port. The two ports are: A, the FB crate port and B, the FB cable port. The buffer works as a rotary FIFO, looping over the 4 blocks of memory, but allowing for any random access. A mechanism is implemented on the board in order to be able to link different modules placed everywhere. If there are m modules, the looping will be around m 4 memory blocks. A multi event function is implemented on the board. HFB is quiped of two NTA for the DATA-Space on the port ''A'', and a flag to choose between them, to allow for a FB spying of DATA during the DAS dead time. HFB is a buffer of memory which can be used at each stage of a DAS: Frontend, Intermediate (MEB) or final, being completely FB standard. The HFB was designed for the LEP data acquisition system

  12. Belief Inhibition in Children's Reasoning: Memory-Based Evidence

    Science.gov (United States)

    Steegen, Sara; Neys, Wim De

    2012-01-01

    Adult reasoning has been shown as mediated by the inhibition of intuitive beliefs that are in conflict with logic. The current study introduces a classic procedure from the memory field to investigate belief inhibition in 12- to 17-year-old reasoners. A lexical decision task was used to probe the memory accessibility of beliefs that were cued…

  13. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization......In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  14. James Joyce, music and memory

    OpenAIRE

    Brown, Katie

    2007-01-01

    This thesis, James Joyce, Music and Memory, explores the connection between music and Irish cultural memory in Joyce’s works from Chamber Music to the “pure music” of Finnegans Wake. Overall, it shows that Joyce’s ongoing desire to emulate musical forms must be seen in light of Joyce’s wish to come to terms with Irish cultural history, as these are the driving forces that bring about his changes in style. TARA (Trinity’s Access to Research Archive) has a robust takedown policy. Please cont...

  15. A Neuroanatomical Model of Prefrontal Inhibitory Modulation of Memory Retrieval

    Science.gov (United States)

    Depue, Brendan E.

    2012-01-01

    Memory of past experience is essential for guiding goal-related behavior. Being able to control accessibility of memory through modulation of retrieval enables humans to flexibly adapt to their environment. Understanding the specific neural pathways of how this control is achieved has largely eluded cognitive neuroscience. Accordingly, in the current paper I review literature that examines the overt control over retrieval in order to reduce accessibility. I first introduce three hypotheses of inhibition of retrieval. These hypotheses involve: i) attending to other stimuli as a form of diversionary attention, ii) inhibiting the specific individual neural representation of the memory, and iii) inhibiting the hippocampus and retrieval process more generally to prevent reactivation of the representation. I then analyze literature taken from the White Bear Suppression, Directed Forgetting and Think/No-Think tasks to provide evidence for these hypotheses. Finally, a neuroanatomical model is developed to indicate three pathways from PFC to the hippocampal complex that support inhibition of memory retrieval. Describing these neural pathways increases our understanding of control over memory in general. PMID:22374224

  16. Contexts and Control Operations Used in Accessing List-Specific, Generalized, and Semantic Memories

    Science.gov (United States)

    Humphreys, Michael S.; Murray, Krista L.; Maguire, Angela M.

    2009-01-01

    The human ability to focus memory retrieval operations on a particular list, episode or memory structure has not been fully appreciated or documented. In Experiment 1-3, we make it increasingly difficult for participants to switch between a less recent list (multiple study opportunities), and a more recent list (single study opportunity). Task…

  17. Loss of object recognition memory produced by extended access to methamphetamine self-administration is reversed by positive allosteric modulation of metabotropic glutamate receptor 5.

    Science.gov (United States)

    Reichel, Carmela M; Schwendt, Marek; McGinty, Jacqueline F; Olive, M Foster; See, Ronald E

    2011-03-01

    Chronic methamphetamine (meth) abuse can lead to persisting cognitive deficits. Here, we utilized a long-access meth self-administration (SA) protocol to assess recognition memory and metabotropic glutamate receptor (mGluR) expression, and the possible reversal of cognitive impairments with the mGluR5 allosteric modulator, 3-cyano-N-(1,3-diphenyl-1H-pyrazol-5-yl) benzamide (CDPPB). Male, Long-Evans rats self-administered i.v. meth (0.02 mg/infusion) on an FR1 schedule of reinforcement or received yoked-saline infusions. After seven daily 1-h sessions, rats were switched to 6-h daily sessions for 14 days, and then underwent drug abstinence. Rats were tested for object recognition memory at 1 week after meth SA at 90 min and 24 h retention intervals. In a separate experiment, rats underwent the same protocol, but received either vehicle or CDPPB (30 mg/kg) after familiarization. Rats were killed on day 8 or 14 post-SA and brain tissue was obtained. Meth intake escalated over the extended access period. Additionally, meth-experienced rats showed deficits in both short- and long-term recognition memory, demonstrated by a lack of novel object exploration. The deficit at 90 min was reversed by CDPPB treatment. On day 8, meth intake during SA negatively correlated with mGluR expression in the perirhinal and prefrontal cortex, and mGluR5 receptor expression was decreased 14 days after discontinuation of meth. This effect was specific to mGluR5 levels in the perirhinal cortex, as no differences were identified in the hippocampus or in mGluR2/3 receptors. These results from a clinically-relevant animal model of addiction suggest that mGluR5 receptor modulation may be a potential treatment of cognitive dysfunction in meth addiction.

  18. Television as a Hybrid Repertoire of Memory. New Dynamic Practices of Cultural Memory in the Multi-Platform Era

    Directory of Open Access Journals (Sweden)

    Berber Hagedoorn

    2013-06-01

    Full Text Available In this article, television is reconsidered as a hybrid ‘repertoire’ ofmemory. It is demonstrated how new dynamic production and scheduling practicesin connection with highly accessible and participatory forms of user engagementoffer opportunities for television users to engage with the past, and how suchpractices affect television as a practice of memory. The media platform HollandDoc is discussed as a principal casestudy. By adopting and expanding Aleida Assmann’s model of the dynamics ofcultural memory between remembering and forgetting, a new model to studytelevision as cultural memory is proposed which represents the medium’shybridity in the multi-platform era.

  19. Semantic Memory and Verbal Working Memory Correlates of N400 to Subordinate Homographs

    Science.gov (United States)

    Salisbury, Dean F.

    2004-01-01

    N400 is an event-related brain potential that indexes operations in semantic memory conceptual space, whether elicited by language or some other representation (e.g., drawings). Language models typically propose three stages: lexical access or orthographic- and phonological-level analysis; lexical selection or word-level meaning and associate…

  20. A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

    Science.gov (United States)

    Chien, Wei-Chih; Chen, Yi-Chou; Lee, Feng-Ming; Lin, Yu-Yu; Lai, Erh-Kun; Yao, Yeong-Der; Gong, Jeng; Horng, Sheng-Fu; Yeh, Chiao-Wen; Tsai, Shih-Chang; Lee, Ching-Hsiung; Huang, Yu-Kai; Chen, Chun-Fu; Kao, Hsiao-Feng; Shih, Yen-Hao; Hsieh, Kuang-Yeu; Lu, Chih-Yuan

    2011-04-01

    The behavior of WOX resistive random access memory (ReRAM) is a strong function of the top electrode material, which controls the conduction mechanism and the forming process. When using a top electrode with low work function, the current conduction is limited by space charges. On the other hand, the mechanism becomes thermionic emission for devices with a high work function top electrode. These (thermionic) devices are also found to have higher initial resistance, reduced forming current, and larger resistance window. Based on these insights and considering the compatibility to complementary metal-oxide-semiconductor (CMOS) process, we proposed to use Ni as the top electrode for high performance WOX ReRAM devices. The new Ni/WOX/W device can be switched at a low current density less than 8×105 A/cm2, with RESET/SET resistance ratio greater than 100, and extremely good data retention of more than 300 years at 85 °C.

  1. Insect olfactory coding and memory at multiple timescales.

    Science.gov (United States)

    Gupta, Nitin; Stopfer, Mark

    2011-10-01

    Insects can learn, allowing them great flexibility for locating seasonal food sources and avoiding wily predators. Because insects are relatively simple and accessible to manipulation, they provide good experimental preparations for exploring mechanisms underlying sensory coding and memory. Here we review how the intertwining of memory with computation enables the coding, decoding, and storage of sensory experience at various stages of the insect olfactory system. Individual parts of this system are capable of multiplexing memories at different timescales, and conversely, memory on a given timescale can be distributed across different parts of the circuit. Our sampling of the olfactory system emphasizes the diversity of memories, and the importance of understanding these memories in the context of computations performed by different parts of a sensory system. Published by Elsevier Ltd.

  2. Silent store detection and recording in memory storage

    Energy Technology Data Exchange (ETDEWEB)

    Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

    2017-03-14

    An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

  3. Silent store detection and recording in memory storage

    Energy Technology Data Exchange (ETDEWEB)

    Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

    2017-03-07

    An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

  4. SODR Memory Control Buffer Control ASIC

    Science.gov (United States)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  5. A memory module for experimental data handling

    Science.gov (United States)

    De Blois, J.

    1985-02-01

    A compact CAMAC memory module for experimental data handling was developed to eliminate the need of direct memory access in computer controlled measurements. When using autonomous controllers it also makes measurements more independent of the program and enlarges the available space for programs in the memory of the micro-computer. The memory module has three modes of operation: an increment-, a list- and a fifo mode. This is achieved by connecting the main parts, being: the memory (MEM), the fifo buffer (FIFO), the address buffer (BUF), two counters (AUX and ADDR) and a readout register (ROR), by an internal 24-bit databus. The time needed for databus operations is 1 μs, for measuring cycles as well as for CAMAC cycles. The FIFO provides temporary data storage during CAMAC cycles and separates the memory part from the application part. The memory is variable from 1 to 64K (24 bits) by using different types of memory chips. The application part, which forms 1/3 of the module, will be specially designed for each application and is added to the memory chian internal connector. The memory unit will be used in Mössbauer experiments and in thermal neutron scattering experiments.

  6. Difference in Subjective Accessibility of On Demand Recall of Visual, Taste, and Olfactory Memories

    OpenAIRE

    Zach, Petr; Zimmelová, Petra; Mrzílková, Jana; Kutová, Martina

    2018-01-01

    We present here significant difference in the evocation capability between sensory memories (visual, taste, and olfactory) throughout certain categories of the population. As object for this memory recall we selected French fries that are simple and generally known. From daily life we may intuitively feel that there is much better recall of the visual and auditory memory compared to the taste and olfactory ones. Our results in young (age 12–21 years) mostly females and some males show low cap...

  7. The influence of aging on attentional refreshing and articulatory rehearsal during working memory on later episodic memory performance.

    Science.gov (United States)

    Loaiza, Vanessa M; McCabe, David P

    2013-01-01

    We investigated age-related changes in two proposed mechanisms of maintenance in working memory, articulatory rehearsal, and attentional refreshing, by examining the consequences of manipulating the opportunity for each on delayed recall. Both experiments utilized modified operation span tasks to vary the opportunity for articulatory rehearsal (Experiment 1) and attentional refreshing opportunities (Experiment 2). In both experiments, episodic memory was tested for items that had been initially studied during the respective operation span task. Older adults' episodic memory benefited less from opportunities for refreshing than younger adults. In contrast, articulatory rehearsal opportunities did not influence episodic memory for either age group. The results suggest that attentional refreshing, and not articulatory rehearsal, is important during working memory in order to bind more accessible traces at later tests, which appears to be more deficient in older adults than younger adults.

  8. An evaluation testing technique of single event effect using Beam Blanking SEM

    Energy Technology Data Exchange (ETDEWEB)

    Aoki, J; Hada, T; Pesce, A; Akutsu, T; Matsuda, S [National Space Development Agency of Japan, Tsukuba, Ibaraki (Japan). Tsukuba Space Center; Igarashi, T; Baba, S

    1997-03-01

    Beam Blanking SEM (Scanning Electron Microscope) testing technique has been applied to CMOS SRAM devices to evaluate the occurence of soft errors on memory cells. Cross-section versus beam current and LET curves derived from BBSEM and heavy ion testing technique, respectively, have been compared. A linear relation between BBSEM current and heavy ion LET has been found. The purpose of this study was to demonstrate that the application of focused pulsed electron beam could be a reliable, convenient and inexpensive tool to investigate the effects of heavy ions and high energy particles on memory devices for space application. (author)

  9. Conversational assessment in memory clinic encounters: interactional profiling for differentiating dementia from functional memory disorders.

    Science.gov (United States)

    Jones, Danielle; Drew, Paul; Elsey, Christopher; Blackburn, Daniel; Wakefield, Sarah; Harkness, Kirsty; Reuber, Markus

    2016-01-01

    In the UK dementia is under-diagnosed, there is limited access to specialist memory clinics, and many of the patients referred to such clinics are ultimately found to have functional (non-progressive) memory disorders (FMD), rather than a neurodegenerative disorder. Government initiatives on 'timely diagnosis' aim to improve the rate and quality of diagnosis for those with dementia. This study seeks to improve the screening and diagnostic process by analysing communication between clinicians and patients during initial specialist clinic visits. Establishing differential conversational profiles could help the timely differential diagnosis of memory complaints. This study is based on video- and audio recordings of 25 initial consultations between neurologists and patients referred to a UK memory clinic. Conversation analysis was used to explore recurrent communicative practices associated with each diagnostic group. Two discrete conversational profiles began to emerge, to help differentiate between patients with dementia and functional memory complaints, based on (1) whether the patient is able to answer questions about personal information; (2) whether they can display working memory in interaction; (3) whether they are able to respond to compound questions; (4) the time taken to respond to questions; and (5) the level of detail they offer when providing an account of their memory failure experiences. The distinctive conversational profiles observed in patients with functional memory complaints on the one hand and neurodegenerative memory conditions on the other suggest that conversational profiling can support the differential diagnosis of functional and neurodegenerative memory disorders.

  10. Holographic View of the Brain Memory Mechanism Based on Evanescent Superluminal Photons

    Directory of Open Access Journals (Sweden)

    Takaaki Musha

    2012-08-01

    Full Text Available D. Pollen and M. Trachtenberg proposed the holographic brain theory to help explain the existence of photographic memories in some people. They suggested that such individuals had more vivid memories because they somehow could access a very large region of their memory holograms. Hameroff suggested in his paper that cylindrical neuronal microtubule cavities, or centrioles, function as waveguides for the evanescent photons for quantum signal processing. The supposition is that microtubular structures of the brain function as a coherent fiber bundle set used to store holographic images, as would a fiber-optic holographic system. In this paper, the author proposes that superluminal photons propagating inside the microtubules via evanescent waves could provide the access needed to record or retrieve a quantum coherent entangled holographic memory.

  11. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

    CERN Document Server

    Cerjan, C J

    2000-01-01

    The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

  12. Psychological Processes Underlying Cultivation Effects: Further Tests of Construct Accessibility.

    Science.gov (United States)

    Shrum, L. J.

    1996-01-01

    Describes a study that tested whether the accessibility of information in memory mediates the cultivation effect (the effect of television viewing on social perceptions), consistent with the availability heuristic. Shows that heavy viewers gave higher frequency estimates (cultivation effect) and responded faster (accessibility effect) than did…

  13. Trinary Associative Memory Would Recognize Machine Parts

    Science.gov (United States)

    Liu, Hua-Kuang; Awwal, Abdul Ahad S.; Karim, Mohammad A.

    1991-01-01

    Trinary associative memory combines merits and overcomes major deficiencies of unipolar and bipolar logics by combining them in three-valued logic that reverts to unipolar or bipolar binary selectively, as needed to perform specific tasks. Advantage of associative memory: one obtains access to all parts of it simultaneously on basis of content, rather than address, of data. Consequently, used to exploit fully parallelism and speed of optical computing.

  14. Texture and flavour memory in foods : an incidental learning experiment

    NARCIS (Netherlands)

    Mojet, J.; Koster, E.P.

    2002-01-01

    Memory plays a major role in the formation of food expectations. How accessible and how accurate is incidentally acquired and stored product information? In the present experiment the memory for variations in texture (and flavour) was tested with a new and ecologically valid method. Subjects (N=69:

  15. Texture and flavour memory in foods : an incidental learning experiment

    NARCIS (Netherlands)

    Mojet, J.; Köster, E.P.

    2002-01-01

    Memory plays a major role in the formation of food expectations. How accessible and how accurate is incidentally acquired and stored product information? In the present experiment the memory for variations in texture (and flavour) was tested with a new and ecologically valid method. Subjects (N =

  16. Memory-assisted measurement-device-independent quantum key distribution

    Science.gov (United States)

    Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

    2014-04-01

    A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations.

  17. Memory-assisted measurement-device-independent quantum key distribution

    International Nuclear Information System (INIS)

    Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

    2014-01-01

    A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations. (paper)

  18. Architectural design and simulation of a virtual memory

    Science.gov (United States)

    Kwok, G.; Chu, Y.

    1971-01-01

    Virtual memory is an imaginary main memory with a very large capacity which the programmer has at his disposal. It greatly contributes to the solution of the dynamic storage allocation problem. The architectural design of a virtual memory is presented which implements by hardware the idea of queuing and scheduling the page requests to a paging drum in such a way that the access of the paging drum is increased many times. With the design, an increase of up to 16 times in page transfer rate is achievable when the virtual memory is heavily loaded. This in turn makes feasible a great increase in the system throughput.

  19. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  20. An Account of Performance in Accessing Information Stored in Long-Term Memory. A Fixed-Links Model Approach

    Science.gov (United States)

    Altmeyer, Michael; Schweizer, Karl; Reiss, Siegbert; Ren, Xuezhu; Schreiner, Michael

    2013-01-01

    Performance in working memory and short-term memory tasks was employed for predicting performance in a long-term memory task in order to find out about the underlying processes. The types of memory were represented by versions of the Posner Task, the Backward Counting Task and the Sternberg Task serving as measures of long-term memory, working…

  1. Conditional load and store in a shared memory

    Science.gov (United States)

    Blumrich, Matthias A; Ohmacht, Martin

    2015-02-03

    A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

  2. A Collective Study on Modeling and Simulation of Resistive Random Access Memory

    Science.gov (United States)

    Panda, Debashis; Sahu, Paritosh Piyush; Tseng, Tseung Yuen

    2018-01-01

    In this work, we provide a comprehensive discussion on the various models proposed for the design and description of resistive random access memory (RRAM), being a nascent technology is heavily reliant on accurate models to develop efficient working designs and standardize its implementation across devices. This review provides detailed information regarding the various physical methodologies considered for developing models for RRAM devices. It covers all the important models reported till now and elucidates their features and limitations. Various additional effects and anomalies arising from memristive system have been addressed, and the solutions provided by the models to these problems have been shown as well. All the fundamental concepts of RRAM model development such as device operation, switching dynamics, and current-voltage relationships are covered in detail in this work. Popular models proposed by Chua, HP Labs, Yakopcic, TEAM, Stanford/ASU, Ielmini, Berco-Tseng, and many others have been compared and analyzed extensively on various parameters. The working and implementations of the window functions like Joglekar, Biolek, Prodromakis, etc. has been presented and compared as well. New well-defined modeling concepts have been discussed which increase the applicability and accuracy of the models. The use of these concepts brings forth several improvements in the existing models, which have been enumerated in this work. Following the template presented, highly accurate models would be developed which will vastly help future model developers and the modeling community.

  3. Autobiographic memory: phenomenological aspects, personal semantic knowledge, generic events and characters (one case of pure retrograde memory recovery).

    Science.gov (United States)

    Thomas Antérion, C; Mazzola, L; Laurent, B

    2008-06-01

    Tulving et al. [Brain Cogn 8 (1988) 3-20] proposed an operational distinction concerning memory between a semantic component consisting of general information about the individual's past and an episodic component, containing memories of specific events that can be situated in space and time. After a mild head trauma and in the context of professional troubles, patient FF displayed a pure retrograde amnesia concerning both his biographical identity and semantic memories. The patient could no longer access his memories. However, these did not seem completely lost since his answers to tests concerning historical events were better than random, his answers to a television quiz were automatic, he showed temporal transfer phenomena (ecmnesia) and since he retrieved the entirety of his memories within nine months. The patient FF illustrates the loss of retrograde autobiographic memory and the recovery of episodic memories, which requires three elements: a sense of subjective time, an autonoetic awareness (the ability to be aware of subjective time) and a "self" that can travel in subjective time.

  4. Towards scalable parellelism in Monte Carlo particle transport codes using remote memory access

    Energy Technology Data Exchange (ETDEWEB)

    Romano, Paul K [Los Alamos National Laboratory; Brown, Forrest B [Los Alamos National Laboratory; Forget, Benoit [MIT

    2010-01-01

    One forthcoming challenge in the area of high-performance computing is having the ability to run large-scale problems while coping with less memory per compute node. In this work, they investigate a novel data decomposition method that would allow Monte Carlo transport calculations to be performed on systems with limited memory per compute node. In this method, each compute node remotely retrieves a small set of geometry and cross-section data as needed and remotely accumulates local tallies when crossing the boundary of the local spatial domain. initial results demonstrate that while the method does allow large problems to be run in a memory-limited environment, achieving scalability may be difficult due to inefficiencies in the current implementation of RMA operations.

  5. Towards scalable parallelism in Monte Carlo particle transport codes using remote memory access

    International Nuclear Information System (INIS)

    Romano, Paul K.; Forget, Benoit; Brown, Forrest

    2010-01-01

    One forthcoming challenge in the area of high-performance computing is having the ability to run large-scale problems while coping with less memory per compute node. In this work, we investigate a novel data decomposition method that would allow Monte Carlo transport calculations to be performed on systems with limited memory per compute node. In this method, each compute node remotely retrieves a small set of geometry and cross-section data as needed and remotely accumulates local tallies when crossing the boundary of the local spatial domain. Initial results demonstrate that while the method does allow large problems to be run in a memory-limited environment, achieving scalability may be difficult due to inefficiencies in the current implementation of RMA operations. (author)

  6. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    Science.gov (United States)

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-07

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  7. Amorphous Semiconductors: From Photocatalyst to Computer Memory

    Science.gov (United States)

    Sundararajan, Mayur

    encouraging but inconclusive. Then the method was successfully demonstrated on mesoporous TiO2SiO 2 by showing a shift in its optical bandgap. One of the special class of amorphous semiconductors is chalcogenide glasses, which exhibit high ionic conductivity even at room temperature. When metal doped chalcogenide glasses are under an electric field, they become electronically conductive. These properties are exploited in the computer memory storage application of Conductive Bridging Random Access Memory (CBRAM). CBRAM is a non-volatile memory that is a strong contender to replace conventional volatile RAMs such as DRAM, SRAM, etc. This technology has already been commercialized, but the working mechanism is still not clearly understood especially the nature of the conductive bridge filament. In this project, the CBRAM memory cells are fabricated by thermal evaporation method with Agx(GeSe 2)1-x as the solid electrolyte layer, Ag as the active electrode and Au as the inert electrode. By careful use of cyclic voltammetry, the conductive filaments were grown on the surface and the bulk of the solid electrolyte. The comparison between the two filaments revealed major differences leading to contradiction with the existing working mechanism. After compiling all the results, a modified working mechanism is proposed. SAXS is a powerful tool to characterize nanostructure of glasses. The analysis of the SAXS data to get useful information are usually performed by different programs. In this project, Irena and GIFT programs were compared by performing the analysis of the SAXS data of glass and glass ceramics samples. Irena was shown to be not suitable for the analysis of SAXS data that has a significant contribution from interparticle interactions. GIFT was demonstrated to be better suited for such analysis. Additionally, the results obtained by programs for samples with low interparticle interactions were shown to be consistent.

  8. External-Memory Algorithms and Data Structures

    DEFF Research Database (Denmark)

    Arge, Lars; Zeh, Norbert

    2010-01-01

    The data sets involved in many modern applications are often too massive to fit in main memory of even the most powerful computers and must therefore reside on disk. Thus communication between internal and external memory, and not actual computation time, becomes the bottleneck in the computation....... This is due to the huge difference in access time of fast internal memory and slower external memory such as disks. The goal of theoretical work in the area of external memory algorithms (also called I/O algorithms or out-of-core algorithms) has been to develop algorithms that minimize the Input...... in parallel and the use of parallel disks has received a lot of theoretical attention. See below for recent surveys of theoretical results in the area of I/O-efficient algorithms. TPIE is designed to bridge the gap between the theory and practice of parallel I/O systems. It is intended to demonstrate all...

  9. All ITO-based transparent resistive switching random access memory using oxygen doping method

    International Nuclear Information System (INIS)

    Kim, Hee-Dong; Yun, Min Ju; Kim, Sungho

    2015-01-01

    Recently, transparent memory would be useful in invisible electronics. In this work, for the first time we present a feasibility of stable unipolar resistive switching (RS) characteristics with reset current of sub-micron ampere for the fully transparent ITO/oxygen-doped ITO/ITO memory capacitors, i.e., all ITO structures, produced by sputtering method, which shows a high optical transmittance of approximately 80% in the visible region as well as near ultra-violet region. In addition, in a RS test to evaluate a reliability for the proposed memory devices, we observed a stable endurance of >100 cycles and a retention time of >10 4  s at 85 °C, with a current ratio of ∼10 2 to ∼10 3 . This result indicates that this transparent memory by engineering the amount of oxygen ions within the ITO films could be a milestone for future see-through electronic devices. - Highlights: • The resistive switching characteristics of the transparent ITO/O-doped ITO/ITO RRAM cells have investigated. • All ITO-based RRAM cell is achieved using oxygen doping method. • Good endurance and long retention time were observed.

  10. The dynamics of sensory buffers: geometric, spatial, and experience-dependent shaping of iconic memory.

    Science.gov (United States)

    Graziano, Martin; Sigman, Mariano

    2008-05-23

    When a stimulus is presented, its sensory trace decays rapidly, lasting for approximately 1000 ms. This brief and labile memory, referred as iconic memory, serves as a buffer before information is transferred to working memory and executive control. Here we explored the effect of different factors--geometric, spatial, and experience--with respect to the access and the maintenance of information in iconic memory and the progressive distortion of this memory. We studied performance in a partial report paradigm, a design wherein recall of only part of a stimulus array is required. Subjects had to report the identity of a letter in a location that was cued in a variable delay after the stimulus onset. Performance decayed exponentially with time, and we studied the different parameters (time constant, zero-delay value, and decay amplitude) as a function of the different factors. We observed that experience (determined by letter frequency) affected the access to iconic memory but not the temporal decay constant. On the contrary, spatial position affected the temporal course of delay. The entropy of the error distribution increased with time reflecting a progressive morphological distortion of the iconic buffer. We discuss our results on the context of a model of information access to executive control and how it is affected by learning and attention.

  11. submitter Methodologies for the Statistical Analysis of Memory Response to Radiation

    CERN Document Server

    Bosser, Alexandre L; Tsiligiannis, Georgios; Frost, Christopher D; Zadeh, Ali; Jaatinen, Jukka; Javanainen, Arto; Puchner, Helmut; Saigne, Frederic; Virtanen, Ari; Wrobel, Frederic; Dilillo, Luigi

    2016-01-01

    Methodologies are proposed for in-depth statistical analysis of Single Event Upset data. The motivation for using these methodologies is to obtain precise information on the intrinsic defects and weaknesses of the tested devices, and to gain insight on their failure mechanisms, at no additional cost. The case study is a 65 nm SRAM irradiated with neutrons, protons and heavy ions. This publication is an extended version of a previous study [1].

  12. From sensory to long-term memory: evidence from auditory memory reactivation studies.

    Science.gov (United States)

    Winkler, István; Cowan, Nelson

    2005-01-01

    Everyday experience tells us that some types of auditory sensory information are retained for long periods of time. For example, we are able to recognize friends by their voice alone or identify the source of familiar noises even years after we last heard the sounds. It is thus somewhat surprising that the results of most studies of auditory sensory memory show that acoustic details, such as the pitch of a tone, fade from memory in ca. 10-15 s. One should, therefore, ask (1) what types of acoustic information can be retained for a longer term, (2) what circumstances allow or help the formation of durable memory records for acoustic details, and (3) how such memory records can be accessed. The present review discusses the results of experiments that used a model of auditory recognition, the auditory memory reactivation paradigm. Results obtained with this paradigm suggest that the brain stores features of individual sounds embedded within representations of acoustic regularities that have been detected for the sound patterns and sequences in which the sounds appeared. Thus, sounds closely linked with their auditory context are more likely to be remembered. The representations of acoustic regularities are automatically activated by matching sounds, enabling object recognition.

  13. Electrical characterization of doped semiconductor nanostructures with scanning microwave microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Fenner, Matthias A.; Tanbakuchi, Hassan [Agilent Technologies, Kronberg (Germany); Streit, Stephan; Baumgart, Christine; Helm, Manfred; Schmidt, Heidemarie [Institute of Ion Beam Physics and Materials Research, Forschungszentrum Dresden-Rossendorf e.V., Dresden (Germany)

    2010-07-01

    Highly sensitive scanning microwave microscopy (SMM) with a capacitance resolution in the aF range has been used to investigate the electrical properties of doped semiconductor nanostructures in the microwave frequency range from 1.5 GHz to 6 GHz at different dc offset biases. The microwave signal S11 reflected by the sample is related to the impedance of the sample. Superimposing an ac voltage in the kHz range one also gains information about the derivative of the S11 signal (dC/dV), which is dependent on the doping density in the semiconductor, circuit resistance, and reactance. We investigated a static random access memory (SRAM) cell and one cross-sectionally prepared Si epilayer structured sample. The derivative of S11 strongly depends on the dc offset bias. The Si epilayer sample reveals the strongest dependence on f{sub ac} and also on the biasing history during the SMM measurements.

  14. An IPv6 routing lookup algorithm using weight-balanced tree based on prefix value for virtual router

    Science.gov (United States)

    Chen, Lingjiang; Zhou, Shuguang; Zhang, Qiaoduo; Li, Fenghua

    2016-10-01

    Virtual router enables the coexistence of different networks on the same physical facility and has lately attracted a great deal of attention from researchers. As the number of IPv6 addresses is rapidly increasing in virtual routers, designing an efficient IPv6 routing lookup algorithm is of great importance. In this paper, we present an IPv6 lookup algorithm called weight-balanced tree (WBT). WBT merges Forwarding Information Bases (FIBs) of virtual routers into one spanning tree, and compresses the space cost. WBT's average time complexity and the worst case time complexity of lookup and update process are both O(logN) and space complexity is O(cN) where N is the size of routing table and c is a constant. Experiments show that WBT helps reduce more than 80% Static Random Access Memory (SRAM) cost in comparison to those separation schemes. WBT also achieves the least average search depth comparing with other homogeneous algorithms.

  15. Rhesus monkeys see who they hear: spontaneous cross-modal memory for familiar conspecifics.

    Directory of Open Access Journals (Sweden)

    Ikuma Adachi

    Full Text Available Rhesus monkeys gather much of their knowledge of the social world through visual input and may preferentially represent this knowledge in the visual modality. Recognition of familiar faces is clearly advantageous, and the flexibility and utility of primate social memory would be greatly enhanced if visual memories could be accessed cross-modally either by visual or auditory stimulation. Such cross-modal access to visual memory would facilitate flexible retrieval of the knowledge necessary for adaptive social behavior. We tested whether rhesus monkeys have cross-modal access to visual memory for familiar conspecifics using a delayed matching-to-sample procedure. Monkeys learned visual matching of video clips of familiar individuals to photographs of those individuals, and generalized performance to novel videos. In crossmodal probe trials, coo-calls were played during the memory interval. The calls were either from the monkey just seen in the sample video clip or from a different familiar monkey. Even though the monkeys were trained exclusively in visual matching, the calls influenced choice by causing an increase in the proportion of errors to the picture of the monkey whose voice was heard on incongruent trials. This result demonstrates spontaneous cross-modal recognition. It also shows that viewing videos of familiar monkeys activates naturally formed memories of real monkeys, validating the use of video stimuli in studies of social cognition in monkeys.

  16. Sight Word Reading in Prereaders: Use of Logographic vs. Alphabetic Access Routes.

    Science.gov (United States)

    Scott, Judith Anne; Ehri, Linnea C.

    1990-01-01

    Investigates whether prereaders who knew all their letters are better at forming logographic access routes than letter-sound access routes into memory from words read by sight. Concludes that prereaders become capable of forming letter-sound access routes when they learn letters well enough to take advantage of the phonetic cues the letters…

  17. Electrophysiological correlates of exemplar-specific processes in implicit and explicit memory.

    Science.gov (United States)

    Küper, Kristina; Groh-Bordin, Christian; Zimmer, Hubert D; Ecker, Ullrich K H

    2012-03-01

    The present ERP study investigated the retrieval of task-irrelevant exemplar-specific information under implicit and explicit memory conditions. Subjects completed either an indirect memory test (a natural/artificial judgment) or a direct recognition memory test. Both test groups were presented with new items, identical repetitions, and perceptually different but conceptually similar exemplars of previously seen study objects. Implicit and explicit memory retrieval elicited clearly dissociable ERP components that were differentially affected by exemplar changes from study to test. In the indirect test, identical repetitions, but not different exemplars, elicited a significant ERP repetition priming effect. In contrast, both types of repeated objects gave rise to a reliable old/new effect in the direct test. The results corroborate that implicit and explicit memory fall back on distinct cognitive representation and, more importantly, indicate that these representations differ in the type of stimulus information stored. Implicit retrieval entailed obligatory access to exemplar-specific perceptual information, despite its being task irrelevant. In contrast, explicit retrieval proved to be more flexible with conceptual and perceptual information accessed according to task demands.

  18. In-Memory Business Intelligence: Concepts and Performance

    Science.gov (United States)

    Rantung, V. P.; Kembuan, O.; Rompas, P. T. D.; Mewengkang, A.; Liando, O. E. S.; Sumayku, J.

    2018-02-01

    This research aims to discuss in-memory Business Intelligent (BI) and to model the business analysis questions to know the performance of the in-memory BI. By using, the Qlickview application found BI dashboards that easily accessed and modified. The dashboards are developed together using an agile development approach such as pre-study, planning, iterative execution, implementation, and evaluation. At the end, this research helping analyzer in choosing a right implementation for BI solution.

  19. Application of phase-change materials in memory taxonomy

    OpenAIRE

    Wang, Lei; Tu, Liang; Wen, Jing

    2017-01-01

    Abstract Phase-change materials are suitable for data storage because they exhibit reversible transitions between crystalline and amorphous states that have distinguishable electrical and optical properties. Consequently, these materials find applications in diverse memory devices ranging from conventional optical discs to emerging nanophotonic devices. Current research efforts are mostly devoted to phase-change random access memory, whereas the applications of phase-change materials in other...

  20. A memory module for experimental data handling

    International Nuclear Information System (INIS)

    Blois, J. de

    1985-01-01

    A compact CAMAC memory module for experimental data handling was developed to eliminate the need of direct memory access in computer controlled measurements. When using autonomous controllers it also makes measurements more independent of the program and enlarges the available space for programs in the memory of the micro-computer. The memory module has three modes of operation: an increment-, a list- and a fifo mode. This is achieved by connecting the main parts, being: the memory (MEM), the fifo buffer (FIFO), the address buffer (BUF), two counters (AUX and ADDR) and a readout register (ROR), by an internal 24-bit databus. The time needed for databus operations is 1 μs, for measuring cycles as well as for CAMAC cycles. The FIFO provides temporary data storage during CAMAC cycles and separates the memory part from the application part. The memory is variable from 1 to 64K (24 bits) by using different types of memory chips. The application part, which forms 1/3 of the module, will be specially designed for each application and is added to the memory by an internal connector. The memory unit will be used in Moessbauer experiments and in thermal neutron scattering experiments. (orig.)

  1. Object selection costs in visual working memory: A diffusion model analysis of the focus of attention.

    Science.gov (United States)

    Sewell, David K; Lilburn, Simon D; Smith, Philip L

    2016-11-01

    A central question in working memory research concerns the degree to which information in working memory is accessible to other cognitive processes (e.g., decision-making). Theories assuming that the focus of attention can only store a single object at a time require the focus to orient to a target representation before further processing can occur. The need to orient the focus of attention implies that single-object accounts typically predict response time costs associated with object selection even when working memory is not full (i.e., memory load is less than 4 items). For other theories that assume storage of multiple items in the focus of attention, predictions depend on specific assumptions about the way resources are allocated among items held in the focus, and how this affects the time course of retrieval of items from the focus. These broad theoretical accounts have been difficult to distinguish because conventional analyses fail to separate components of empirical response times related to decision-making from components related to selection and retrieval processes associated with accessing information in working memory. To better distinguish these response time components from one another, we analyze data from a probed visual working memory task using extensions of the diffusion decision model. Analysis of model parameters revealed that increases in memory load resulted in (a) reductions in the quality of the underlying stimulus representations in a manner consistent with a sample size model of visual working memory capacity and (b) systematic increases in the time needed to selectively access a probed representation in memory. The results are consistent with single-object theories of the focus of attention. The results are also consistent with a subset of theories that assume a multiobject focus of attention in which resource allocation diminishes both the quality and accessibility of the underlying representations. (PsycINFO Database Record (c) 2016

  2. Memory Loss and Retrieval

    Science.gov (United States)

    Reid, Ian

    2016-01-01

    Underlying the generally oblivious attitude of teachers and learners towards the past is insufficient respect for the role of memory in giving meaning to experience and access to knowledge. We shape our identity by making sense of our past and its relationship to present and future selves, a process that should be intensively cultivated when we…

  3. Working memory biasing of visual perception without awareness.

    Science.gov (United States)

    Pan, Yi; Lin, Bingyuan; Zhao, Yajun; Soto, David

    2014-10-01

    Previous research has demonstrated that the contents of visual working memory can bias visual processing in favor of matching stimuli in the scene. However, the extent to which such top-down, memory-driven biasing of visual perception is contingent on conscious awareness remains unknown. Here we showed that conscious awareness of critical visual cues is dispensable for working memory to bias perceptual selection mechanisms. Using the procedure of continuous flash suppression, we demonstrated that "unseen" visual stimuli during interocular suppression can gain preferential access to awareness if they match the contents of visual working memory. Strikingly, the very same effect occurred even when the visual cue to be held in memory was rendered nonconscious by masking. Control experiments ruled out the alternative accounts of repetition priming and different detection criteria. We conclude that working memory biases of visual perception can operate in the absence of conscious awareness.

  4. Post-irradiation effects in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

    1988-01-01

    The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

  5. Alpha radiation detection using silicon memory chips - preliminary studies

    International Nuclear Information System (INIS)

    Pace, R.; Paix, D.; Haskard, M.

    1993-01-01

    Alpha radiation dosage is an important occupational health factor in the mining of uranium and mineral sands. Alpha radiation induced errors in the data of silicon based memory chips provide the foundation for a new type of sensor, with the potential for affordable and prompt measurement of personal alpha doses. With particular reference to Dynamic Random Access Memories (DRAM) this paper introduces the operating principle of a memory based radiation sensor, which is the error mechanism in silicon integrated circuits. 14 refs., 3 figs

  6. Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

    Energy Technology Data Exchange (ETDEWEB)

    Tomczak, Y., E-mail: Yoann.Tomczak@imec.be [IMEC Kapeldreef 75, B-3001 Leuven (Belgium); Department of Chemistry, KU Leuven (University of Leuven), Celestijnenlaan 200F, B-3001 Leuven (Belgium); Swerts, J.; Mertens, S.; Lin, T.; Couet, S.; Sankaran, K.; Pourtois, G.; Kim, W.; Souriau, L.; Van Elshocht, S.; Kar, G.; Furnemont, A. [IMEC Kapeldreef 75, B-3001 Leuven (Belgium); Liu, E. [Department of Chemistry, KU Leuven (University of Leuven), Celestijnenlaan 200F, B-3001 Leuven (Belgium)

    2016-01-25

    Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm{sup 2} after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

  7. What happens during a Join? - Dissecting CPU and Memory Optimization Effects

    OpenAIRE

    Manegold, Stefan; Boncz, Peter; Kersten, Martin

    2000-01-01

    textabstractPerformance of modern hardware increasingly depends on proper utilization of both the memory cache hierarchy and parallel execution possibilities in todays super-scalar CPUs. Recent database research has demonstrated that database system performance severely suffers from poor utilization of these resources. In previous work, we presented join algorithms that strongly accelerate large equi-join by tuning the memory access pattern to match the characteristics of the memory cache sub...

  8. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    Energy Technology Data Exchange (ETDEWEB)

    Dawson, J. A., E-mail: jad95@cam.ac.uk; Guo, Y.; Robertson, J. [Department of Engineering, University of Cambridge, Cambridge CB2 1PZ (United Kingdom)

    2015-09-21

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.

  9. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    International Nuclear Information System (INIS)

    Dawson, J. A.; Guo, Y.; Robertson, J.

    2015-01-01

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour

  10. Memory Dynamics and Decision Making in Younger and Older Adults

    Science.gov (United States)

    Lechuga, M. Teresa; Gomez-Ariza, Carlos J.; Iglesias-Parro, Sergio; Pelegrina, Santiago

    2012-01-01

    The main aim of this research was to study whether memory dynamics influence older people's choices to the same extent as younger's ones. To do so, we adapted the retrieval-practice paradigm to produce variations in memory accessibility of information on which decisions were made later. Based on previous results, we expected to observe…

  11. Beyond accessibility? Toward an on-line and memory-based model of framing effects

    OpenAIRE

    Matthes, Jörg

    2007-01-01

    This theoretical article investigates the effects of media frames on individuals' judgments. In contrast to previous theorizing, we suggest that framing scholars should embrace both, on-line and memory-based judgment formation processes. Based on that premise, we propose a model that distinguishes between two phases of framing effects. Along the first phase, the media's framing contributes to the formation of an on-line or a memory-based judgment. The second phase describes six hypothetical r...

  12. A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications.

    Science.gov (United States)

    Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

    2018-04-09

    As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 10 6 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

  13. Lost for words or loss of memories? Autobiographical memory in semantic dementia.

    Science.gov (United States)

    Moss, H E; Kopelman, M D; Cappelletti, M; Davies, P de Mornay; Jaldow, E

    2003-12-01

    Recent reports have suggested that patients with semantic dementia show a loss of early (remote) auto-biographical memories with pronounced sparing of recent memories (Graham & Hodges, 1997; Snowden, Griffiths, & Neary, 1996), i.e., a 'reversed' temporal gradient or 'Ribot effect'. At first sight, these findings suggest that the deficits in 'semantic' dementia go beyond the semantic domain, involving aspects of autobiographical (episodic) memory. It has also been proposed that there is a 'step-like' function with personal memories preserved for 18 months to 2 years in the immediate past. This view is consistent with the theory that the hippocampal complex/medial temporal lobe (relatively intact in semantic dementia) plays a time-limited role in the acquisition and storage of memories, while the temporal neocortex (damaged in semantic dementia) is required for long-term storage and retrieval. In this study we ask whether (a) previous tests have underestimated the integrity of remote memory in semantic dementia as a result of not allowing for these patients' comprehension and language production difficulties, and (b) whether a recency effect, if obtained, is genuinely step-like or more graded. We used a cued autobiographical memory interview with semantic dementia patient, IH, to examine the effect of providing increasingly specific lexical cues to probe salient events throughout his lifespan. Results demonstrated that the provision of specific cues enabled IH to access and express memories from his childhood and early adulthood as well as from more recent times. There was a gentle recency effect only for intermediate levels of cueing, indicating that recent memories were easier to retrieve and/or express in the absence of specific cues, but this effect was graded, with no evidence of a step-like cut-off at 18 months or 2 years before testing. In brief, our findings are consistent with the view that the deficits in semantic dementia are predominantly or exclusively

  14. Retrieval of memories with the help of music in Alzheimer's disease.

    Science.gov (United States)

    Chevreau, Priscilia; Nizard, Ingrid; Allain, Philippe

    2017-09-01

    This study focuses on music as a mediator facilitating access to autobiographical memory in Alzheimer's disease (AD). Studies on this topic are rare, but available data have shown a beneficial effect of music on autobiographical performance in AD patients. Based on the "index word" method, we developed the "index music" method for the evaluation of autobiographical memory. The subjects had to tell a memory of their choice from the words or music presented to them. The task was proposed to 54 patients with diagnosis of AD according to DSM IV and NINCDS-ADRDA criteria. All of them had a significant cognitive decline on the MMSE (mean score: 14.5). Patients were matched by age, sex and level of education with 48 control subjects without cognitive impairment (mean score on the MMSE: 28). Results showed that autobiographical memory quantity scores of AD patients were significantly lower than those of healthy control in both methods. However, autobiographical memory quality scores of AD patients increased with "index music" whereas autobiographical memory quality scores of healthy control decreased. Also, the autobiographical performance of patients with AD in condition index music was not correlated with cognitive performance in contrast to the autobiographical performances in index word. These results confirm that music improves access to personal memories in patients with AD. Personal memories could be preserved in patients with AD and music could constitute an interesting way to stimulate recollection.

  15. Episodic-like memory in the rat.

    Science.gov (United States)

    Babb, Stephanie J; Crystal, Jonathon D

    2006-07-11

    A fundamental question in comparative cognition is whether animals remember unique, personal past experiences. It has long been argued that memories for specific events (referred to as episodic memory) are unique to humans. Recently, considerable evidence has accumulated to show that food-storing birds possess critical behavioral elements of episodic memory, referred to as episodic-like memory in acknowledgment of the fact that behavioral criteria do not assess subjective experiences. Here we show that rats have a detailed representation of remembered events and meet behavioral criteria for episodic-like memory. We provided rats with access to locations baited with distinctive (e.g., grape and raspberry) or nondistinctive (regular chow) flavors. Locations with a distinctive flavor replenished after a long but not a short delay, and locations with the nondistinctive flavor never replenished. One distinctive flavor was devalued after encoding its location by prefeeding that flavor (satiation) or by pairing it with lithium chloride (acquired taste aversion), while the other distinctive flavor was not devalued. The rats selectively decreased revisits to the devalued distinctive flavor but not to the nondevalued distinctive flavor. The present studies demonstrate that rats selectively encode the content of episodic-like memories.

  16. Resonator memories and optical novelty filters

    Science.gov (United States)

    Anderson, Dana Z.; Erle, Marie C.

    Optical resonators having holographic elements are potential candidates for storing information that can be accessed through content addressable or associative recall. Closely related to the resonator memory is the optical novelty filter, which can detect the differences between a test object and a set of reference objects. We discuss implementations of these devices using continuous optical media such as photorefractive materials. The discussion is framed in the context of neural network models. There are both formal and qualitative similarities between the resonator memory and optical novelty filter and network models. Mode competition arises in the theory of the resonator memory, much as it does in some network models. We show that the role of the phenomena of "daydreaming" in the real-time programmable optical resonator is very much akin to the role of "unlearning" in neural network memories. The theory of programming the real-time memory for a single mode is given in detail. This leads to a discussion of the optical novelty filter. Experimental results for the resonator memory, the real-time programmable memory, and the optical tracking novelty filter are reviewed. We also point to several issues that need to be addressed in order to implement more formal models of neural networks.

  17. Non-volatile memory based on the ferroelectric photovoltaic effect

    Science.gov (United States)

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  18. `Unlearning' has a stabilizing effect in collective memories

    Science.gov (United States)

    Hopfield, J. J.; Feinstein, D. I.; Palmer, R. G.

    1983-07-01

    Crick and Mitchison1 have presented a hypothesis for the functional role of dream sleep involving an `unlearning' process. We have independently carried out mathematical and computer modelling of learning and `unlearning' in a collective neural network of 30-1,000 neurones. The model network has a content-addressable memory or `associative memory' which allows it to learn and store many memories. A particular memory can be evoked in its entirety when the network is stimulated by any adequate-sized subpart of the information of that memory2. But different memories of the same size are not equally easy to recall. Also, when memories are learned, spurious memories are also created and can also be evoked. Applying an `unlearning' process, similar to the learning processes but with a reversed sign and starting from a noise input, enhances the performance of the network in accessing real memories and in minimizing spurious ones. Although our model was not motivated by higher nervous function, our system displays behaviours which are strikingly parallel to those needed for the hypothesized role of `unlearning' in rapid eye movement (REM) sleep.

  19. A short cut to the past: Cueing via concrete objects improves autobiographical memory retrieval in Alzheimer's disease patients.

    Science.gov (United States)

    Kirk, Marie; Berntsen, Dorthe

    2018-02-01

    Older adults diagnosed with Alzheimer's disease (AD) have difficulties accessing autobiographical memories. However, this deficit tends to spare memories dated to earlier parts of their lives, and may partially reflect retrieval deficits rather than complete memory loss. Introducing a novel paradigm, the present study examines whether autobiographical memory recall can be improved in AD by manipulating the sensory richness, concreteness and cultural dating of the memory cues. Specifically, we examine whether concrete everyday objects historically dated to the participants' youth (e.g., a skipping rope), relative to verbal cues (i.e., the verbal signifiers for the objects) facilitate access to autobiographical memories. The study includes 49 AD patients, and 50 healthy, older matched control participants, all tested on word versus object-cued recall. Both groups recalled significantly more memories, when cued by objects relative to words, but the advantage was significantly larger in the AD group. In both groups, memory descriptions were longer and significantly more episodic in nature in response to object-cued recall. Together these findings suggest that the multimodal nature of the object cues (i.e. vision, olfaction, audition, somatic sensation) along with specific cue characteristics, such as time reference, texture, shape, may constrain the retrieval search, potentially minimizing executive function demands, and hence strategic processing requirements, thus easing access to autobiographical memories in AD. Copyright © 2017 Elsevier Ltd. All rights reserved.

  20. Using organisational memory in evaluations

    Directory of Open Access Journals (Sweden)

    Madri S. Jansen van Rensburg

    2014-12-01

    Full Text Available This article uses the case of a regional intermediary organisation to investigate organisational memory (OM and its contribution to knowledge management and activities in evaluations. Understanding of, and accessing OM is critical for participatory evaluations. The aim of the article is to reflect on the OM of a non-governmental organisation (NGO and what implicationsthe structural changes in OM over the organisation’s life cycle have for evaluators. It further aims to advocate an awareness of OM and explains how evaluators can access and utilise it more effectively. Evaluators need to have an understanding of OM, and to take more responsibility for disseminating results to enhance it. This case study reflects on a retrospective case example of a regional NGO. The report reflects the development and structure of the life cycle of the organisation. The data collection included in-depth interviews with staff members and other key stakeholders, engagement with beneficiary organisations and donors, and analyses of documents, electronic files and audio-visual material. Since OM survives after the demise of an organisation, and is accessible through directories, it is important for the evaluator to include historical information. Specific implications for evaluators include the ability to access OM through directories and networks of the organisation. As evaluators hold OM of all the organisations they have engaged with, they also have a responsibility to share knowledge. The key findings of this study illustrate the importance of accessing the memory and historical information of the organisation. Understanding OM enhances the in-depth comprehension of the activity, project or programme under investigation, and the collective knowledge generated as a result of it.