WorldWideScience

Sample records for 1-v 90-nm cmos

  1. Design Rules and Electrical Parameters for a 90nm CMOS process

    DEFF Research Database (Denmark)

    Stassen, Flemming

    2007-01-01

    A set of fictitious simplified geometrical design rules and tables of electrical parameters are presented describing a 90nm CMOS process for educational purposes only.......A set of fictitious simplified geometrical design rules and tables of electrical parameters are presented describing a 90nm CMOS process for educational purposes only....

  2. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    Science.gov (United States)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  3. A new single-photon avalanche diode in 90nm standard CMOS technology

    NARCIS (Netherlands)

    Karami, M.A.; Gersbach, M.; Charbon, E.

    2010-01-01

    A single-photon avalanche diode (SPAD) fabricated in a 90nm standard CMOS process is reported. The detector comprises an octagonal multiplication region and a guard ring to prevent premature edge breakdown using exclusively standard layers. The proposed structure is the result of a systematic study

  4. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    CERN Document Server

    Rivetti, A; Wyss, J; Bisello, D; Costa, M; Kloukinas, K; Demaria, N; Pantano, D; Rousset, J; Battaglia, M; Mansuy, C; Potenza, A; Ikemoto, Y; Giubilato, P; Chalmet, P; Mugnier, H; Silvestrin, L; Marchioro, A

    2013-01-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Omega cm, which is at least one order of magnitude greater than the typical value (1-10 Omega cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. (C) 2013 Elsevier B.V. All rights reserved

  5. Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

    Directory of Open Access Journals (Sweden)

    D. Arbet

    2014-09-01

    Full Text Available In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC based on digitally compensated input offset of the operational amplifier (OPAMP is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.

  6. A 10-bit low power SAR A/D converter based on 90 nm CMOS

    Institute of Scientific and Technical Information of China (English)

    Tong Xingyuan; Yang Yintang; Zhu Zhangming; Xiao Yan; Chen Jianming

    2009-01-01

    Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.

  7. Investigation of the characteristics of GIDL current in 90nm CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Chen Hai-Feng; Hao Yue; Ma Xiao-Hua; Zhang Jin-Cheng; Li Kang; Cao Yan-Rong; Zhang Jin-Feng; Zhou Peng-Ju

    2006-01-01

    A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG-It is found that the difference between ID in the off-state ID-VG characteristics and the corresponding one in the off-state ID-VD characteristics, which is defined as /DIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by /DIFF, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum /DIFF(IDIFF.MAX) varies linearly with VDG in logarithmic coordinates and also VDG at IDIFF.MAX with VF which is the characteristic voltage of /DIFF- The relations are studied and some related expressions are given.

  8. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU) Processor Controller

    OpenAIRE

    2012-01-01

    In this present study includes the Very Large Scale Integration (VLSI) system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS) Arithmetic and Logic Unit (ALU) processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90n...

  9. 10-bit segmented current steering DAC in 90nm CMOS technology

    Science.gov (United States)

    Bringas, R., Jr.; Dy, F.; Gerasta, O. J.

    2015-06-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

  10. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    Science.gov (United States)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  11. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  12. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  13. The temperature dependence of single-event transients in 90-nm CMOS dual-well and triple-well NMOSFETs

    Institute of Scientific and Technical Information of China (English)

    Li Da-Wei; Qin Jun-Rui; Chen Shu-Ming

    2013-01-01

    This paper investigates the temperature dependence of single-event transients (SETs) in 90-nm complementary metat-oxide semiconductor (CMOS) dual-well and triple-well negative metal-oxide semiconductor field-effect transistors (NMOSFETs).Technology computer-aided design (TCAD) three-dimensional (3D) simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55 ℃C to 125 ℃C,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.

  14. 90nm CMOS数字工艺实现的低抖动时钟锁相环设计%A Low Jitter PLL in a 90nm CMOS Digital Process

    Institute of Scientific and Technical Information of China (English)

    尹海丰; 王峰; 刘军; 毛志刚

    2008-01-01

    A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabrica-ted in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power con-sumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.%用90nmCMOS数字工艺设计实现了一个低抖动的时钟锁相环.锁相环不需要"模拟"的电阻和电容,采用金属间的寄生电容作为环路滤波器的电容.测试结果显示,锁相环锁定在1.989GHz时的均方抖动为3.7977ps,周期峰峰值抖动为31.225ps,核心功耗约为9mW.锁相环可稳定输出的频率范围为125MHz到2.7GHz.

  15. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, D.; Klumperink, E.A.M.; Tuijl, van A.J.M.; Nauta, B.

    2007-01-01

    Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previou

  16. A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS

    DEFF Research Database (Denmark)

    Wismar, Ulrik Sørensen; Wisland, D; Andreani, Pietro

    2007-01-01

    This paper presents a frequency-to-digital SigmaDelta modulator designed in a digital 90nm CMOS process, operating with a supply voltage of 0.2 V. For a 7.5 muW power consumption, the SNR is 68.9 dB and the SNDR is 60.3 dB over a 20Hz-20kHz bandwidth. This work shows that the SNR/SNDR performance...

  17. Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

    Science.gov (United States)

    Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

    2012-01-01

    Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

  18. Impact of STI Depth on Charge Sharing in 90nm CMOS Technology%90纳米CMOS双阱工艺下STI深度对电荷共享的影响

    Institute of Scientific and Technical Information of China (English)

    刘衡竹; 刘凡宇; 刘必慰; 梁斌

    2011-01-01

    基于3维TCAD器件模拟,研究了90nm CMOS双阱工艺下STI对电荷共享的影响.研究结果表明:增大STI深度能有效抑制NMOS电荷共享,且550nm为抑制电荷共享的有效深度,超过这个深度收集的电荷量几乎保持不变;而对于PMOS,STI深度的增加使电荷共享线性减小.这对于电荷共享加固具有重要指导意义.%THe dependence of various STI depths on charge sharing in 90nm dual well CMOS technology was investigated. TCAD simulation results show that increasing STI can restrain charge sharing of NMOS effectively, and 550nm is the effective depth for the prevention of charge diffusion, beyond which the collected charge almost keeps constant; for PMOS, charge sharing decreases linearly with the increment of STI depth. This conclusion is useful for irradiation-hardness.

  19. Design of an adaptive LNA for hand-held devices in a 1-V 90-nm standard RF CMOS technology: From circuit analysis to layout

    OpenAIRE

    2009-01-01

    [ES]: Este trabajo presenta el diseño de un amplificador de bajo ruido, LNA (del inglés Low‐Noise Amplifier) reconfigurable para la siguiente generación de dispositivos portátiles de comunicación inalámbricos, usando la aproximación de circuitos concentrados sustentada en leyes físicas. El propósito de este trabajo no es sólo presentar resultados de simulación que muestran el cumplimiento de especificaciones para cada estándar, sino también demostrar que cada paso de diseño ...

  20. A sub-1 V high-precision CMOS bandgap voltage reference

    Institute of Scientific and Technical Information of China (English)

    廖峻; 赵毅强; 耿俊峰

    2012-01-01

    A third-order,sub-1 V bandgap voltage reference design for low-power supply,high-precision applications is presented.This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation.The circuit was designed and fabricated by SMIC 0.18μm CMOS technology.It produces an output reference of 713.6 mV.The temperature coefficient is 3.235 pprn/℃ in the temperature range of-40 to 120 ℃,with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V.The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.

  1. A 1V Phase Frequency Detector (PFD with 180nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    N . K . Kaphungkui

    2013-02-01

    Full Text Available In this paper, designing of a Phase frequency detector with 180nm CMOS technology is presented. The main objective of the designed circuit is to reduce the power dissipation with a low voltage supply of 1V. Phase frequency detector has a wide range of applications but one of the main application is in modern day phased locked loop, it serve as a main building block. PFD (Phase Frequency Detector is a circuit that measures the phase and frequency difference between two signals, and has two outputs UP and DOWN which are signalled according to the phase and frequency difference of the two input signals. The designed circuit shows a satisfactory result with the low supply voltage. The detection of phase difference occurs only at the rising edge of the two clock signal. The total power dissipation from the circuit is only 3.88uW which is considerably low. In the field of IC design power dissipation of the circuit is always an important factor. The lower the power dissipation the longer the service time of the battery powered electronics circuit

  2. A 90nm, Low Power VCO with Reduced KVCO and Sub−band Spacing Variation

    OpenAIRE

    Collins, Diarmuid; Keady, Aidan; Szczepkowski, Grzegorz; Farrell, Ronan

    2011-01-01

    In this paper we present the design of a low power VCO with reduced variations in VCO gain (KVCO) and subband spacing resolution (fres). The proposed VCO is designed using a 90nm CMOS process to cover a tuning range of 23%. Variations in KVCO and fres are reduced by factors of 6 and 17 respectively over a conventional sub-banded VCO, designed using the same process, to meet the same tuning range. This makes the proposed VCO more suited to stable PLL operation with its ...

  3. Design and Simulation of Low Noise Amplifiers at 180nm and 90nm Technologies

    Directory of Open Access Journals (Sweden)

    Fathima Janisha

    2016-11-01

    Full Text Available With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs in the radio frequency (RF regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.

  4. Accurate geometry scalable complementary metal oxide semiconductor modelling of low-power 90 nm amplifier circuits

    Directory of Open Access Journals (Sweden)

    Apratim Roy

    2014-05-01

    Full Text Available This paper proposes a technique to accurately estimate radio frequency behaviour of low-power 90 nm amplifier circuits with geometry scalable discrete complementary metal oxide semiconductor (CMOS modelling. Rather than characterising individual elements, the scheme is able to predict gain, noise and reflection loss of low-noise amplifier (LNA architectures made with bias, active and passive components. It reduces number of model parameters by formulating dependent functions in symmetric distributed modelling and shows that simple fitting factors can account for extraneous (interconnect effects in LNA structure. Equivalent-circuit model equations based on physical structure and describing layout parasites are developed for major amplifier elements like metal–insulator–metal (MIM capacitor, spiral symmetric inductor, polysilicon (PS resistor and bulk RF transistor. The models are geometry scalable with respect to feature dimensions, i.e. MIM/PS width and length, outer-dimension/turns of planar inductor and channel-width/fingers of active device. Results obtained with the CMOS models are compared against measured literature data for two 1.2 V amplifier circuits where prediction accuracy for RF parameters (S(21, noise figure, S(11, S(22 lies within the range of 92–99%.

  5. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology

    OpenAIRE

    Hassan Raza Naqvi, Syed

    2007-01-01

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high pe...

  6. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    Science.gov (United States)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  7. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

    Science.gov (United States)

    Mingyuan, Yu; Ting, Li; Jiaqi, Yang; Shuangshuang, Zhang; Fujiang, Lin; Lin, He

    2016-07-01

    This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

  8. 324GHz CMOS VCO Using Linear Superimposition Technique

    Science.gov (United States)

    Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

    2007-01-01

    Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

  9. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    Science.gov (United States)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  10. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS

    Science.gov (United States)

    Jun, Ma; Yawei, Guo; Yue, Wu; Xu, Cheng; Xiaoyang, Zeng

    2013-08-01

    This paper presents a 10-bit 80-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip (SoC). By using the top-plate-sample switching scheme and a split capacitive array structure, the total capacitance is dramatically reduced which leads to low power and high speed. Since the split structure makes the capacitive array highly sensitive to parasitic capacitance, a three-row layout method is applied to the layout design. To overcome the charge leakage in the nanometer process, a special input stage is proposed in the comparator. As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock, and a tunable clock generator is implemented. The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP (general purpose) CMOS technology. Measurement results show a peak signal-to-noise and distortion ratio (SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit (FOM) of 94.8 fJ/conversion-step.

  11. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS

    Institute of Scientific and Technical Information of China (English)

    Ma Jun; Guo Yawei; Wu Yue; Cheng Xu; Zeng Xiaoyang

    2013-01-01

    This paper presents a 10-bit 80-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip (SoC).By using the top-plate-sample switching scheme and a split capacitive array structure,the total capacitance is dramatically reduced which leads to low power and high speed.Since the split structure makes the capacitive array highly sensitive to parasitic capacitance,a three-row layout method is applied to the layout design.To overcome the charge leakage in the nanometer process,a special input stage is proposed in the comparator.As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock,and a tunable clock generator is implemented.The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP (general purpose) CMOS technology.Measurement results show a peak signal-to-noise and distortion ratio (S1NAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit (FOM) of 94.8 fJ/conversion-step.

  12. Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

    Science.gov (United States)

    Cantu, Pietro; Capetti, Gianfranco; Loi, Sara; Lupo, Marco; Pepe, Annalisa; Saitoh, Kenji; Yamazoe, Kenji; Hasegawa, Yasuo; Iwasa, Junji; Toublan, Olivier R.

    2004-05-01

    According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

  13. DOE experiment for scattering bars optimization at the 90nm node

    Science.gov (United States)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  14. A low voltage CMOS low drop-out voltage regulator

    Science.gov (United States)

    Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

    2009-05-01

    A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

  15. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    Science.gov (United States)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  16. A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

    NARCIS (Netherlands)

    Harpe, P.; Zhou, C.; Wang, X.; Dolmans, G.; Groot, H. de

    2010-01-01

    Applications like wireless sensor nodes require ultra low-power receivers with power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power applications

  17. High precision CMOS clock duty-cycle corrector%高精度CMOS时钟占空比纠正器的设计

    Institute of Scientific and Technical Information of China (English)

    孙烨辉; 高静

    2013-01-01

    设计并实现了一种使用90nm CMOS工艺制造的高精度CMOS占空比纠正器.它的核心电路工作电压为1V,最高工作频率为10GHz.占空比纠正器负责对高速数字电路中的时钟占空比进行纠正,以减小占空比失真造成的确定性抖动.设计利用差分电荷泵方式完成对时钟占空比信息的提取,然后通过闭环负反馈环路来完成失真纠正工作.仿真结果表明,占空比纠正精度非常高,占空比剩余误差在1%以内.%A CMOS clock duty-cycle correction circuit with high precision is described.The circuit is implemented in 90nm CMOS process and power supply voltage is 1V.The maximum frequency is 10GHz.The duty-cycle corrector is used to correct the duty-cycle of the clock to reduce the deterministic jitter introduced by the duty-cycle distortion.The circuits extract the duty-cycle information by differential charge pump and correct the clock distortion by a negative feedback loop.The simulation result shows that the residual error of the duty-cycle distortion is within 1%.

  18. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  19. Nano CMOS

    OpenAIRE

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  20. Analytical design of a 0.5V 5GHz CMOS LC-VCO

    OpenAIRE

    Yamashita, Fumiaki; Matsuoka, Toshimasa; Kihara, Takao; Takobe, Isao; Park, Hae-Ju; Taniguchi, Kenji

    2009-01-01

    A low-voltage complementary cross-coupled differential LC-VCO was investigated using simple modeling. The bias-controllability of the VCO provides a simple design for low-voltage operation. An analytical design approach realized a 5GHz VCO under a 0.5V supply voltage using a 90-nm digital CMOS process.

  1. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique...

  2. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  3. Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

    Institute of Scientific and Technical Information of China (English)

    HU Shi-Gang; HAO Yue; MA Xiao-Hua; CAO Yan-Rong; CHEN Chi; WU Xiao-Feng

    2009-01-01

    Hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub,max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses, ttowever, the damage generated during the LGVS shows different characteristics from that during Isub,max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.

  4. CMOS Direct-Injection Divide-by-3 Injection-Locked Frequency Dividers

    Institute of Scientific and Technical Information of China (English)

    Chia-Wei; Chang; Jhin-Fang; Huang; Sheng-Lyang; Jang; Ying-Hsiang; Liao; Miin-Horng; Juang

    2010-01-01

    <正>This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.

  5. A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Pushpa Saini

    2012-10-01

    Full Text Available Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In this paper, a technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature.

  6. Design of Current steering DAC using 250nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Vineet Tiwari

    2012-06-01

    applied at the reference terminal. Analog to digital converter performs the reverse operation. It has many era of operations in audio and Video form and whiffletree electromagnetic device uses DAC linkage in typewriter. It describes the 3.3 volt, 65 MHz 8 bit CMOS digital to analog converter, includes two stage current cell matrix. This paper describes a 1v CMOS 8 bit DAC with two stage current cell matrix architecture which consists of 4 MSB and 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the no of high swing current mirrors. The designed DAC with a by 90 nm nwell CMOS standard process. The experiment is based on settling time, Integrity, or non linearity. The designed DAC is fully operational for power supply down to 1 volt such that DAC is suitable for low voltage and low power applications.

  7. Reliability engineering in RF CMOS

    OpenAIRE

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies.

  8. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  9. Main: 1V08 [RPSD[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V08 トウモロコシ Corn Zea mays L. Beta-Glucosidase, Chloroplast Precursor Name=Glu1; Zea...EGLKDLLMIMKNKYGNPPIYITENGIGDVDTKETPLPMEAALNDYKRLDYIQRHIATLKESIDLGSNVQGYFAWSLLDNFEWFAGFTERYGIVYVDRNNNCTRYMKESAKWLKEFNTAKKPSKKILTPA corn_1V08.jpg ...

  10. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  11. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  12. A CMOS frequency generation module for 60-GHz applications

    Institute of Scientific and Technical Information of China (English)

    Zhou Chunyuan; Zhang Lei; Wang Hongrui; Qian He

    2012-01-01

    A frequency generation module for 60-GHz transceivers and phased array systems is presented in this paper.It is composed of a divide-by-2 current mode logic divider (CM L) and a doubler in push-push configuration.Benefiting from the CML structure and push-push configuration,the proposed frequency generation module has a wide operating frequency range to cover process,voltage,and temperature variation.It is implemented in a 90-nm CMOS process,and occupies a chip area of 0.64 × 0.65 mm2 including pads.The measurement results show that the designed frequency generation module functions properly with input frequency over 15 GHz to 25 GHz.The whole chip dissipates 12.1 mW from a 1.2-V supply excluding the output buffers.

  13. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  14. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  15. A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

    Institute of Scientific and Technical Information of China (English)

    Yang Jinda; Wang Xianbiao; Li Li; Cheng Xu; Guo Yawei; Zeng Xiaoyang

    2011-01-01

    A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13 μm CMOS technology.The contrast experimental resuits verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.

  16. Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.

    Science.gov (United States)

    Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanović, Vladimir; Popović, Miloš A

    2013-08-01

    We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects.

  17. High-Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

    CERN Document Server

    Mak, Pui-In

    2012-01-01

    This book presents high-/mixed-voltage analog and radio frequency (RF) circuit techniques for developing low-cost multistandard wireless receivers in nm-length CMOS processes.  Key benefits of high-/mixed-voltage RF and analog CMOS circuits are explained, state-of-the-art examples are studied, and circuit solutions before and after voltage-conscious design are compared. Three real design examples are included, which demonstrate the feasibility of high-/mixed-voltage circuit techniques.    Provides a valuable summary and real case studies of the state-of-the-art in high-/mixed-voltage circuits and systems; Includes novel high-/mixed-voltage analog and RF circuit techniques – from concept to practice; Describes the first high-voltage-enabled mobile-TVRF front-end in 90nm CMOS and the first mixed-voltage full-band mobile-TV Receiver in 65nm CMOS; Demonstrates the feasibility of high-/mixed-voltage circuit techniques with real design examples.  

  18. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-06-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range, analog and mixed integrated circuit (IC design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layout simulation results.

  19. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  20. Building strong partnerships with CMOs.

    Science.gov (United States)

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings.

  1. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  2. 增强90nm以下节点应用的工艺控制适应性%Enhancing Process Control Flexibility for Sub-90 nm Applications

    Institute of Scientific and Technical Information of China (English)

    John Yamartino; Vivien Chang; James Holland; Andrey Poliektov

    2007-01-01

    器件尺寸正在对半导体加工工艺从多方面提出新的挑战.对于在90nm节点之后的应用,需要更大改进,且用适应性强的先进工艺来克服更大节点工艺中已得到验证的固有技术的限制.不仅基于先进工艺控制(APC)的下一代工艺设备能够得到来自一个以上信息来源的测量数据,而且将这些测量数据转换成为工艺控制参数以减少性能变化,下一代工艺设备必须提供生产线许多表明圆片经过工艺设备的整个控制程序特性.这种先进工艺控制系统将给予生产线高度理想的、适合先进工艺控制的适应能力需求,实现对其独特的生产线提供最大的优势.%Device scaling is posing new challenges for many aspects of semiconductor processing. More sophisticated and flexible advanced process controls (APC) are needed for sub-90-nm applications to overcome limitations inherent in techniques that have proven effective for larger nodes. Not only must next-generation process-tool-based APC systems be able to receive metrology data from more than one source and translate them into process-control parameters to reduce performance variations, they must provide the fab host with features for designating the entire process control sequence for wafers passing through the system. Such APC systems will give fabs the highly desirable versatility needed for tailoring APC implementation to best advantage for its particular production lines.

  3. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-07-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layoutsimulation results.

  4. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  5. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  6. CMOS Nonlinear Signal Processing Circuits

    OpenAIRE

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  7. CMOS array design automation techniques

    Science.gov (United States)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  8. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  9. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  10. CMOS bulk-metal design handbook

    Science.gov (United States)

    Edge, T. M.

    1978-01-01

    User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

  11. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  12. A CMOS floating point multiplier

    Science.gov (United States)

    Uya, M.; Kaneko, K.; Yasui, J.

    1984-10-01

    This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

  13. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  14. Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

    OpenAIRE

    Yoshikawa, Nobuyuki; Tomida, T.; Tokuda, A.; Liu, Q.; Meng, X.(Institute of High Energy Physics, Beijing, China); Whiteley, SR.; VanDuzer, T.

    2005-01-01

    Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 mu m, 0.25 mu m, and 0.35 mu m commercial CMOS processes. Their static IN characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured...

  15. A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

    Directory of Open Access Journals (Sweden)

    A. Oncu

    2015-04-01

    Full Text Available A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF. The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW.

  16. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    Energy Technology Data Exchange (ETDEWEB)

    Gómez-Galán, J.A., E-mail: jgalan@uhu.es [Dpto de Ingeniería Electrónica, Sist. Informáticos y Automática, Universidad de Huelva (Spain); Sánchez-Rodríguez, T.; Sánchez-Raya, M.; Martel, I. [Dpto de Ingeniería Electrónica, Sist. Informáticos y Automática, Universidad de Huelva (Spain); López-Martín, A. [Dpto de Ingeniería Eléctrica y Electrónica, Universidad Pública de Navarra (Spain); Carvajal, R.G. [Dpto de Ingeniería Electrónica, Universidad de Sevilla (Spain); Ramírez-Angulo, J. [Klipsch School of Electrical Engineering, New Mexico State University (United States)

    2014-06-01

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.

  17. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  18. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  19. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence, the proc......This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence....... The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  20. Portable design rules for bulk CMOS

    Science.gov (United States)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  1. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  2. CMOS Law-jitter Clock Driver Design

    OpenAIRE

    2012-01-01

    [ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. [CASTELLÀ] Diseño de un circuito integrado "clock driver" de bajo jitter y bajo ruido de fase en tecnología CMOS 40 nm. El trabajo se contextualiza en el campo del diseño de circuitos integrados analógicos en tecnologías CMOS nanométricas. [CATALÀ] Disseny d'un circuit "clock driver" de baix jitter i bai...

  3. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  4. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  5. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  6. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  7. Design Of High Performance CMOS Dynamic Latch Comparator

    Directory of Open Access Journals (Sweden)

    G.Saroja

    2016-10-01

    Full Text Available High performance analog to digital converters (ADC, memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two factors they are speed and power consumption. The latch based comparator has two different stages encompassing of a dynamic differential input gain stage and an output latch.The output node in the differential gain stage of proposed comparator requires lesser time to regain higher charge potential. The proposed comparator hasbeen designed and simulated using 130nm CMOS 1P2M technology by using mentor graphics tools with a supply voltage of 1V. Proposed dynamic latch comparator iscompared with existing conventional dynamic latch comparator and with other comparators and the results are discussed in detail.

  8. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  9. Josephson-CMOS Hybrid Memories

    Science.gov (United States)

    2007-04-25

    capacitance. For an on-chip wire which is made of copper/aluminum alloy , the resistance is in the order of 100 mΩ per square and the capacitance is about 0.2...the thickness of the barrier. In a typical Nb process, the barrier is an approximately 1-nm-thick alu - minum oxide made by thermal oxidation of the...minimize the interconnection degradation , the CMOS circuits must be cooled to the temperature at which the superconducting circuits can work well, which

  10. Nanosecond monolithic CMOS readout cell

    Science.gov (United States)

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  11. A 1-V 15 μW High-Accuracy Temperature Switch

    NARCIS (Netherlands)

    Schinkel, D.; Boer, de R.P.; Annema, A.J.; Tuijl, van A.J.M.

    2004-01-01

    A CMOS temperature switch with uncalibrated high accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 m CMOS process. The temperature switch has an in-designed hy

  12. A 1-V 15µW high-precision temperature switch

    NARCIS (Netherlands)

    Schinkel, D.; Boer, de R.P.; Annema, A.J.; Tuijl, van A.J.M.

    2001-01-01

    A CMOS temperature switch with uncalibrated high temperature accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 µm CMOS process. The temperature switch has a in

  13. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  14. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  15. Integrated RF MEMS/CMOS Devices

    CERN Document Server

    Mansour, R R; Bakeri-Kassem, M

    2008-01-01

    A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

  16. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  17. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  18. Spectrometry with consumer-quality CMOS cameras.

    Science.gov (United States)

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  19. Carbon Nanotube Integration with a CMOS Process

    OpenAIRE

    Perez, Maximiliano S.; Betiana Lerner; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Pedro M. Julian; Pablo S. Mandolesi; Fabian A. Buffa; Alfredo Boselli; Alberto Lamagna

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new rout...

  20. Carbon nanotube integration with a CMOS process.

    Science.gov (United States)

    Perez, Maximiliano S; Lerner, Betiana; Resasco, Daniel E; Pareja Obregon, Pablo D; Julian, Pedro M; Mandolesi, Pablo S; Buffa, Fabian A; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  1. Carbon Nanotube Integration with a CMOS Process

    Directory of Open Access Journals (Sweden)

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  2. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  3. Analog CMOS contrastive Hebbian networks

    Science.gov (United States)

    Schneider, Christian; Card, Howard

    1992-09-01

    CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

  4. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  5. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  6. Main: 1V3I [RPSD[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V3I 大豆 Soybean Glycine max (L.) Merrill Beta-Amylase Name=Bmy1; Glycine Max Molecule: Beta-Amylase; Chain...: A; Synonym: 1,4-Alpha-D-Glucan Maltohydrolase; Engineered: Yes; Mutation: Yes Hydro

  7. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths.......A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss

  8. A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

    Institute of Scientific and Technical Information of China (English)

    Li Yuanwen; Qi Da; Dong Yifeng; Xu Jun; Ren Junyan

    2009-01-01

    A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.

  9. A 1-V 60-{mu}W 85-dB dynamic range continuous-time third-order sigma-delta modulator

    Energy Technology Data Exchange (ETDEWEB)

    Li Yuanwen; Qi Da; Dong Yifeng; Xu Jun; Ren Junyan, E-mail: 072021068@fudan.edu.c [State Key Laboratory of ASIC and System, Shanghai 201203 (China)

    2009-12-15

    A 1-V third order one-bit continuous-time (CT) EA modulator is presented. Designed in the SMIC mixed-signal 0.13-{mu}m CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT {Sigma}{Delta} modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 {mu}W from a 1-V power supply and the prototype occupies an active area of 0.12 mm{sup 2}. (semiconductor integrated circuits)

  10. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS

    OpenAIRE

    Payami, Sima

    2012-01-01

    In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The open-loop DC-gain of the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz. Phase-Margin (PM) of the ...

  11. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  12. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  13. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  14. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    OpenAIRE

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal a...

  15. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  16. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  17. CMOS-compatible LVOF-based visible microspectrometer

    NARCIS (Netherlands)

    Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabricati

  18. Noise in sub-micron CMOS image sensors

    NARCIS (Netherlands)

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  19. An RF (R) MS Power Detector in Standard CMOS

    NARCIS (Netherlands)

    Aa, van der F.H.J.

    2006-01-01

    This Master thesis describes the research towards the integration of RF power detectors for 3G cellular phones and base stations in CMOS technology1. It is a feasibility study with the emphasis on the identification of fundamental limitations of CMOS (particularly CMOS9) and of a number of squaring

  20. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  1. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  2. Scaling CMOS devices through alternative structures

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  3. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  4. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  5. Evaluation of a scientific CMOS camera for astronomical observations

    Institute of Scientific and Technical Information of China (English)

    Peng Qiu; Yong-Na Mao; Xiao-Meng Lu; E Xiang; Xiao-Jun Jiang

    2013-01-01

    We evaluate the performance of the first generation scientific CMOS (sCMOS) camera used for astronomical observations.The sCMOS camera was attached to a 25 cm telescope at Xinglong Observatory,in order to estimate its photometric capabilities.We further compared the capabilities of the sCMOS camera with that of full-frame and electron multiplying CCD cameras in laboratory tests and observations.The results indicate the sCMOS camera is capable of performing photometry of bright sources,especially when high spatial resolution or temporal resolution is desired.

  6. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  7. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  8. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  9. Fully CMOS-compatible titanium nitride nanoantennas

    Science.gov (United States)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  10. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  11. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transisto

  12. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  13. CMOS VHF transconductance-C lowpass filter

    NARCIS (Netherlands)

    Nauta, B.

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  14. Linear CMOS transconductance element for VHF filters

    NARCIS (Netherlands)

    Nauta, B.; Seevinck, E.

    1989-01-01

    A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, Vipp=1.8 V), nondominant poles in the gigaher

  15. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  16. A CMOS current-mode operational amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1993-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2...

  17. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, E.A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    2001-01-01

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important transmissi

  18. A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    Zhitang Song; YiPeng Zhan; Daolin Cai; Bo Liu; Yifeng Chen; Jiadong Ren

    2015-01-01

    In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

  19. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  20. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  1. A 1-V 15µW high-precision temperature switch

    OpenAIRE

    Schinkel, D.; De Boer, MR; Annema, A.J.; Tuijl, van, B.A.J.

    2001-01-01

    A CMOS temperature switch with uncalibrated high temperature accuracy is presented. The circuit is based on the classical CMOS bandgap reference structure, using parasitic PNPs and a PTAT multiplier. The circuit was designed in a standard digital 0.18 µm CMOS process. The temperature switch has a in-designed hysteresis of 1.2° C around a threshold value of 128° C. At the switching-threshold all matched transistors have also matched operating conditions, yielding a temperature threshold that i...

  2. Graphene/Si CMOS hybrid hall integrated circuits.

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  3. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  4. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  5. Spatio-temporal simulation in subthreshold CMOS

    Science.gov (United States)

    Neeley, John; Harris, John G.

    1997-05-01

    This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua's circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit's dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.

  6. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  7. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  8. CMOS compatible nanoscale nonvolatile resistance switching memory.

    Science.gov (United States)

    Jo, Sung Hyun; Lu, Wei

    2008-02-01

    We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

  9. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  10. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  11. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  12. CMOS Camera Array With Onboard Memory

    Science.gov (United States)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  13. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  14. CMOS Design of Ternary Arithmetic Devices

    Institute of Scientific and Technical Information of China (English)

    吴训威; F.Prosser

    1991-01-01

    This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.

  15. CMOS-array design-automation techniques

    Science.gov (United States)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  16. Cantilever-Based Biosensors in CMOS Technology

    CERN Document Server

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  17. CMOS current amplifiers : speed versus nonlinearity

    OpenAIRE

    2000-01-01

    This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived tha...

  18. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  19. Efficient design of CMOS TSC checkers

    Science.gov (United States)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  20. A logarithmic low dark current CMOS pixel

    Science.gov (United States)

    Brunetti, Alessandro Michel; Choubey, Bhaskar

    2016-04-01

    High dynamic range pixels are required in a number of automotive and scientific applications. CMOS pixels provide different approaches to achieve this. However, these suffer from poor performance under low light conditions due to inherently high leakage current that is present in CMOS processes, also known as dark current. The typical approach to reduce this dark current involves process modifications. Nevertheless, energy considerations suggest that the leakage current will be close to zero at a close to zero voltage on the photodiode. Hence, the reduction in dark current can be achieved by forcing a zero voltage across the photodiode. In this paper, a novel logarithmic CMOS pixel design capable of reducing dark current without any process modifications is proposed. This pixel is also able to produce a wide dynamic range response. This circuit utilizes two current mirrors to force the in-pixel photodiode at a close to zero voltage. Additionally, a bias voltage is used to reduce a higher order effect known as Drain Induced Barrier Lowering (DIBL). In fact, the contribution of this effect can be compensated by increasing the body effect. In this paper, we studied the consequences of a negative bias voltage applied to the body of the current mirror pair to compensate for the DIBL effect thereby achieving a very small voltage drop on the photodiode and consequently, a higher sensitivity in low light conditions.

  1. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    Science.gov (United States)

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  2. Optical design of microlens array for CMOS image sensors

    Science.gov (United States)

    Zhang, Rongzhu; Lai, Liping

    2016-10-01

    The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

  3. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  4. Data of evolutionary structure change: 1C3AB-1V4LC [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available uence>AWSGG--SDCIV > --EEEEEe> AT...>1V4L C 1V4LC NLYKQSSKKCYA ...> GGG EEE> ATOM 2895 CA ASN C 95 14.946 47.67...ence>SKTTD--NQWLS >E -- EEEEe> AT...dbChain>C 1V4LC LKKGTELRTWFN ture>EE EEEE

  5. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  6. A New Low-Power CMOS Quadrature VCO with Current Reused Structure

    Directory of Open Access Journals (Sweden)

    C. Wang

    2011-04-01

    Full Text Available A new quadrature voltage controlled oscillator (QVCO circuit topology is proposed for low-voltage and low-power applications. In the proposed circuit, two oscillators with current-reused structure are coupled to each other by two P&N-MOS pairs. In this way, low phase noise quadrature signals are generated with low-voltage and low-power. The simulation is made by Cadence in chartered 0.18 μm CMOS process. The simulation result shows that the QVCO phase noise is approximately - 117.1 dBc/Hz at 1MHz offset from 1.8 GHz operation frequency. The QVCO dissipates 1.92 mW with a 1.1 V supply voltage.

  7. 0.18μm CMOS Low Voltage Power Amplifier For WSN Application

    Directory of Open Access Journals (Sweden)

    Wu Chenjian

    2013-08-01

    Full Text Available This paper presents the design of a Class A/B power amplifier (PA for 2.4-2.4835GHz Wireless Sensor Network (WSN system in 0.18μm CMOS technology. The PA adopts the single-stage differential structure and the output power of the PA can be controlled by switching the sizes of transistors. Seven different level of output power can be obtained through a three- bit control code. The tested results shows that the proposed PA achieves power added efficiency (PAE of 26.73% while delivering an output power of 6.35dBm at 1dB compression point. Its power gain is 15.87dB. With a low DC voltage supply of 1V, its power consumption is 15.3mW. The PA die size is 1070×610μm2.

  8. A 94 GHz CMOS based oscillator transmitter with an on-chip meandered dipole antenna

    KAUST Repository

    Cheema, Hammad M.

    2015-10-26

    A miniaturized 94 GHz oscillator transmitter in 65nm CMOS is presented. An extremely small silicon foot-print of 0.25mm2 is achieved through meandering of the top-metal dipole antenna, conjugate matching between the oscillator and the antenna without impedance matching elements and efficient placement of the oscillator circuit within the antenna. The antenna demonstrates bandwidth of 90 to 99 GHz (10%) and a gain of -6dBi. The use of parasitic aware antenna-circuit code-sign strategy results in an accurate measured oscillation frequency of 94.1 GHz. The oscillator exhibits a measured output power of -25 dBm, phase noise of -88 dBc/Hz at 1 MHz offset and consumes 8.4mW from a 1V supply. © 2015 IEEE.

  9. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-03-06

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  10. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Science.gov (United States)

    Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

    2016-01-01

    An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

  11. Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer.

    Science.gov (United States)

    Xu, Wenya; Dou, Junyan; Zhao, Jianwen; Tan, Hongwei; Ye, Jun; Tange, Masayoshi; Gao, Wei; Xu, Weiwei; Zhang, Xiang; Guo, Wenrui; Ma, Changqi; Okazaki, Toshiya; Zhang, Kai; Cui, Zheng

    2016-02-28

    Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (±2 V) and subthreshold swing (SS) (122-161 mV dec(-1)), high effective mobility (up to 17.6-37.7 cm(2) V(-1) s(-1)) and high on/off ratio (10(4)-10(7)). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption.

  12. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.;

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process...

  13. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    Science.gov (United States)

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  14. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  15. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  16. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  17. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  18. Method and circuitry for CMOS transconductor linearization

    OpenAIRE

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a sec...

  19. Silicon Light Emitting Devices in CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    CHEN Hong-Da; LIU Hai-Jun; LIU Jin-Bin; GU Ming; HUANG Bei-Ju

    2007-01-01

    @@ Two silicon light emitting devices with different structures are realized in standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/cm2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm.

  20. Analysis of bipolar and CMOS amplifiers

    CERN Document Server

    Sodagar, Amir M

    2007-01-01

    The classical approach to analog circuit analysis is a daunting prospect to many students, requiring tedious enumeration of contributing factors and lengthy calculations. Most textbooks apply this cumbersome approach to small-signal amplifiers, which becomes even more difficult as the number of components increases. Analysis of Bipolar and CMOS Amplifiers offers students an alternative that enables quick and intuitive analysis and design: the analysis-by-inspection method.This practical and student-friendly text demonstrates how to achieve approximate results that fall within an acceptable ran

  1. Vertical Isolation for Photodiodes in CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  2. An Approach for Low Power CMOS Design

    Directory of Open Access Journals (Sweden)

    Ravindra kumar chejara

    2015-03-01

    Full Text Available Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay. In this paper, variable supply-voltage scheme (dual-VS scheme for dual power supplies along with voltage level converter is presented. Also paper presents an overall comparative analysis among various methods to achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the best methods for same at this technology.

  3. RF Circuit Design in Nanometer CMOS

    OpenAIRE

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer C...

  4. CMOS Current-mode Operational Amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1992-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-range ±700¿A) and a (theoretically) unlimited slew-rate. The amplifier is realized in a standard CMOS 2......A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...

  5. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  6. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  7. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  8. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  9. Design of high speed camera based on CMOS technology

    Science.gov (United States)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  10. Theoretical performance analysis for CMOS based high resolution detectors.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-06

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

  11. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  12. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  13. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  14. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  15. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  16. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  17. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  18. Design of Low Voltage Low Power CMOS OP-AMP

    OpenAIRE

    2014-01-01

    Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipa...

  19. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    Science.gov (United States)

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-05

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation.

  20. High-speed multicolor photometry with CMOS cameras

    CERN Document Server

    Pokhvala, S M; Reshetnyk, V M

    2012-01-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11" on Peak Terskol. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR color system of CMOS sensors is close to the Johnson BVR system. The results of testing show that we can measure the stars up to V $\\simeq$ 14 with the precision of 0.01 mag. Stars up to magnitude V $\\sim$ 10 can shoot at 24 frames per second in the video mode.

  1. A monolithically integrated torsional CMOS-MEMS relay

    Science.gov (United States)

    Riverola, M.; Sobreviela, G.; Torres, F.; Uranga, A.; Barniol, N.

    2016-11-01

    We report experimental demonstrations of a torsional microelectromechanical (MEM) relay fabricated using the CMOS-MEMS approach (or intra-CMOS) which exploits the full foundry inherent characteristics enabling drastic reduction of the fabrication costs and batch production. In particular, the relay is monolithically integrated in the back end of line of a commercial standard CMOS technology (AMS 0.35 μm) and released by means of a simple one-step mask-less wet etching. The fabricated torsional relay exhibits an extremely steep switching behaviour symmetrical about both contact sides with an on-state contact resistance in the k Ω -range throughout the on-off cycling test.

  2. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  3. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  4. IMEC pushes the limits of CMOS

    Directory of Open Access Journals (Sweden)

    George Marsh

    2002-06-01

    Visionary stuff, but although the day of the cyborg may still be some way off, IMEC (Inter-University MicroElectronics Centre — Europe’s leading independent microelectronics research organization — sees its role as expediting some aspects of this future. This means, inter alia, a dedication to maintaining the currency of Moore’s Law, in the belief that this can continue for several years yet before fundamental limits impose insurmountable barriers. Success will require further extension of the boundaries of complementary metal oxide silicon (CMOS, that backbone of mainstream electronic technology. Materials, both the manipulation of existing and development of new, are germane to this, as Materials Today discovered on a recent visit.

  5. CMOS imager for pointing and tracking applications

    Science.gov (United States)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  6. CMOS digital pixel sensors: technology and applications

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  7. Data of evolutionary structure change: 1CEMA-1V5CA [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available 1CEMA-1V5CA 1CEM 1V5C A A ----AGVPFNTKYPYGPTSIADNQSEVTAMLKAEWEDWK...confEVID> 0 1CEM A 1CEMA...CEM A 1CEMA VCFNE-----QALFD A 1CEMA VPDWC-TASGT A 1CEMA MTGYD-LNFAK

  8. Data of evolutionary structure change: 1MRVA-1V0BA [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available 1MRVA-1V0BA 1MRV 1V0B A A VTMNDFDYLKLLGKGTFGKVILVREKATGRYYAMKILR-...confEVID> 0 1MRV A 1MRVA...entryChain> 1MRV A 1MRVA PEVLE-DN...dbChain>A 1MRVA IRFPR-----TLSPE A 1MRVA LVREKATGRYY

  9. Data of evolutionary structure change: 1V38A-2COTA [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V38A-2COTA 1V38 2COT A A --GSSGSSGRRENHQTIQEFLERIHL--QEYTSTLLLNG...ine>SER CA 486 2COT A 2COTA...4> -5.748000144958496 4.816999912261963 -7.743000030517578 ...9999704360962 0.7080000042915344 0.017000000923871994 tion> 4.228970050811768 7.614790916442871 ...

  10. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  11. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  12. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  13. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

    2016-01-01

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

  14. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    Institute of Scientific and Technical Information of China (English)

    ZHANG Guo-An; ZHANG Dong-Wei; HE Jin; SU Yan-Mei; WANG Cheng; CHEN Qin; LIANG Hai-Lang; YE Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1T CMOS APS) architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus,the reset and selected transistors can be removed. In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

  15. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  16. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

    Institute of Scientific and Technical Information of China (English)

    Hossein AGHABABA; Behjat FOROUZANDEH; Ali AFZALI-KUSHA

    2012-01-01

    We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations.The key parameters in determining the leakage and delay are OFF and ON currents,respectively,which are both affected by the variation of the threshold voltage.Additionally,the current is a strong function of mobility.The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations,which may be induced by any source.Using this model,in the plane of threshold voltage and mobility,we determine regions for different combinations of performance (speed) and leakage.Based on these regions,we discuss the trade-offbetween leakage and delay where the leakage-delay-product is the optimization objective.To assess the accuracy of the proposed model,we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-,65-,and 90-nm technologies.

  17. Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

    Science.gov (United States)

    2013-04-01

    Red, Green, Blue, Yellow, Magenta, Cyan) averaged CIE Delta-E 2000 = 16.6-19.3 after a white balance and color matrix correction is applied to the...insertion loss and also metal-insulator-metal waveguides; iii) developed a full format CMOS image sensor with plasmonic color filters; iv) explored... color filters and demonstration of imaging. v. Design of a plasMOStor plasmonic switching device, with low insertion loss, implemented in CMOS Si

  18. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    D Contarato; J-M Bussat; P Denes; L Griender; T Kim; T Stezeberger; H Weiman; M Battaglia; B Hooberman; L Tompkins

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  19. Delta Doping High Purity CCDs and CMOS for LSST

    Science.gov (United States)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  20. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...... poor performance compared to the bipolar designs, but CMOS has a potential for CFB op-amp design if more ingenious circuit configurations are applied...

  1. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  2. Design of 2.1 GHz CMOS Low Noise Amplifier

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

  3. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  4. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  5. Integration of III-V materials and Si-CMOS through double layer transfer process

    Science.gov (United States)

    Lee, Kwang Hong; Bao, Shuyu; Fitzgerald, Eugene; Tan, Chuan Seng

    2015-03-01

    A method to integrate III-V compound semiconductor and SOI-CMOS on a common Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III-V/Si hybrid structure on a common substrate. Through this method, high temperature III-V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damage to the CMOS layer is avoided.

  6. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  7. On noise in time-delay integration CMOS image sensors

    Science.gov (United States)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  8. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

  9. Data of evolutionary structure change: 1V37A-2YW3C [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V37A-2YW3C 1V37 2YW3 A C --------MELWLVRH--------GETLWNREGRLLGWT...41 ALA CA 498 2YW3 C 2YW3C...CA 453 2YW3 C 2YW3C.../pdbChain> 2YW3C LEITL-RTEKG EEE - HH...VID> 3 2YW3 C 2YW3C

  10. Low Power CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Sujata Pandey,

    2010-08-01

    Full Text Available Here, two new designs of CMOS digitally controlled oscillators (DCO for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and withtwo NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 - 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 - 700.2977] μW and [617.6616 -6 77.3996] μW respectively.

  11. A CMOS readout circuit for microstrip detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  12. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  13. NSC 800, 8-bit CMOS microprocessor

    Science.gov (United States)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  14. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  15. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  16. CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria.

    Science.gov (United States)

    Lei Yao; Lamarche, P; Tawil, N; Khan, R; Aliakbar, A M; Hassan, M H; Chodavarapu, V P; Mandeville, R

    2011-06-01

    We present the design and implementation of a prototype complementary metal-oxide semiconductor (CMOS) conductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The detection of E. coli is done by employing T4 bacteriophages as receptor organisms. The conductometric system operates by measuring the resistance of the test sample between the electrodes of a two-electrode electrochemical system (reference electrode and working electrode). The CMOS IC is fabricated in a TSMC 0.35-μm process and uses a current-to-frequency (I to F) conversion circuit to convert the test sample resistance into a digital output modulated in frequency. Pulsewidth control (one-shot circuit) is implemented on-chip to control the pulsewidth of the output digital signal. The novelty in the current work lies in the ability of the CMOS sensor system to monitor very low initial concentrations of bacteria (4×10(2) to 4×10(4) colony forming unit (CFU)/mL). The CMOS system is also used to record the interaction between E. coli and its specific receptor T4 bacteriophage. The prototype CMOS IC consumes an average power of 1.85 mW with a 3.3-V dc power supply.

  17. CMOS cell sensors for point-of-care diagnostics.

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  18. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  19. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  20. CMOS Cell Sensors for Point-of-Care Diagnostics

    Directory of Open Access Journals (Sweden)

    Haluk Kulah

    2012-07-01

    Full Text Available The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS. CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  1. Figures of merit for CMOS SPADs and arrays

    Science.gov (United States)

    Bronzi, D.; Villa, F.; Bellisai, S.; Tisa, S.; Ripamonti, G.; Tosi, A.

    2013-05-01

    SPADs (Single Photon Avalanche Diodes) are emerging as most suitable photodetectors for both single-photon counting (Fluorescence Correlation Spectroscopy, Lock-in 3D Ranging) and single-photon timing (Lidar, Fluorescence Lifetime Imaging, Diffuse Optical Imaging) applications. Different complementary metal-oxide semiconductor (CMOS) implementations have been reported in literature. We present some figure of merit able to summarize the typical SPAD performances (i.e. Dark Counting Rate, Photo Detection Efficiency, afterpulsing probability, hold-off time, timing jitter) and to identify a proper metric for SPAD comparison, both as single detectors and also as imaging arrays. The goal is to define a practical framework within which it is possible to rank detectors based on their performances in specific experimental conditions, for either photon-counting or photon-timing applications. Furthermore we review the performances of some CMOS and custom-made SPADs. Results show that CMOS SPADs performances improve as the technology scales down; moreover, miniaturization of SPADs and new solutions adopted to counteract issues related with the SPAD design (electric field uniformity, premature edge breakdown, tunneling effects, defect-rich STI interface) along with advances in standard CMOS processes led to a general improvement in all fabricated photodetectors; therefore, CMOS SPADs can be suitable for very dense and cost-effective many-pixels imagers with high performances.

  2. Hybrid CMOS / Microfluidic Systems for Cell Manipulation with Dielectrophoresis

    Science.gov (United States)

    Hunt, Tom; Issadore, David; Westervelt, Robert M.

    2007-03-01

    A hybrid CMOS/microfluidic chip combines the biocompatibility of microfluidics with the built-in logic, programmability, and sensitivity of CMOS integrated circuits (ICs)^1 We have designed a CMOS IC for moving individual cells using dielectrophoresis (DEP). The IC was built in a commercial foundry and we subsequently fabricated a microfluidic chamber on the top surface. The chip consists of a 1.4 by 2.8mm array of over 32,000 individually addressable 11x11 micron pixels. An RF voltage of 5V at 10MHz can be applied to each pixel with respect to the conductive lid of the microfluidic chamber, producing a localized electric field that can trap a cell. By shifting the location of energized pixels, the array can trap and move cells along programmable paths through the microfluidic chamber. We show the design, fabrication, and testing of the hybrid chip. Bringing together the biocompatibility of microfluidics and the power of CMOS chips, hybrid CMOS / microfluidic systems are an exciting technology for biomedical research. Thanks to NSEC NSF grant PHY-0117795 and the NCI MIT-Harvard CCNE. [1] H Lee, Y Liu, RM Westervelt, D Ham, IEEE JSSC 41, 6, pp. 1471-1480, 2006

  3. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Liu, Wei; Kovalgin, Alexey Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  4. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  5. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  6. CMOS reliability issues for emerging cryogenic Lunar electronics applications

    Science.gov (United States)

    Chen, Tianbing; Zhu, Chendong; Najafizadeh, Laleh; Jun, Bongim; Ahmed, Adnan; Diestelhorst, Ryan; Espinel, Gustavo; Cressler, John D.

    2006-06-01

    We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

  7. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  8. Design of Low Voltage Low Power CMOS OP-AMP

    Directory of Open Access Journals (Sweden)

    Shahid Khan,

    2014-11-01

    Full Text Available Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.

  9. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  10. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri......This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation...... of the electrical parameters of n-channel and p-channel transistors. The magnetron sputtering technique is shown to be compatible with standard CMOS electronics without any restriction of the metal types and annealing requirements....

  11. Design of CMOS logic gates for TID radiation

    Science.gov (United States)

    Attia, John Okyere; Sasabo, Maria L.

    1993-01-01

    The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

  12. Electroplated solenoid-type inductors for CMOS rf CO

    Science.gov (United States)

    Nam, Chul; Choi, Wonseo; Chun, KukJin

    2000-10-01

    A Solenoid-type Inductors have been realized using electroplating technique mainly used for 2 Ghz band CMOS RF VCO applications. The integrated spiral inductor has low Q factor due to substrate loss and skin effects. And it also occupies large area compared to solenoid-type inductor. The direction of flux of the solenoid-type inductor is parallel to the substrate, which can lower substrate loss and other interference with integrated passive components. In this research, Solenoid-type inductors are simulated and modeled as equivalent circuit for CMOS RF VCO based on extracted S- parameters. The electroplated solenoid-type inductors are fabricated on both a standard silicon substrate and glass substrate by thick PR photolithography and copper electroplating. The achieved inductance varies range from 1 nH to 5 nH, and maximum Q factor over 10. The inductors are scheduled to be integrated on CMOS RF VCO with RF MEMS capacitor for future.

  13. CMOS biosensors for in vitro diagnosis - transducing mechanisms and applications.

    Science.gov (United States)

    Lei, Ka-Meng; Mak, Pui-In; Law, Man-Kay; Martins, Rui P

    2016-09-21

    Complementary metal oxide semiconductor (CMOS) technology enables low-cost and large-scale integration of transistors and physical sensing materials on tiny chips (e.g., key functions of biosensors: transducing and signal processing. Recent CMOS biosensors unified different transducing mechanisms (impedance, fluorescence, and nuclear spin) and readout electronics have demonstrated competitive sensitivity for in vitro diagnosis, such as detection of DNA (down to 10 aM), protein (down to 10 fM), or bacteria/cells (single cell). Herein, we detail the recent advances in CMOS biosensors, centering on their key principles, requisites, and applications. Together, these may contribute to the advancement of our healthcare system, which should be decentralized by broadly utilizing point-of-care diagnostic tools.

  14. Silicon pixel detector prototyping in SOI CMOS technology

    Science.gov (United States)

    Dasgupta, Roma; Bugiel, Szymon; Idzik, Marek; Kapusta, Piotr; Kucewicz, Wojciech; Turala, Michal

    2016-12-01

    The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

  15. Operation and biasing for single device equivalent to CMOS

    Science.gov (United States)

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  16. High-speed polysilicon CMOS photodetector for telecom and datacom

    Science.gov (United States)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  17. Separation of the subtypes of type V collagen molecules, [alpha 1(V)]2 alpha 2(V) and alpha 1(V) alpha 2(V) alpha 3(V), by chain composition-dependent affinity for heparin: single alpha 1(V) chain shows intermediate heparin affinity between those of the type V collagen subtypes composed of [alpha 1(V)]2 alpha 2(V) and of alpha 1(V) alpha 2(V) alpha 3(V).

    Science.gov (United States)

    Mizuno, K; Hayashi, T

    1996-11-01

    The heparin affinities of heat-treated type V collagen alpha-chains and the triple-helical molecules were evaluated in terms of the NaCl concentration required for prevention of binding to a heparin-Sepharose column. After heat treatment, alpha 1(V) chain required approximately two-fold higher NaCl concentration to pass through the column than the other two chains, alpha 2(V) and alpha 3(V). Thus, the heparin affinity of alpha 1(V) may be approximately two-fold higher than those of the other alpha (V)-chains. The type V collagen molecules in triple-helical conformation were separated into two fractions at 170 mM NaCl in 20 mM phosphate buffer, pH 7.2, containing 2 M urea; bound and non-bound. The ratio of the three alpha-chains, alpha 1(V): alpha 2(V): alpha 3(V) was 2 : 1 : 0 and 1 : 1 : 1 in the bound and flow-through fractions, respectively, on analysis by SDS-PAGE. The differential affinity of the two fractions could be accounted for by the number of alpha 1(V) chains in the triple-helical molecule, if these fractions contained triple-helical subtypes with the chain compositions of [alpha 1(V)]2 alpha 2(V) and alpha 1(V) alpha 2(V) alpha 3(V), respectively. From the comparison of the NaCl concentration required for prevention of the binding, [alpha 1(V)]2, alpha 2(V) had about two-fold higher affinity than alpha 1(V) alpha 2(V) alpha 3(V), and the separated alpha 1(V) chain showed an intermediate affinity. A possible explanation for difference in heparin affinity among the subtypes of molecules and the separated alpha-chains is that the heparin affinity of type V collagen molecule is governed by the number of alpha 1(V) chains contained in the molecule and that steric restraint in a triple-helical conformation weakens the binding of alpha 1(V) chain to heparin.

  18. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  19. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  20. Design and integration of a high accuracy multichannel analog CMOS peak detect and hold circuit for APD-based PET imaging.

    Science.gov (United States)

    Fang, Xiaochao; Brasse, David; Hu-Guo, Christine; Hu, Yann

    2012-04-01

    This paper presents the design of a high accuracy multichannel peak detect and hold (PDH) circuit. This PDH measures the energy of an event and is one part of a readout chain for avalanche photo diodes (APD)-based positron emission tomography (PET) imaging. The circuit is designed in a 0.35μm CMOS process. The proposed PDH is dedicated to ultra low amplitude, large amplitude range from several tens millivolts to 1.1 V, and fast peaking time (190 ns) semi-Gaussian pulses. The two-phase technique has been used to cancel the major error source of the classical CMOS PDH: offset. A two-gain OTA is applied to minimize the DC error. A peak error less 1% for a small input signal (amplitude is between 40 mV and 300 mV) and a peak error less than 0.2% for a large input signal (amplitude is between 300 mV and 1.1 V) have been obtained from test. The area of a PDH is equal to about 200 μm × 40 μm. In our PDH system, the drop rate is negligible.

  1. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  2. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  3. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  4. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  5. Statistical circuit design for yield improvement in CMOS circuits

    Science.gov (United States)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  6. A Voltage Controlled Oscillator using Ring Structure in CMOS Technology

    Directory of Open Access Journals (Sweden)

    Mrs. Devendra Rani

    2012-06-01

    Full Text Available Voltage-Controlled Ring Oscillators are crucial components in many wireless communication systems. The goal of this project is to design a high speed and lower power consumption, a voltage controlled oscillator (VCO, based on ring oscillators in 250nm CMOS technology, which provides a frequency of 2.4GHz. This CMOS based VCO is used for high speed wireless communication applications. A design of VCO includes delay cell, bias circuitry, and tuning circuitry using Tanner 13.0v software.

  7. Modifications in CMOS Dynamic Logic Style: A Review Paper

    Science.gov (United States)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  8. A 65 nm CMOS LNA for Bolometer Application

    Science.gov (United States)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  9. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  10. CMOS-compatible photonic devices for single-photon generation

    Science.gov (United States)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  11. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  12. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  13. Integrated Circuit of CMOS DC-DC Buck Converter with Differential Active Inductor

    Directory of Open Access Journals (Sweden)

    Kaoutar Elbakkar

    2011-11-01

    Full Text Available In this paper, we propose a new design of DC-DC buck converter (BC, which the spiral inductor is replaced by a differential gyrator with capacitor load (gyrator-C implemented in 0.18um CMOS process. The gyrator-C transforms the capacitor load (which is the parasitic capacitor of MOSFETS to differential active inductor DAI. The low-Q value of DAI at switching frequency of converter (few hundred kHz is boosted by adding a negative impedance converter (NIC. The transistor parameters of DAI and NIC can be properly chosen to achieve the desirable value of equivalent inductance L (few tens H, and the maximum-Q value at the switching frequency, and thus the efficiency of converter is improved. Experimental results show that the converter supplied with an input voltage of 1V, provides an output voltage of 0.74V and output ripple voltage of 10mV at 155 kHz and Q-value is maximum (#8776;4226 at this frequency.

  14. Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology

    CERN Document Server

    Kuczynska, Marika; Bugiel, Szymon; Firlej, Miroslaw; Fiutowski, Tomasz; Idzik, Marek; Michelis, Stefano; Moron, Jakub; Przyborowski, Dominik; Swientek, Krzysztof

    2015-01-01

    A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, w...

  15. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Directory of Open Access Journals (Sweden)

    Haiyun Huang

    2015-10-01

    Full Text Available This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  16. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-01-01

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

  17. Evaluation of alignment marks using ASML ATHENA alignment system in 90nm BEOL process

    CERN Document Server

    Tan Chin Boon; Koh Hui Peng; Koo Chee, Kiong; Siew Yong Kong; Yeo Swee Hock

    2003-01-01

    As the critical dimension (CD) in integrated circuit (IC) device reduces, the total overlay budget needs to be more stringent. Typically, the allowable overlay error is 1/3 of the CD in the IC device. In this case, robustness of alignment mark is critical, as accurate signal is required by the scanner's alignment system to precisely align a layer of pattern to the previous layer. Alignment issue is more severe in back-end process partly due to the influenced of Chemical Mechanical Polishing (CMP), which contribute to the asymmetric or total destruction of the alignment marks. Alignment marks on the wafer can be placed along the scribe-line of the IC pattern. ASML scanner allows such type of wafer alignment using phase grating mark, known as Scribe-line Primary Mark (SPM) which can be fit into a standard 80um scribe-line. In this paper, we have studied the feasibility of introducing Narrow SPM (NSPM) to enable a smaller scribe-line. The width of NSPM has been shrunk down to 70% of the SPM and the length remain...

  18. Study of hot-carrier-induced photon emission from 90 nm Si MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Gurfinkel, M. [School of Electrical Engineering, Tel-Aviv University, Ramat-Aviv 69978 (Israel)]. E-mail: moshegur@post.tau.ac.il; Borenshtein, M. [Freescale Semiconductor Israel Ltd., Herzlia 46725 (Israel); Margulis, A. [Freescale Semiconductor Israel Ltd., Herzlia 46725 (Israel); Sade, S. [Freescale Semiconductor Israel Ltd., Herzlia 46725 (Israel); Fefer, Y. [Freescale Semiconductor Israel Ltd., Herzlia 46725 (Israel); Weizman, Y. [Freescale Semiconductor Israel Ltd., Herzlia 46725 (Israel); Shapira, Yoram [School of Electrical Engineering, Tel-Aviv University, Ramat-Aviv 69978 (Israel)

    2005-07-30

    Measurements of photon emission and substrate current in metal-oxide-semiconductor field effect transistors at various temperatures have been carried out using electrical and NIR microscopy. The results received at room temperature have extended the correlation between the substrate current and the photon emission, which was previously found in the visible, to the NIR range. On the basis of this correlation, an empirical model based on the substrate current was used to describe the static emission intensity dependence on the transistor bias. Temperature resolved measurements show that the correlation between emission intensity and the substrate current appears to be coincidental.

  19. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  20. Performance Comparison of Bipolar Vs CMOS VCO in BiCMOS Technology%基于BiCMOS工艺的Bipolar VCO和CMOS VCO性能对比

    Institute of Scientific and Technical Information of China (English)

    欧阳宏志; 陈洪云; 苏旷宇

    2007-01-01

    阐述了基于BiCMOS工艺的全集成LC调谐压控振荡器的基本原理.为了比较Bipolar VCO和CMOS VCO的性能,他们很好地设计在同一块芯片上.在560M的中心频率上,CMOS VCO无论在功耗,还是在相位噪声方面都要优于Bipolar VCO,他们的电流消耗分别为3.9 mA和5.9 mA,两种VCO都是基于0.6 μm BiCMOS工艺而仿真和测量的.

  1. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  2. A CMOS Wideband Linear Current Attenuator with Electronically Variable Gain

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1993-01-01

    A CMOS highly linear current attenuator is described. The circuit is suited for both differential and single input currents. The current gain is electronically variable between -1 and +1 by means of two controlling currents. A simple additional circuit is described to obtain a gain that is linearly

  3. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators.

    Science.gov (United States)

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  4. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    Directory of Open Access Journals (Sweden)

    Mao-Chen Liu

    2010-02-01

    Full Text Available This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  5. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the outpu

  6. Fundamental Characteristics of a Pinned Photodiode CMOS Pixels

    NARCIS (Netherlands)

    Xu, Y.

    2015-01-01

    This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier.

  7. A CMOS low-noise instrumentation amplifier using chopper modulation

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...

  8. A CMOS image sensor with row and column profiling means

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.; Wang, X.; Leijtens, J.A.P.; Hakkesteegt, H.; Jansen, H.

    2008-01-01

    This paper describes the implementation and firstmeasurement results of a new way that obtains row and column profile data from a CMOS Image Sensor, which is developed for a micro-Digital Sun Sensor (μDSS).The basic profiling action is achieved by the pixels with p-type MOS transistors which realize

  9. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  10. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Science.gov (United States)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  11. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  12. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...

  13. Planar CMOS analog SiPMs: design, modeling, and characterization

    Science.gov (United States)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  14. CMOS image sensors as an efficient platform for glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-07

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

  15. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  16. Analysis of the Noise Characteristics of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1997-01-01

    is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches...

  17. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.;

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of t...

  18. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    Science.gov (United States)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  19. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  20. Reducing crosstalk in vertically integrated CMOS image sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2010-01-01

    Image sensors can benefit from 3D IC fabrication methods because photodetectors and electronic circuits may be fabricated using significantly different processes. When fabricating the die that contains the photodetectors, it is desirable to avoid pixel level patterning of the light sensitive semiconductor. But without a physical border between adjacent photodetectors, lateral currents may flow between neighboring devices, which is called "crosstalk". This work introduces circuits that can be used to reduce crosstalk in vertically-integrated (VI) CMOS image sensors with an unpatterned photodetector array. It treats the case of a VI-CMOS image sensor composed of a silicon die with CMOS read-out circuits and a transparent die with an unpatterned array of photodetectors. A reduction in crosstalk can be achieved by maintaining a constant electric potential at all nodes, at which the photodetector array connects with the readout circuit array. This can be implemented by designing a pixel circuit that uses an operational amplifier with a logarithmic feedback to control the voltage at the input node. The work presents several optional circuit configurations for the pixel circuit, and indicates the one that is the most power efficient. Afterwards, it uses a simplified small-signal model of the pixel circuit to address stability and compensation issues. Lastly, the method is validated through circuit simulation for a standard CMOS process.

  1. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  2. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  3. Research-grade CMOS image sensors for remote sensing applications

    Science.gov (United States)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  4. The Influenza A(H1N1)v Pandemic: An Exploratory System Dynamics Approach

    NARCIS (Netherlands)

    Pruyt, E.; Hamarat, C.

    2010-01-01

    This paper presents a small exploratory System Dynamics model related to the dynamics of the 2009 flu pandemic, also known as the Mexican flu, swine flu, or A(H1N1)v. The model was developed in May 2009 in order to quickly foster understanding about the possible dynamics of this new flu variant and

  5. [Influenza A H1N1v treated with extra-corporal membrane oxygenation.

    DEFF Research Database (Denmark)

    Jensen, Reinhold; Severinsen, Inge Krogh; Terp, Kim;

    2010-01-01

    . Polymerase chain reaction test for H1N1v was positive until day ten. No mutations were found in the virus. The patient was given oseltamivir tablets and inhalable zanamivir as well as antibiotics. The patient was treated with extra-corporal membrane oxygenation (EcmO) for 12 days followed by ventilator...

  6. Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

    Science.gov (United States)

    Shufeng Ren

    As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on

  7. French experience of 2009 A/H1N1v influenza in pregnant women.

    Directory of Open Access Journals (Sweden)

    Grégory Dubar

    Full Text Available BACKGROUND: The first reports on the pandemic influenza 2009 A/H1N1v from the USA, Mexico, and Australia indicated that this disease was associated with a high mortality in pregnant women. The aim of this study was to describe and compare the characteristics of severe critically ill and non-severe pregnant women with 2009 A/H1N1v-related illness in France. METHODOLOGY/PRINCIPAL FINDINGS: A national registry was created to screen pregnant women with laboratory-confirmed 2009 A/H1N1v influenza. Three hundred and fifteen patients from 46 French hospitals were included: 40 patients were admitted to intensive care units (severe outcomes, 111 were hospitalized in obstetric or medical wards (moderate outcomes, and 164 were outpatients (mild outcomes. The 2009 A/H1N1v influenza illness occurred during all pregnancy trimesters, but most women (54%, notably the severe patients (70%, were in the third trimester. Among the severe patients, twenty (50% underwent mechanical ventilation, and eleven (28% were treated with extracorporeal membrane oxygenation. Three women died from A/H1N1v influenza. We found a strong association between the development of a severe outcome and both co-existing illnesses (adjusted odds ratio [OR], 5.1; 95% confidence interval [CI], 2.2-11.8 and a delay in oseltamivir treatment after the onset of symptoms (>3 or 5 days (adjusted OR, 4.8; 95% CI, 1.9-12.1 and 61.2, 95% CI; 14.4-261.3, respectively. Among the 140 deliveries after 22 weeks of gestation known to date, 19 neonates (14% were admitted to a neonatal intensive care unit, mainly for preterm delivery, and two neonates died. None of these neonates developed 2009 A/H1N1v infection. CONCLUSIONS: This series confirms the high incidence of complications in pregnant women infected with pandemic A/H1N1v observed in other countries but depicts a lower overall maternal and neonatal mortality and morbidity than indicated in the USA or Australia. Moreover, our data demonstrate the

  8. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  9. Photon detection with CMOS sensors for fast imaging

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J. [IPHC, Universite Louis Pasteur, CNRS/IN2P3, BP 28, F-67037 Strasbourg (France)], E-mail: baudot@in2p3.fr; Dulinski, W.; Winter, M. [IPHC, Universite Louis Pasteur, CNRS/IN2P3, BP 28, F-67037 Strasbourg (France); Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N. [Universite de Lyon, Universite Lyon 1, Lyon, F-69003 (France); Institut de Physique Nucleaire de Lyon, CNRS/IN2P3, Villeurbanne, F-69622 (France)

    2009-06-01

    Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e{sup -}, and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100{mu}s have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

  10. An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

    Science.gov (United States)

    Guo, Zhiyong; Li, Qiang; Liu, Haiqi; Yan, Bo; Li, Guangjun

    2011-06-01

    This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), ? input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

  11. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  12. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  13. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  14. A New 1-V Second-Order Temperature-Compensated Current Reference

    Institute of Scientific and Technical Information of China (English)

    YI Jun; ZHANG Bo; FANG Jian; LI Zhaoji

    2004-01-01

    A new bipolar temperature-compensated current reference is proposed.The first-order temperature compensation is achieved by the idea of self temperature-compensation configuration exploiting the temperature coefficient of a combined resistor.The second-order compensation employs a VBE-tracking thermal-startup technique to obtain improved temperature performance.The proposed circuit can operate down to a 1-V supply.A temperature coefficient of 46.6 ×10-6/ ℃ [0,100 ℃] at a 1-V supply and a supply regulation of 0.036%/V at 25 ℃ are achieved.Compared with present works,the proposed circuit shows better results of the temperature coefficient and supply regulation.The current matching issue frequently encountered in current references is also discussed in detail.

  15. Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

    Directory of Open Access Journals (Sweden)

    Edwin Becerra‐Álvarez

    2009-04-01

    Full Text Available This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA for the next generation of wireless hand‐held devicesby using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing thefulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such thatthe mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit underanalysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topologyincluding inductive‐source degeneration, MOS‐varactor based tuning networks, and programmable bias currents. This proposal,with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications;the LNA is designed to cope with the requirements of GSM (PCS1900, WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g. In orderto evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA featuresNF16dB, S11‐3.3 dBm over the 1.85‐2.48 GHz band. For all the standards understudy the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of thereconfigurable LNA occupies an area of 1.8mm2.

  16. 技术手册:prb 1v3技术分析

    Institute of Scientific and Technical Information of China (English)

    Lucid; Dreaming

    2005-01-01

    Cpl_Mill A炸点左侧通道,从来都是兵家必争之地,狭长的地形对选手的个人能力提出了极高的要求,在Tearn9与SK.swe比赛的关键局中,Team9的新人prb就在这个位置上演了一出精彩的1v3,使得Team9拿下了这个关键局,把SK.swe在上半场的经济打入谷底,为最终的胜利奠定了良好的基础。下面我们就从技术角度来分析一下这个1v3。(由于比赛的hltv录像质量原因,为了让读者更好地看到这次1v3的精髓,小编们亲自上阵做了一次示意图。)

  17. System and Circuit Design Aspects for CMOS Wireless Handset Receivers

    DEFF Research Database (Denmark)

    Mikkelsen, Jan H.

    The presented work deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. First, an overview, from a historic perspective, on the use of CMOS in cellular applications is provided. Based on this the tremendous...... practice to employ a full separation of different distortion mechanisms. While this approach is very useful when an implementation performance surplus is available it is not an option when a low-cost silicon technology is the target. To manage this, a simple approach that allows all interfering components...... closely spaced adjacent inductors by approximately 10-15dB. At larger distances the gain of having a guard-ring reduces and eventually the gain reduces to zero dB. For modeling purposes an extended lumped element model is proposed and found to fit very well with crosstalk measurements....

  18. 65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction

    CERN Document Server

    Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

    2014-01-01

    Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

  19. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  20. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  1. A novel noise optimization technique for inductively degenerated CMOS LNA

    Science.gov (United States)

    Zhiqing, Geng; Haiyong, Wang; Nanjian, Wu

    2009-10-01

    This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

  2. High Speed Boosted Cmos Differential Logic for Ripple Carry Adders

    Directory of Open Access Journals (Sweden)

    Meenu Roy,

    2014-01-01

    Full Text Available This paper describes a high speed boosted CMOS differential logic which is applicable in Ripple Carry Adders. The proposed logic operating with supply voltage approaching the MOS threshold voltage. The logic style improves switching speed by boosting the gate-source voltage of transistors along timing critical signal path. It allows a single boosting circuit to be shared by complementary outputs as a result the area overhead also minimizes. As compared to the conventional logic gates the EDP (energy delay product is improved. The test sets of logic gates and adders where designed in tsmc0.18μm of Mentor Graphics EDA tool. The experimental result for Ripple Carry Adders using the proposed logic style revealed that the addition time is reduced as compared with the conventional CMOS circuits.

  3. A novel noise optimization technique for inductively degenerated CMOS LNA

    Institute of Scientific and Technical Information of China (English)

    Geng Zhiqing; Wang Haiyong; Wu Nanjian

    2009-01-01

    This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

  4. Pixel front-end development in 65 nm CMOS technology

    CERN Document Server

    Havránek, M; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.

  5. Micromachined high-performance RF passives in CMOS substrate

    Science.gov (United States)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  6. Monolithic CMOS-compatible zero-index metamaterials

    CERN Document Server

    Vulis, Daryl I; Reshef, Orad; Camayd-Muñoz, Philip; Yin, Mei; Kita, Shota; Lončar, Marko; Mazur, Eric

    2016-01-01

    Zero-index materials exhibit exotic optical properties that can be utilized for integrated-optics applications. However, practical implementation requires compatibility with complementary metallic-oxide-semiconductor (CMOS) technologies. We demonstrate a CMOS-compatible zero-index metamaterial consisting of a square array of air holes in a 220-nm-thick silicon-on-insulator (SOI) wafer. This design is achieved through a Dirac-cone dispersion. The metamaterial is entirely composed of silicon and offers compatibility through low-aspect-ratio structures that can be simply fabricated in a standard device layer. This platform enables mass adoption and exploration of zero-index-based photonic devices at low cost and high fidelity.

  7. TID Simulation of Advanced CMOS Devices for Space Applications

    Science.gov (United States)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  8. Challenges of 22 nm and beyond CMOS technology

    Institute of Scientific and Technical Information of China (English)

    HUANG Ru; WU HanMing; KANG JinFeng; XIAO DeYuan; SHI XueLong; AN Xia; TIAN Yu; WANG RunSheng; ZHANG LiangLiang; ZHANG Xing; WANG YangYuan

    2009-01-01

    It is predicted that CMOS technology will probably enter Into 22 nm node around 2012.Scaling of CMOS logic technology from 32 to 22 nm node meets more critical Issues and needs some significant changes of the technology,as well as integration of the advanced processes.This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes,including double patterning technology with high NA water immersion lithography and EUV lithography,new device architectures,high K/metal gate (HK/MG) stack and integration technology,mobility enhancement technologies,source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

  9. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  10. A linear stepping PGA used in CMOS image sensors

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 李斌桥; 赵士彬; 李红乐; 姚素英

    2009-01-01

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  11. A New CMOS Current Reference with High Order Temperature Compensation

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 (m standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [(50~100℃] at a 1.8 V supply, and also achieves line regulation of 0.01%/V and (120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.

  12. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  13. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  14. A Modular Programmable CMOS Analog Fuzzy Controller Chip

    OpenAIRE

    1999-01-01

    We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area a...

  15. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication

    Science.gov (United States)

    2008-08-25

    This approach combines a semiconductor transistor system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each...hybrid CMOS/nanodevice integrated circuits [10-12]. Such circuit combines a semiconductor transistors system with a nanowire crossbar, with simple two...both with and without embedded metallic clusters), self-assembled molecular monolayers, and thin chalcogenide and crystalline perovskite layers [20

  16. Linear dynamic range enhancement in a CMOS imager

    Science.gov (United States)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  17. IGBT Scaling Principle Toward CMOS Compatible Wafer Processes

    OpenAIRE

    2012-01-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in t...

  18. A Low-Cost CMOS Programmable Temperature Switch

    OpenAIRE

    Nanjian Wu; Yunlong Li

    2008-01-01

    A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a ...

  19. Radiation-induced edge effects in deep submicron CMOS transistors

    CERN Document Server

    Faccio, F

    2005-01-01

    The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

  20. High-speed modulator in zero-change CMOS photonics

    CERN Document Server

    Alloatti, Luca; Ram, Rajeev Jagga

    2016-01-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  1. Ring CMOS NOT-based Oscillators: Analysis and Design

    Directory of Open Access Journals (Sweden)

    F. Sandoval-Ibarra

    2008-04-01

    Full Text Available This paper presents design hints in CMOS ring oscillators based on NOT gates. The NOT gate is usedas vehicle to introduce basics on signal propagation and also to present simple design models. Bothsimulation and experimental results are presented in order to show the usefulness of the design models.However, for high frequency oscillators several design strategies that are translated at layout level arealso described not only to minimize undesirable effects, but also for testing the circuit under study (CUS.

  2. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  3. First result on biased CMOS MAPs-on-diamond devices

    Energy Technology Data Exchange (ETDEWEB)

    Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  4. CMOS IC design for wireless medical and health care

    CERN Document Server

    Wang, Zhihua; Chen, Hong

    2014-01-01

    This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to tu...

  5. High Q-factor CMOS-MEMS inductor

    CERN Document Server

    Dai, Ching-Liang; Liu, Mao-Chen

    2008-01-01

    This study investigates a high Q-factor spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process. The spiral inductor is manufactured on silicon substrate using the 0.35 micrometers CMOS process. In order to reduce the substrate loss and enhance the Q-factor of the inductor, silicon substrate under the inductor is removed using a post-process. The post-process uses RIE (reactive ion etching) to etch the sacrificial layer of silicon dioxide, and then TMAH (tetra methyl ammonium hydroxide) is employed to remove the underlying silicon substrate and obtain the suspended spiral inductor. The advantage of the post process is compatible with the CMOS process. The Agilent 8510C network analyzer and a Cascade probe station are used to measure the performances of the spiral inductor. Experiments indicate that the spiral inductor has a Q-factor of 15 at 11 GHz, an inductance of 4 nH at 25.5 GHz and a self-resonance frequency of about 27 GHz.

  6. Design of a high frequency low voltage CMOS operational amplifier

    Directory of Open Access Journals (Sweden)

    Priyanka Kakoty

    2011-03-01

    Full Text Available A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMPdesigned is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-ampsis a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHzand exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition.Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

  7. Design of a high frequency low voltage CMOS operational amplifier

    Directory of Open Access Journals (Sweden)

    Priyanka Kakoty

    2011-03-01

    Full Text Available A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMPdesigned is a two-stage CMOS OPAMP followed by an output buffer. This OperationalTransconductance Amplifier (OTA employs a Miller capacitor and is compensated with a current buffercompensation technique. The unique behaviour of the MOS transistors in saturation region not onlyallows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-ampsis a multi-dimensional-optimization problem where optimization of one or more parameters may easilyresult into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHzand exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, theproposed compensation method results in a higher unity gain frequency under the same load condition.Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

  8. CMOS integration of inkjet-printed graphene for humidity sensing.

    Science.gov (United States)

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-11-30

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  9. Seamless integration of CMOS and microfluidics using flip chip bonding

    Science.gov (United States)

    Welch, David; Blain Christen, Jennifer

    2013-03-01

    We demonstrate the microassembly of PDMS (polydimethylsiloxane) microfluidics with integrated circuits made in complementary metal-oxide-semiconductor (CMOS) processes. CMOS-sized chips are flip chip bonded to a flexible polyimide printed circuit board (PCB) with commercially available solder paste patterned using a SU-8 epoxy. The average resistance of each flip chip bond is negligible and all connections are electrically isolated. PDMS is attached to the flexible polyimide PCB using a combination of oxygen plasma treatment and chemical bonding with 3-aminopropyltriethoxysilane. The total device has a burst pressure of 175 kPA which is limited by the strength of the flip chip attachment. This technique allows the sensor area of the die to act as the bottom of the microfluidic channel. The SU-8 provides a barrier between the pad ring (electrical interface) and the fluids; post-processing is not required on the CMOS die. This assembly method shows great promise for developing analytic systems which combine the strengths of microelectronics and microfluidics into one device.

  10. CMOS integration of inkjet-printed graphene for humidity sensing

    Science.gov (United States)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  11. Optimization of precision localization microscopy using CMOS camera technology

    Science.gov (United States)

    Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

    2012-02-01

    Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, super resolution precision localization microscopy.

  12. Low voltage electron multiplying CCD in a CMOS process

    Science.gov (United States)

    Dunford, Alice; Stefanov, Konstantin; Holland, Andrew

    2016-07-01

    Low light level and high-speed image sensors as required for space applications can suffer from a decrease in the signal to noise ratio (SNR) due to the photon-starved environment and limitations of the sensor's readout noise. The SNR can be increased by the implementation of Time Delay Integration (TDI) as it allows photoelectrons from multiple exposures to be summed in the charge domain with no added noise. Electron Multiplication (EM) can further improve the SNR and lead to an increase in device performance. However, both techniques have traditionally been confined to Charge Coupled Devices (CCD) due to the efficient charge transfer required. With the increase in demand for CMOS sensors with equivalent or superior functionality and performance, this paper presents findings from the characterisation of a low voltage EMCCD in a CMOS process using advanced design features to increase the electron multiplying gain. By using the CMOS process, it is possible to increase chip integration and functionality and achieve higher readout speeds and reduced pixel size. The presented characterisation results include analysis of the photon transfer curve, the dark current, the electron multiplying gain and analysis of the parameters' dependence on temperature and operating voltage.

  13. Noise sources and noise suppression in CMOS imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  14. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A; Spiriti, E.; Baudot, J.; Claus, G.; Goffe, M.; Winter, M.

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  15. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  16. Single photon detection and localization accuracy with an ebCMOS camera

    Science.gov (United States)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  17. TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies

    OpenAIRE

    2011-01-01

    The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits. Peer Reviewed

  18. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    Energy Technology Data Exchange (ETDEWEB)

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  19. Seroprevalence study in Vojvodina (Serbia following 2009 pandemic influenza A(H1N1v

    Directory of Open Access Journals (Sweden)

    Petrović Vladimir

    2012-01-01

    Full Text Available Introduction. The seroprevalence study was performed in Vojvodina during May and June 2010 in order to asses the effects of the 2009 pandemic influenza A(H1N1v epidemic on herd immunity. It was a part of the Serbian Ministry of Health funded nationwide study. Objective. Prevalence of antibodies against 2009 pandemic influenza A(H1N1v was determined in a 1% sample of the population monitored for influenza-like illness and acute respiratory infections in Vojvodina through sentinel surveillance system. Methods. The study sample involved a total of 1004 inhabitants of Vojvodina. The control group consisted of randomly selected and age-adjusted 1054 sera collected in the pre-pandemic period. Sera were tested by the reaction of hemagglutination inhibition using influenza A/California/7/2009 (H1N1 antigen in dilution from 1:8 to 1:256. Antibody titers ≥1:32 and ≥1:8 were considered protective and diagnostic, respectively. Results. The differences between control and study sera in all age groups were significant for both diagnostic ≥1/8 and protective titres ≥1/32 of hemagglutination inhibition antibodies (chi square test, p<0.001. The highest percentage of seropositive subjects was registered in the age group 15-19 years followed by children aged 5-14 years. Both diagnostic and protective titres were about twice higher in the vaccinated as compared to the non-vaccinated group. There were no statistically significant differences in seroprevalence between seven districts of Vojvodina. Conclusion. The 2009 pandemic influenza A(H1N1v epidemic significantly influenced the herd immunity in our population regardless of low immunization coverage with highest immunity levels in adolescents aged 15-19 years and with similar herd immunity levels in all the regions in the province six months after the outbreak.

  20. 76 FR 20835 - Amendment of VOR Federal Airways V-1, V-7, V-11 and V-20; Kona, HI

    Science.gov (United States)

    2011-04-14

    ... Administration 14 CFR Part 71 Amendment of VOR Federal Airways V-1, V-7, V-11 and V-20; Kona, HI AGENCY: Federal... delays the effective date for the amendment of four VOR Federal airways in the vicinity of Kona, HI; V-1...), amends VOR Federal Airways V-1, V-7 V-11 and V-20; Kona, HI. These VHF Omnidirectional Range...

  1. Design of Traditional CMOS to Adiabatic CMOS Interface Circuit%传统CMOS到绝热CMOS接口电路的设计

    Institute of Scientific and Technical Information of China (English)

    郁军军; 汪鹏君

    2006-01-01

    通过对传统CMOS与绝热CMOS接口电路的研究,在分析传统CMOS信号和绝热信号的时序关系的基础上提出了三种传统CMOS到绝热CMOS(Traditional CMOS to Adiabatic CMOS,TC/AC)接口电路的设计方案,实现了将传统CMOS信号到绝热信号的转变.最后HSPICE模拟验证了所设计的三种TC/AC接口电路逻辑功能的正确性.

  2. 从嵌入CMOS MEMS振荡器展望IC设计的潜在变革%Embedding CMOS MEMS Oscillator Push Potential IC Design Revolution

    Institute of Scientific and Technical Information of China (English)

    周智勇

    2007-01-01

    随着CMOS MEMS振荡器大规模制造技术的成熟,应用将涉及汽车、电视、摄像机、个人电脑、便携式设备等等几乎一切电子设备,本文向中国工程师概要介绍CMOS MEMS谐振器主流技术及行业动态、在IC中嵌入CMOS MEMS振荡器的设计流程以及相关支持工具的发展趋势.

  3. Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

    Science.gov (United States)

    Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

    2008-11-01

    This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

  4. A 1 V supercapacitor device with nanostructured graphene oxide/polyaniline composite materials

    Indian Academy of Sciences (India)

    Deepak Kumar; Anjan Banerjee; Satish Patil; Ashok K Shukla

    2015-10-01

    Polyaniline and graphene oxide composite on activated carbon cum reduced graphene oxide-supported supercapacitor electrodes are fabricated and electrochemically characterized in a three-electrode cell assembly. Attractive supercapacitor performance, namely high-power capability and cycling stability for graphene oxide/polyaniline composite, is observed owing to the layered and porous-polymeric-structured electrodes. Based on the materials characterization data in a three-electrode cell assembly, 1 V supercapacitor devices are developed and performance tested. A comparative study has also been conducted for polyaniline and graphene oxide/polyaniline composite-based 1 V supercapacitors for comprehending the synergic effect of graphene oxide and polyaniline. Graphene oxide/polyaniline composite-based capacitor that exhibits about 100 F g−1 specific capacitance with faradaic efficiency in excess of 90% has its energy and power density values of 14 Wh kg−1 and 72 kW kg−1, respectively. Cycle-life data for over 1000 cycles reflect 10% capacitance degradation for graphene oxide/polyaniline composite supercapacitor.

  5. Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array

    Science.gov (United States)

    Yamaji, Yuuki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Electrophoresis is widely used in biomedical applications. However, conventional (centimeter-order) electrophoresis requires a high-voltage power supply, which is not suitable for point-of-care testing (POCT). Electrophoresis is driven by electric fields, and miniaturization (from the centimeter order to the micrometer order) is effective for low-voltage operation. A CMOS platform is a cost-competitive and promising candidate for miniaturization and enables the integration of biomolecule manipulation by electrophoresis and its electrochemical sensing. These features will contribute to the development of a biochemical analyzer called the micro-total analysis system (µ-TAS). To realize a truly portable electrophoresis system, we present the design and experimental verification of a low-voltage (<1 V), two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array. Experimental results showed successful constant voltage outputs to each electrode. By miniaturizing the electrode structure to a 60 µm pitch, we achieved sufficient electric field strength even at low voltages.

  6. Leakage Power Reduction and Analysis of CMOS Sequential Circuits

    Directory of Open Access Journals (Sweden)

    M. Janaki Rani

    2012-02-01

    Full Text Available A significant portion of the total power consumption in high performance digital circuits in deep sub micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

  7. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  8. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  9. An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.

    2013-01-01

    This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

  10. Feasibility Study of Analogue and Digital Temperature Sensors in Nanoscale CMOS Technologies

    NARCIS (Netherlands)

    Geljon, M.; Sill, F.; De Lima Monteiro, D.W.

    2009-01-01

    The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Te

  11. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Kovalgin, Alexey Y.; Werf, van der Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  12. Power amplifiers in CMOS technology : a contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, Mustafa

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers(PAs) in the mainstream CMOS technology is essential. In general, CMOS PAs require high supply-voltage to decrease the matching network losses and for high output pow

  13. Design rules for RCA self-aligned silicon-gate CMOS/SOS process

    Science.gov (United States)

    1977-01-01

    The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

  14. Design of Multivalued Circuits Based on an Algebra for Current—Mode CMOS Multivalued Circuits

    Institute of Scientific and Technical Information of China (English)

    陈偕雄; ClaudioMoraga

    1995-01-01

    An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed.this paper discusses its application in the design of multivalued circuits.Several current-mode CMOS quaternary and quinary circuits are designed by algebraic means.The design method based on this algebra may offer a design simpler than the previously known ones.

  15. SOI CMOS Imager with Suppression of Cross-Talk

    Science.gov (United States)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  16. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  17. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  18. Monolithic CMOS-MEMS resonant beams for ultrasensitive mass detection

    OpenAIRE

    Verd Martorell, Jaume

    2008-01-01

    Consultable des del TDX Títol obtingut de la portada digitalitzada Estructures ressonants en forma de biga (p.e. ponts o palanques) són molt interessants com a element transductor en sensors físics, químics i biològics basats en sistemes micro-/nanoelectromecànics (M-/NEMS) degut a la seva simplicitat, al gran rang de dominis que poden sensar, i a la seva extremada alta sensibilitat. Aquesta tesis està focalitzada en el disseny, fabricació i caracterització de CMOS-MEMS monolítics basat...

  19. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  20. All-Digital ADC Design in 65 nm CMOS Technology

    OpenAIRE

    Pathapati, Srinivasa Rao

    2014-01-01

    The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the ...

  1. Extrinsic parameter extraction and RF modelling of CMOS

    Science.gov (United States)

    Alam, M. S.; Armstrong, G. A.

    2004-05-01

    An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation.

  2. Power comparison of CMOS and adiabatic full adder circuit

    CERN Document Server

    Reddy, Sunil Gavaskar; 10.5121/vlsic.2011.2306

    2011-01-01

    Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

  3. Design considerations for a low-noise CMOS image sensor

    Science.gov (United States)

    González-Márquez, Ana; Charlet, Alexandre; Villegas, Alberto; Jiménez-Garrido, Francisco; Medeiro, Fernando; Domínguez-Castro, Rafael; Rodríguez-Vázquez, Ángel

    2015-03-01

    This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.

  4. Design procedure for optimizing CMOS low noise operational amplifiers

    Institute of Scientific and Technical Information of China (English)

    Li Zhiyuan; Ye Yizheng; Ma Jianguo

    2009-01-01

    This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

  5. CMOS realization of a 2-layer CNN universal machine chip.

    Science.gov (United States)

    Carmona, R; Jiménez-Garrido, F; Domínguez-Castro, R; Espejo, S; Rodríguez-Vázquez, A

    2003-12-01

    Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5 microm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5 x 10(6) transistors, most of them operating in analog mode, are presented in this paper.

  6. CMOS vertical hall magnetic sensors on flexible substrate

    OpenAIRE

    2016-01-01

    This paper presents the realization of different\\ud Vertical Hall Sensors (VHSs) implemented using a 0.18-μm\\ud CMOS technology and mounted on flexible substrates. Various\\ud geometries of VHS have been studied to obtain the optimum\\ud sensor device dimension and shape. COMSOL multiphysics\\ud simulation results are validated with respect to the electrical\\ud behaviour of an 8-resistor Verilog-A model implemented in\\ud Cadence environment. Simulation and measurement results are in\\ud good agre...

  7. The DUV Stability of Superlattice-Doped CMOS Detector Arrays

    Science.gov (United States)

    Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

    2013-01-01

    JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

  8. Trade-offs in Specific CMOS RF Communication Circuits

    Institute of Scientific and Technical Information of China (English)

    李效龙; 田雨波

    2009-01-01

    The design trade-off in the front-end of the transceiver, such as LNA, mixer, local oscillator and PA, is concerned. The advantages and limitations of the circuit topologies and key parameters of the state-of-the-art CMOS transceiver building blocks are discussed in order to gain more insight about a specific block design. A normalized formula of the figures of merit for each building block is also proposed to evaluate the overall performance of various circuits for fair comparison.

  9. Design and optimization of BCCD in CMOS technology

    Science.gov (United States)

    Gao, Jing; Li, Yi; Gao, Zhi-yuan; Luo, Tao

    2016-09-01

    This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency ( CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

  10. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    Science.gov (United States)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration

  11. Effect of ABCA1-V771M polymorphism on plasma lipid levels and its relationship with coronary atherosclerotic heart disease

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Objective To explore the risk association of ABCA1-V771M polymorphism with coronary heart disease(CHD)in Han nationality in Northwest of China.Methods With case-control study,ABCA1-V771M polymorphism was detected in 204 unrelated Han nationality people in Northwest of China,and all the subjects by coronary angiography were grouped into 106 cases and 98 controls.The genotypes and alleles frequency distribution of ABCA1-V771M polymorphisms were analyzed by PCR-RFLP analysis,and the clinical statistics of seru...

  12. Comparative Study of CMOS Op-Amp In 45nm And 180 Nm Technology

    Directory of Open Access Journals (Sweden)

    Siddharth

    2014-07-01

    Full Text Available In this paper we have provided a method for designing a Two Stage CMOS Operational Amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS Technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as Gain, Phase Margin,GBW,3db Gain etc. and the results obtained for 45n CMOS Technology is compared with those obtained for 180nm CMOS Technology It has been demonstrated that on lowering the technology and keeping the slew rate constant, the Power dissipation decreases.

  13. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    AUTHOR|(CDS)2070112; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  14. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    Science.gov (United States)

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  15. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    Science.gov (United States)

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

  16. An electrostatic CMOS/BiCMOS Lithium ion vibration-based harvester-charger IC

    Science.gov (United States)

    Torres, Erick Omar

    Self-powered microsystems, such as wireless transceiver microsensors, appeal to an expanding application space in monitoring, control, and diagnosis for commercial, industrial, military, space, and biomedical products. As these devices continue to shrink, their microscale dimensions allow them to be unobtrusive and economical, with the potential to operate from typically unreachable environments and, in wireless network applications, deploy numerous distributed sensing nodes simultaneously. Extended operational life, however, is difficult to achieve since their limited volume space constrains the stored energy available, even with state-of-the-art technologies, such as thin-film lithium-ion batteries (Li Ion) and micro-fuel cells. Harvesting ambient energy overcomes this deficit by continually replenishing the energy reservoir and, as a result, indefinitely extending system lifetime. In this work, an electrostatic harvester that harnesses ambient kinetic energy from vibrations to charge an energy-storage device (e.g., a battery) is investigated, developed, and evaluated. The proposed harvester charges and holds the voltage across a vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). The challenge is that energy is harnessed at relatively slow rates, producing low output power, and the electronics required to transfer it to charge a battery can easily demand more than the power produced. To this end, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient quasi-lossless inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during every vibration cycle. Two energy-harvesting integrated circuits (IC) were analyzed, designed, developed, and validated using a 0.7-im BiCMOS process and a 30-Hz

  17. 绝热CMOS与传统CMOS接口电路的设计%Design of adiabatic CMOS and traditional CMOS interface circuit

    Institute of Scientific and Technical Information of China (English)

    郁军军; 汪鹏君

    2007-01-01

    为了将绝热CMOS电路嵌入到传统电路系统中替代耗能较大的部件,本文研究并设计绝热CMOS电路和传统CMOS电路两者之间的接口电路:传统CMOS到绝热CMOS(Traditional CMOS to Adiabatic CMOS,TC/AC)的接口电路、绝热CMOS到传统CMOS(Adiabatic CMOS to Traditional CMOS,AC/TC)的接口电路.这样传统CMOS电路可以通过TC/AC接口电路来驱动绝热CMOS电路,绝热CMOS电路可以通过AC/TC接口电路来驱动传统CMOS电路,从而可以利用具低功耗特性的绝热CMOS电路来降低整个电路系统的功耗,增强绝热CMOS电路的实用性.最后计算机模拟验证了TC/AC接口电路和AC/TC接口电路逻辑功能的正确性.

  18. 高精度CMOS DEM-CCⅡ放大器%High-Precision CMOS DEM-CC Ⅱ Amplifier

    Institute of Scientific and Technical Information of China (English)

    张雷; 成立; 周洋; 张静; 倪雪梅; 王振宇

    2009-01-01

    采用动态元件匹配二代电流传输器(DEM-CCⅡ)技术,设计了一种0.35 μm标准工艺的高精度CMOS放大器.通过比较传统的CMOS运放可知,所设计的CMOS放大器既增大了输出摆幅又减小了输出阻抗,且有效地限制了有限的运放增益对电路性能的影响.仿真实验结果表明,该CMOS放大器增益误差比传统运放的增益误差小38~50倍,精度等级明显提高,因而特别适用于各类检测和信号调理放大器的设计中.%CMOS amplifiers with high-precision was designed in a standard 0.35 μm CMOS process by properly applying dynamic element matching to a second generation current conveyor. Compared with traditional CMOS circuits, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite operational amplifier gain. The simulation results show that the gain error is reduced 38~50 times than the gain error of operational amplifiers, and the precision is improved, it is very suitable for the design of various detections and signal conditioning amplifiers.

  19. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  20. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-06

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  1. An Ultra Wideband VHF CMOS LC VCO%超宽频带VHF频段CMOS LC VCO

    Institute of Scientific and Technical Information of China (English)

    宁彦卿; 王志华; 陈弘毅

    2006-01-01

    This paper presents a VHF CMOS VCO. The most significant improvement on the VCO is that the cross-coupled MOSFET pairs are divided into several switchable parts so the characteristics can compensate the state change that results from the frequency tuning of the oscillator. This VCO is implemented in 0.18μm CMOS with a core area of about 550μm × 700μm. The test results show that the tuning range covers 31~111MHz with a power consumption between 0.3~6.9mW and a phase noise at a 100kHz offset of about - 110dBc/Hz.%实现了一个宽频带VHF频段CMOS VCO.其最大的改进在于将振荡器中交叉耦合MOS管分为并联可开关的若干段.这样使其特性可以在较大范围内补偿VCO调频过程中状态的变化.该VCO使用标准0.18μmCMOS工艺制作,核心版图面积约为550μm×700μm.测试结果表明:该VCO频率覆盖范围为31~111MHz;功耗为0.3~6.9mW;在100kHz频偏处相位噪声约-110dBc/Hz.

  2. Effect of charge sharing on the single event transient response of CMOS logic gates

    Institute of Scientific and Technical Information of China (English)

    Duan Xueyan; Wang Liyun; Lai Jinmei

    2011-01-01

    This paper presents three new types of pulse quenching mechanism (NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node.The three major contributions of this paper are:(1) with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.(2) Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style (i.e.spacing between transistors and n-well contact area).(3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

  3. A CMOS active pixel sensor for retinal stimulation

    Science.gov (United States)

    Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

    2006-02-01

    Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

  4. W-plug via electromigration in CMOS process

    Institute of Scientific and Technical Information of China (English)

    Zhao Wenbin; Chen Haifeng; Xiao Zhiqiang; Li Leilei; Yu Zongguang

    2009-01-01

    We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.

  5. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2013-10-01

    Full Text Available This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT.

  6. A Review on Energy Efficient CMOS Digital Logic

    Directory of Open Access Journals (Sweden)

    B. L. Dokic

    2013-12-01

    Full Text Available Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt and power supply voltage (Vdd on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL, complementary pass logic (CPL, push-pull pass logic (PPL and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

  7. CMOS mm-wave transceivers for Gbps wireless communication

    Science.gov (United States)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  8. Leakage Current Estimation of CMOS Circuit with Stack Effect

    Institute of Scientific and Technical Information of China (English)

    Yong-Jun Xu; Zu-Ying Luo; Xiao-Wei Li; Li-Jian Li; Xian-Long Hong

    2004-01-01

    Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.

  9. CMOS low data rate imaging method based on compressed sensing

    Science.gov (United States)

    Xiao, Long-long; Liu, Kun; Han, Da-peng

    2012-07-01

    Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

  10. CMOS prototype for retinal prosthesis applications with analog processing

    Science.gov (United States)

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  11. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  12. BiCMOS-integrated photodiode exploiting drift enhancement

    Science.gov (United States)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  13. Neutron detectors based on CMOS solid state photomultipliers

    Science.gov (United States)

    Sia, Radia; Christian, James F.; Stapels, Christopher J.; Prettyman, Thomas; Squillante, Michael R.

    2008-08-01

    CMOS solid-state photomultipliers (CMOS-SSPM) are new, potentially very inexpensive, photodetectors that have the promise of supplanting photomultiplier tubes and standard photodiodes for many nuclear radiation detection measurements using scintillator crystals. The compact size and very high gain make SSPMs attractive for use in applications where photomultiplier tubes cannot be used and standard photodiodes have insufficient sensitivity. In this effort, the use of SSPMs was investigated for the detection of neutrons with the goal of designing a detector for portable systems that has the capability of discriminating neutrons from gamma rays. The neutron scintillation signatures were measured using boron-loaded plastic scintillators. Our detector concept design incorporates a dual-scintillator design with both a neutrons sensitive organic scintillator (a boron-loaded gel) and a gamma ray sensitive inorganic scintillator (LYSO). Using this design, the gamma ray signal is suppressed and the neutron events are clearly resolved. The design was modeled to optimize the detection efficiency for both thermal and energetic neutrons. In addition, the detection of thermal neutrons in the presence of gamma rays was examined using the SSPM coupled to Cs2LiYCl6:Ce scintillator (CLYC).

  14. W-CMOS blanking device for projection multibeam lithography

    Science.gov (United States)

    Jurisch, Michael; Irmscher, Mathias; Letzkus, Florian; Eder-Kapl, Stefan; Klein, Christof; Loeschner, Hans; Piller, Walter; Platzgummer, Elmar

    2010-05-01

    As the designs of future mask nodes become more and more complex the corresponding pattern writing times will rise significantly when using single beam writing tools. Projection multi-beam lithography [1] is one promising technology to enhance the throughput compared to state of the art VSB pattern generators. One key component of the projection multi-beam tool is an Aperture Plate System (APS) to form and switch thousands of individual beamlets. In our present setup a highly parallel beam is divided into 43,008 individual beamlets by a Siaperture- plate. These micrometer sized beams pass through larger openings in a blanking-plate and are individually switched on and off by applying a voltage to blanking-electrodes which are placed around the blanking-plate openings. A charged particle 200x reduction optics demagnifies the beamlet array to the substrate. The switched off beams are filtered out in the projection optics so that only the beams which are unaffected by the blanking-plate are projected to the substrate with 200x reduction. The blanking-plate is basically a CMOS device for handling the writing data. In our work the blanking-electrodes are fabricated using CMOS compatible add on processes like SiO2-etching or metal deposition and structuring. A new approach is the implementation of buried tungsten electrodes for beam blanking.

  15. Improvement to the signaling interface for CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Shi, Zhan, E-mail: sz1134@163.com [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Tang, Zhenan, E-mail: tangza@dlut.edu.cn [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Feng, Chong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Dalian Minzu University, No.18 Liaohe West Road, 116600 Dalian (China); Cai, Hong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China)

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  16. An integrated CMOS high data rate transceiver for video applications

    Science.gov (United States)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  17. Design and Analysis of Hybrid CMOS SRAM Sense Amplifier

    Directory of Open Access Journals (Sweden)

    Karishma Bajaj

    2012-03-01

    Full Text Available Sense amplifiers are one of the very important peripheral components of CMOS memories. In a Hybrid Sense amplifier both current and voltage sensing techniques are used which makes it a better selection than a conventional current or voltage sense amplifiers. The hybrid sense amplifier works in three phases-Offset cancellation (200ps, Access phase (500ps and Evaluation phase. The offset cancellation is done simultaneously with word line decoding, so as to speed up the process. The sensing range of the hybrid sense amplifier is improved from 1.18mV to 92mV. Also hybrid sense amplifier consumes very low energy of about 6.84fj. This sense amplifier is analyzed with a column of 512 SRAM cells at 180nm technology node and compared to CMOS conventional voltage sense amplifier. The circuit consumes an average power of 1.57 µW with a negligible offset of 149.3µV.

  18. A CMOS Imager with Focal Plane Compression using Predictive Coding

    Science.gov (United States)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  19. Improvement to the signaling interface for CMOS pixel sensors

    Science.gov (United States)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  20. An integrated CMOS high data rate transceiver for video applications

    Institute of Scientific and Technical Information of China (English)

    Liang Yaping; Che Dazhi; Liang Cheng; Sun Lingling

    2012-01-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology hy using a proprietary protocol,which combines the new IEEE 802.11n features such as multiplein multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment.The RF frequencies cover from 4.9 to 5.9 GHz:the industrial,scientific and medical (ISM) band.Each RF channel bandwidth is 20 MHz.The transceiver utilizes a direct up transmitter and low-IF receiver architecture.A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration.The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  1. A Low-Cost CMOS Programmable Temperature Switch.

    Science.gov (United States)

    Li, Yunlong; Wu, Nanjian

    2008-05-15

    A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm² and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  2. High-stage analog accumulator for TDI CMOS image sensors

    Science.gov (United States)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  3. A Low-Cost CMOS Programmable Temperature Switch

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2008-05-01

    Full Text Available A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  4. Review of radiation damage studies on DNW CMOS MAPS

    Science.gov (United States)

    Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.; Zucca, S.; Bettarini, S.; Rizzo, G.; Morsani, F.; Bosisio, L.; Rashevskaya, I.; Cindro, V.

    2013-12-01

    Monolithic active pixel sensors fabricated in a bulk CMOS technology with no epitaxial layer and standard resistivity (10 Ω cm) substrate, featuring a deep N-well as the collecting electrode (DNW MAPS), have been exposed to γ-rays, up to a final dose of 10 Mrad (SiO2), and to neutrons from a nuclear reactor, up to a total 1 MeV neutron equivalent fluence of about 3.7 ·1013cm-2. The irradiation campaign was aimed at studying the effects of radiation on the most significant parameters of the front-end electronics and on the charge collection properties of the sensors. Device characterization has been carried out before and after irradiations. The DNW MAPS irradiated with 60Co γ-rays were also subjected to high temperature annealing (100 °C for 168 h). Measurements have been performed through a number of different techniques, including electrical characterization of the front-end electronics and of DNW diodes, laser stimulation of the sensors and tests with 55Fe and 90Sr radioactive sources. This paper reviews the measurement results, their relation with the damage mechanisms underlying performance degradation and provides a new comparison between DNW devices and MAPS fabricated in a CMOS process with high resistivity (1 kΩ cm) epitaxial layer.

  5. Custom CMOS Reed Solomon coder for the Hubble Space Telescope

    Science.gov (United States)

    Whitaker, S.; Cameron, K.; Owsley, P.; Maki, G.

    1990-01-01

    A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

  6. HV-CMOS detectors in BCD8 technology

    Science.gov (United States)

    Andreazza, A.; Castoldi, A.; Ceriale, V.; Chiodini, G.; Citterio, M.; Darbo, G.; Gariano, G.; Gaudiello, A.; Guazzoni, C.; Joshi, A.; Liberali, V.; Passadore, S.; Ragusa, F.; Ruscino, E.; Sbarra, C.; Shrimali, H.; Sidoti, A.; Stabile, A.; Yadav, I.; Zaffaroni, E.

    2016-11-01

    This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

  7. NV-CMOS HD camera for day/night imaging

    Science.gov (United States)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  8. FAD-linked Presenilin-1 V97L mutation impede tranport regulation and intracellular Ca(2+) homeostasis under ER stress.

    Science.gov (United States)

    Shao, Yankun; Li, Miao; Wu, Miao; Shi, Kai; Fang, Boyan; Wang, Jie

    2015-01-01

    We report a PS1 gene mutation (Val 97Leu) in a Chinese familial Alzheimer's disease (FAD) pedigree and a cell model of FAD built by transfecting PS1 v97L mutants into human neuroblastoma SH-SY5Y cells. To test our hypothesis that the PS1 v97L mutation is pathogenic, we investigated possible alterations in transport regulation and intracellular Ca(2+) homeostasis in endoplasmic reticulum (ER). Grp78 is an ER-resident chaperone mediating the unfolded protein response (UPR) and is a key regulator of ER stress transducers. KDEL is a 4-amino-acid retention sequence made of Lys-Asp-Glu-Leu-COO. KDEL is a "resident" sequence as protein residence in ER is consistently associated with KDEL at the C-extremity. Our group used KDEL recognizing anti-Grp78 monoclonal antibody to detect the level of Grp78. We found increased KDEL level in all the transfected cells including cells transfected with PS1 V97L genes, wild-type and the mock. However cells with PS1 V97L mutation expressed a relatively lower KDEL compared with the wild-type and the mock, and a significantly lower Grp78 level compared with the wild-type, the mock and control. These results suggest that PS1 V97L mutation impedes intracellular transport regulation in ER. PS1 V97L mutation mediates increased ER Ca(2+) content in human neuroblastoma SH-SY5Y cells. The increased intracellular Ca(2+) release is due to depleted Ca(2+) storing content of ER but not due to extracellular environment as capacitative Ca(2+) entry (CCE) is invariant. PS1 V97L mutation interferes with intracellular Ca(2+) homeostasis. Abnormal transport regulation and Ca(2+) homeostasis attributed to PS1 V97L mutation may be associated with the pathology of Chinese familial FAD.

  9. Stripe rust resistance and dough quality of new wheat - Dasypyrum villosum translocation lines T1DL•1V#3S and T1DS•1V#3L and the location of HMW-GS genes.

    Science.gov (United States)

    Zhao, W C; Gao, X; Dong, J; Zhao, Z J; Chen, Q G; Chen, L G; Shi, Y G; Li, X Y

    2015-07-17

    The transfer of agronomically useful genes from wild wheat species into cultivated wheat is one of the most effective approaches to improvement of wheat varieties. To evaluate the transfer of genes from Dasypyrum villosum into Triticum aestivum, wheat quality and disease resistance was evaluated in two new translocation lines, T1DL•1V#3S and T1DS•1V#3L. We examined the levels of stripe rust resistance and dough quality in the two lines, and identified and located the stripe rust resistant genes and high molecular weight glutenin subunit (HMW-GS) genes Glu-V1 of D. villosum. Compared to the Chinese Spring (CS) variety, T1DL•1V#3S plants showed moderate resistance to moderate susceptibility to the stripe rust races CYR33 and Su11-4. However, T1DS•1V#3L plants showed high resistance or immunity to these stripe rusts. The genes for resistance to stripe rust were located on 1VL of D. villosum. In comparison to CS, the dough from T1DS•1V#3L had a significantly shorter developing time (1.45 min) and stable time (1.0 min), a higher weakness in gluten strength (208.5 FU), and a lower farinograph quality index (18). T1DL•1V#3S had a significantly longer developing time (4.2 min) and stable time (5.25 min), a lower weakness in gluten strength (53 FU) and a higher farinograph quality index (78.5). We also found that T1DS•1V#3L had reduced gluten strength and dough quality compared to CS, but T1DL•1V#3S had increased gluten strength and dough quality. The results of SDS-PAGE analysis indicated that Glu-V1 of D. villosum was located on short arm 1VS and long arm 1VL. These results prove that the new translocation lines, T1DS•1V#3L and T1DS•1V#3L, have valuable stripe rust resistance and dough quality traits that will be important for improving wheat quality and resistance in future wheat breeding programs.

  10. Effect of ABCA1-V771M polymorphism on plasma lipid levels and its relationship with coronary atherosclerotic heart disease

    Institute of Scientific and Technical Information of China (English)

    Wang Dongqi; Li Hongbing; Zhang Tao; Cui Hanbin; Shu Juan; Yang Haitao; Cui Changcong; Joseph B. Muhlestein

    2008-01-01

    Objective To explore the risk association of ABCA1-V771M polymorphism with coronary heart disease (CHD) in Hart nationality in Northwest of China. Methods With case-control study, ABCA1-V771M polymorphism was detected in 204 unrelated Hart nationality people in Northwest of China, and all the subjects by coronary angiography were grouped into 106 cases and 98 controls. The genotypes and alleles frequency distribution of ABCA1-V771M polymorphisms were analyzed by PCR-RFLP analysis, and the clinical statistics of serum lipids were compared and its effects of ABCA1-V771M polymorphism on the plasma lipid levels and coronary atherosclerotic heart disease were analyzed. Results The genotypic frequencies of ABCA1-V771M polymorphism matched well under Hardy-Weinberg equilibrium (P>0.05), V and M allelic frequencies were 33.3% and 66.7%. In comparison with VV+VM genotype carriers, MM genotypes carriers had much lower plasma levels of HDL-C (P0.05). Conclusion ABCA1-V771M polymorphism was not only associated with the plasma levels of HDL-C and TG, but also related to the susceptibility and severity of coronary atheroselerotic heart disease. Moreover, M771 allele appeared to be atherogenie among Han population in Northwest of China.

  11. Structure of HIV-1 gp120 V1/V2 domain with broadly neutralizing antibody PG9

    Energy Technology Data Exchange (ETDEWEB)

    McLellan, Jason S.; Pancera, Marie; Carrico, Chris; Gorman, Jason; Julien, Jean-Philippe; Khayat, Reza; Louder, Robert; Pejchal, Robert; Sastry, Mallika; Dai, Kaifan; O’Dell, Sijy; Patel, Nikita; Shahzad-ul-Hussan, Syed; Yang, Yongping; Zhang, Baoshan; Zhou, Tongqing; Zhu, Jiang; Boyington, Jeffrey C.; Chuang, Gwo-Yu; Diwanji, Devan; Georgiev, Ivelin; Kwon, Young Do; Lee, Doyung; Louder, Mark K.; Moquin, Stephanie; Schmidt, Stephen D.; Yang, Zhi-Yong; Bonsignori, Mattia; Crump, John A.; Kapiga, Saidi H.; Sam, Noel E.; Haynes, Barton F.; Burton, Dennis R.; Koff, Wayne C.; Walker, Laura M.; Phogat, Sanjay; Wyatt, Richard; Orwenyo, Jared; Wang, Lai-Xi; Arthos, James; Bewley, Carole A.; Mascola, John R.; Nabel, Gary J.; Schief, William R.; Ward, Andrew B.; Wilson, Ian A.; Kwong, Peter D. (UWASH); (NIH); (Scripps); (Duke); (IAVI); (Maryland-MED)

    2012-12-13

    Variable regions 1 and 2 (V1/V2) of human immunodeficiency virus-1 (HIV-1) gp120 envelope glycoprotein are critical for viral evasion of antibody neutralization, and are themselves protected by extraordinary sequence diversity and N-linked glycosylation. Human antibodies such as PG9 nonetheless engage V1/V2 and neutralize 80% of HIV-1 isolates. Here we report the structure of V1/V2 in complex with PG9. V1/V2 forms a four-stranded {beta}-sheet domain, in which sequence diversity and glycosylation are largely segregated to strand-connecting loops. PG9 recognition involves electrostatic, sequence-independent and glycan interactions: the latter account for over half the interactive surface but are of sufficiently weak affinity to avoid autoreactivity. The structures of V1/V2-directed antibodies CH04 and PGT145 indicate that they share a common mode of glycan penetration by extended anionic loops. In addition to structurally defining V1/V2, the results thus identify a paradigm of antibody recognition for highly glycosylated antigens, which - with PG9 - involves a site of vulnerability comprising just two glycans and a strand.

  12. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  13. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging.

  14. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  15. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    Science.gov (United States)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  16. Robust Supersolidity in the V1- V2 Extended Bose-Hubbard Model

    Science.gov (United States)

    Greene, Nicole; Pixley, Jedediah

    2016-05-01

    Motivated by ultra-cold atomic gases with long-range interactions in an optical lattice we study the effects of the next-nearest neighbor interaction on the extended Bose-Hubbard model on a square lattice. Using the variational Gutzwiller approach with a four-site unit cell we determine the ground state phase diagrams as a function of the model parameters. We focus on the interplay of each interaction between the nearest neighbor (V1) , the next-nearest neighbor (V2) , and the onsite repulsion (U). We find various super-solid phases that can be described by one of the ordering wave-vectors (π, 0), (0, π) , and (π, π) . In the limits V1, V2 U we find phases reminiscent of the limit V2 = 0 but with a richer super solid structure. For V1

  17. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  18. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    Science.gov (United States)

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  19. Developing CMOS Camera and USB Device Drivers in Linux 2.6.32

    Directory of Open Access Journals (Sweden)

    CH. P. N. S. Sujitha

    2013-07-01

    Full Text Available —This paper proposes CMOS camera and USB device drivers implementation on S3C2440 using LINUX 2.6.32. The CMOS camera driver is used for video acquisition applications, which implements image-sensor technology and USB driver is used for data acquisition applications, establishes communication between host computer and a number of peripheral devices. OV9650 CMOS camera is implemented in linux 2.6.32, uses V4L2 protocol for complying. Similarly USB device in LINUX kernel uses struct urb structure to communicate with all USB devices

  20. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction.

    Science.gov (United States)

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-07-14

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

  1. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  2. Evaluation of sCMOS cameras for detection and localization of single Cy5 molecules.

    Science.gov (United States)

    Saurabh, Saumya; Maji, Suvrajit; Bruchez, Marcel P

    2012-03-26

    The ability to detect single molecules over the electronic noise requires high performance detector systems. Electron Multiplying Charge-Coupled Device (EMCCD) cameras have been employed successfully to image single molecules. Recently, scientific Complementary Metal Oxide Semiconductor (sCMOS) based cameras have been introduced with very low read noise at faster read out rates, smaller pixel sizes and a lower price compared to EMCCD cameras. In this study, we have compared the two technologies using two EMCCD and three sCMOS cameras to detect single Cy5 molecules. Our findings indicate that the sCMOS cameras perform similar to EMCCD cameras for detecting and localizing single Cy5 molecules.

  3. A new interpolating method based on the variation of spectra energy using CMOS array

    Institute of Scientific and Technical Information of China (English)

    Tianjin Tang; Xiangqun Cao; Hongqiu Chen; Bin Lin

    2005-01-01

    @@ A new interpolating method to enhance the resolution of gratings using complementary metal-oxide semiconductor (CMOS) according to the variation of some specified spectral light intensities during the motion of scale grating in a periodic separation is proposed. CMOS image sensor (pixel array 648 × 488) was also introduced as receiving device and its stability was verified experimentally. Many factors in the experiment were analyzed theoretically and contrasted with experiment. The advantages of this novel method were featured by CMOS and the specified spectral variation of the energy distribution was discussed.

  4. CMOS time-resolved, contact, and multispectral fluorescence imaging for DNA molecular diagnostics.

    Science.gov (United States)

    Guo, Nan; Cheung, Kawai; Wong, Hiu Tong; Ho, Derek

    2014-10-31

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  5. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Science.gov (United States)

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  6. Spectral_Engineering_with_CMOS_compatible_SOI_Photonic_Molecules

    CERN Document Server

    Barea, Luis A M; de Rezende, Guilherme F M; Frateschi, Newton C

    2013-01-01

    Photonic systems based on microring resonators have a fundamental constrain given by the strict relationship among free spectral range (FSR), total quality factor (QT) and resonator size, intrinsically making filter spacing, photonic lifetime and footprint interdependent. Here we break this paradigm employing CMOS compatible Silicon-on-Insulator (SOI) photonic molecules based on coupled multiple ring resonators. The resonance wavelengths and their respective linewidths are controlled by the hybridization of the quasi-orthogonal photonic states. We demonstrate photonic molecules with doublet and triplet resonances with spectral spliting only achievable with single rings orders of magnitude larger in foot print. Besides, these splitting are potentially controllable based on the coupling (bonds) between resonators. Finally, the spatial distribution of the hybrid states allows up to sevenfold QT enhancement.

  7. A 20 MHz CMOS reorder buffer for a superscalar microprocessor

    Science.gov (United States)

    Lenell, John; Wallace, Steve; Bagherzadeh, Nader

    1992-01-01

    Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

  8. CMOS APS detector characterization for quantitative X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Endrizzi, Marco, E-mail: m.endrizzi@ucl.ac.uk [Dipartimento di Fisica, Università di Siena, Via Roma 56, 53100 Siena (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy); Oliva, Piernicola [Dipartimento di Chimica e Farmacia, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Golosio, Bruno [Sezione di Matematica, Fisica e Ingegneria dell' Informazione, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Delogu, Pasquale [Dipartimento di Fisica “E. Fermi”, Università di Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy)

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11–30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  9. Small-Scale CMOS Pseudo SRAM Module Design

    Institute of Scientific and Technical Information of China (English)

    李昀; 刘振宇; 韩月秋

    2004-01-01

    An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.

  10. A photonics design tool for advanced CMOS nodes

    CERN Document Server

    Alloatti, Luca; Stojanovic, Vladimir; Popovic, Milos; Ram, Rajeev Jagga

    2015-01-01

    Recently, we have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigor that is embodied in the 10000 to 50000 design rules that these designs must comply within advanced CMOS manufacturing. Here, we present a photonic design automation (PDA) tool which allows automatic generation of layouts without design-rule violations. Our tool is written in SKILL, the native language of the mainstream electric design automation (EDA) software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. Removal of design-rule violations - based on Manhattan discretization, Boolean and sizing operations - occurs during data preparation from the initial photonic layers to the final mask...

  11. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    Directory of Open Access Journals (Sweden)

    Wei-Song Wang

    2010-03-01

    Full Text Available Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 ºpA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB.

  12. On Dynamic Range Limitations of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1999-01-01

    This paper is concerned with the dynamic range of continuous time CMOS current mode circuits. As a representative current mode device a class AB current conveyor is examined. First, the voltage input range of the high impedance Y input is investigated. Next, the current input range of the low...... impedance X input is investigated. It is compared to the thermal noise in the X to Z signal path in order to evaluate the dynamic range, and the dependencies of the dynamic range on the supply voltage and the transistor lay-out is derived, both for the situation where the conveyor is used over a narrow...... frequency band and for the situation where the conveyor is used over the full bandwidth achievable. Finally, the optimisation of the current input range is related to the distortion characteristics and it is pointed out that to a first order approximation the distortion is independent of the current range....

  13. New CMOS Compatible Platforms for Integrated Nonlinear Optical Signal Processing

    CERN Document Server

    Moss, D J

    2014-01-01

    Nonlinear photonic chips have succeeded in generating and processing signals all-optically with performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. This paper reviews some of the recent achievements in CMOS-compatible platforms for nonlinear optics, focusing on amorphous silicon and Hydex glass, highlighting their potential future impact as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  14. Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

    CERN Document Server

    Oliveira, João P

    2012-01-01

    This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC).  Experimental results are shown to validate the overall design technique. Provides the complete theoretical analysis, supported by electrical simulations, of the parametric amplification technique in both continuous time and discrete time domains; Describes the design flow of an ADC fully based on discrete-time parametric amplification in CMOS technology; Presents a high speed time-interleaved pipeline ADC, based on parametric MOS amplification techniques described, complementing theory discussed with experimental results.

  15. Design Of A 65 Nm Cmos Comparator With Hysteresis

    Directory of Open Access Journals (Sweden)

    Aleksandr Vasjanov

    2014-05-01

    Full Text Available The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC.

  16. Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

    Science.gov (United States)

    White, Mark; MacNeal, Kristen; Cooper, Mark

    2012-01-01

    NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

  17. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  18. An Approach for Self-Timed Synchronous CMOS Circuit Design

    Science.gov (United States)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  19. Single-donor ionization energies in a nanoscale CMOS channel.

    Science.gov (United States)

    Pierre, M; Wacquez, R; Jehl, X; Sanquer, M; Vinet, M; Cueto, O

    2010-02-01

    One consequence of the continued downward scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations in the number of these dopants are already a major issue in the microelectronics industry. Although single dopant signatures have been observed at low temperatures, the impact on transistor performance of a single dopant atom at room temperature is not well understood. Here, we show that a single arsenic dopant atom dramatically affects the off-state room-temperature behaviour of a short-channel field-effect transistor fabricated with standard microelectronics processes. The ionization energy of the dopant is measured to be much larger than it is in bulk, due to its proximity to the buried oxide, and this explains the large current below threshold and large variability in ultra-scaled transistors. The results also suggest a path to incorporating quantum functionalities into silicon CMOS devices through manipulation of single donor orbitals.

  20. Almost perfectly symmetric SWCNT-based CMOS devices and scaling.

    Science.gov (United States)

    Zhang, Zhiyong; Wang, Sheng; Wang, Zhenxing; Ding, Li; Pei, Tian; Hu, Zhudong; Liang, Xuelei; Chen, Qing; Li, Yan; Peng, Lian-Mao

    2009-11-24

    Symmetric n- and p-type field-effect transistors (FETs) have been fabricated on the same undoped single-walled carbon nanotube (SWCNT). The polarity of the FET is defined by controlled injection of electrons (n-type, via Sc electrodes) or holes (p-type, via Pd electrodes) into the SWCNT, instead of via chemically doping the SWCNT. The SWCNT-based FETs with different channel lengths show a clear trend of performance improvement for channel length scaling. Taking full advantage of the perfect symmetric band structure of the semiconductor SWCNT, a perfect SWCNT-based CMOS inverter is demonstrated, which gives a voltage gain of over 160, and for the two adjacent n- and p-type FETs fabricated on the same SWCNT, high field mobility is realized simultaneously for electrons (3000 cm(2)/V.s) and holes (3300 cm(2)/V.s).

  1. An improved equivalent simulation model for CMOS integrated Hall plates.

    Science.gov (United States)

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model's simulation results are in good agreement with the classic experimental results reported in the literature.

  2. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    Directory of Open Access Journals (Sweden)

    Yue Xu

    2011-06-01

    Full Text Available An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

  3. Radiation hardness studies on CMOS monolithic pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Battaglia, Marco [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Bisello, Dario [Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Contarato, Devis, E-mail: DContarato@lbl.go [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Denes, Peter; Doering, Dionisio [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Giubilato, Piero [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Sung Kim, Tae [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Mattiazzo, Serena [Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Radmilovic, Velimir [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Zalusky, Sarah [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States)

    2010-12-11

    This paper presents irradiation studies performed on a CMOS monolithic pixel sensor prototype implementing different optimizations of the pixel cell aimed at a superior radiation tolerance. Irradiations with 200 keV electrons up to a total dose of 1.1 Mrad have been performed in view of the utilization of such a design in Transmission Electron Microscopy (TEM) applications. Comparative irradiations were performed with 29 MeV protons up to a 2 Mrad total dose and with 1-14 MeV neutrons up to fluences in excess of 10{sup 13} n{sub eq} cm{sup -2}. Experimental results show an improved performance of pixels designed with Enclosed Layout Transistor (ELT) rules and an optimized layout of the charge collecting diodes.

  4. An inductorless CMOS realization of Chua's circuit

    Energy Technology Data Exchange (ETDEWEB)

    Radwan, Ahmed G.; Soliman, Ahmed M.; El-Sedeek, Abdel-Latif

    2003-09-01

    In this paper, an inductorless CMOS realization of Chua's circuit [IEEE Trans. Circ. Syst.--I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua's circuit and can generate Rossler or double-scroll attractors by changing a single capacitor's value. Variables are represented in the current domain to facilitate adding or subtracting variables. New G{sub m}-C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as {+-}1.5 V. Transistor-level simulation results using PSpice in 0.5 {mu}m Mietec process are presented.

  5. State assignment approach to asynchronous CMOS circuit design

    Science.gov (United States)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  6. A CMOS single-supply logarithmic amplifier for hearing aids

    Science.gov (United States)

    Jarng, Soon Suck; Chen, Lingfeng; Kwon, You Jung

    2005-12-01

    The Log Amplifier described in this paper is designed for hearing aids (HA) application. It works on a low single-supply voltage (1.3V). The input signal varies between 0.01mV and 100mV. To give enough compensation to the hearing impairment, the amplifier provides a very large gain. The output swing is limited because of the low supply voltage and the large gain. Therefore, the logarithmic amplifier introduced into the design of HA to compress input signal so that the output distortion can be avoid. Another factor we use it here is that the amplifier has enough sensitivity and gain to deal with the compressed input signal without getting extra distortion coursed by the pre-process on input signal. The short channel CMOS devices play an important role in reduction of the supply voltage. DONG-BU ANAM 0.18 μm process is selected.

  7. Design of a CMOS multi-mode GNSS receiver VCO

    Institute of Scientific and Technical Information of China (English)

    Long Qiang; Zhuang Yiqi; Yin Yue; Li Zhenrong

    2012-01-01

    A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multimode global navigation satellite system (GNSS) application,which adopts sigma-delta fractional-N technology in the synthesizer,is presented.The structure is selected to optimize the frequency coverage and tuning linearity,based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells,which cover the global positioning system (GPS) and Beidou (BD) bands.The VCO implemented in the 0.18 μm CMOS process can cover the GPS L1,BD B1,B2 and B3 bands with sufficient margin,and exhibits low phase noise by using this tuning curve linearization technique.The equalized Kvco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

  8. Voltage-to-frequency converters CMOS design and implementation

    CERN Document Server

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  9. Measurements of Si Hybrid CMOS X-Ray Detector Characteristics

    CERN Document Server

    Bongiorno, Stephen D; Burrows, David N; Cook, Robert; Bai, Yibin; Farris, Mark

    2009-01-01

    The development of Hybrid CMOS Detectors (HCDs) for X-Ray telescope focal planes will place them in con- tention with CCDs on future satellite missions due to their faster frame rates, flexible readout scenarios, lower power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However their bucket-brigade read-out architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels with low power, on-chip multiplexer electronics in a random access fashion. Faster frame rates achieved with multi-output readout design will allow the next generation's larger effective area telescopes to observe bright sources free of pileup. Radiation damaged latt...

  10. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis.

    Science.gov (United States)

    Hageman, Kristin N; Kalayjian, Zaven K; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A; Fridman, Gene Y; Dai, Chenkai; Pouliquen, Philippe O; Georgiou, Julio; Della Santina, Charles C; Andreou, Andreas G

    2016-04-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 °/s for the MVP2 and 2.0-14.2 °/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2.

  11. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  12. Spatially Resolved Spectroscopy Across HD189733 (K1V) Using Exoplanet Transits

    Science.gov (United States)

    Gustavsson, Martin; Dravins, Dainis; Ludwig, Hans-Günter

    2016-06-01

    For testing 3-dimensional models of stellar atmospheres, spectroscopy across spatially resolved stellar surfaces would be desired with a spectral resolution of(R = 100,000) or more. Hydrodynamic models predict variations in line profile shapes, strengths, wavelength positions and asymmetries. These variations vary systematically between disk center and limb and as a function of line strength, excitation potential and wavelength region. However, except for a few supergiants and the Sun, current telescopes are not yet capable of resolving any stellar surfaces. One alternative method to resolve distant stellar surfaces, feasible already now, is differential spectroscopy of transiting exoplanet systems. By subtracting in-transit spectra from the spectrum outside of transit, the spectra from stellar surface portions temporarily hidden behind the planet can be disentangled. Since transiting planets cover only a small portion of the stellar surface, the method requires a very high signal-to-noise ratio, obtainable by averaging numerous similar spectral lines. We apply such differential spectroscopy on the 7.7 mag K1V star HD 189733 ('Alopex'*); its transiting planet covers ˜ 3% of its host star's surface, which is the deepest known transit among the brighter systems. Archival data from the ESO HARPS spectrometerare used to construct averaged profiles of photospheric Fe I lines, with the aim of comparing spatially resolved profiles to analogous synthetic line profiles computed from the 3-dimensional hydrodynamic CO5BOLD model. * We refer to HD 189733 as 'Alopex' (from the Greek 'αλɛπού'), denoting a fox related to the one that gave name to its constellation of Vulpecula.

  13. Development of radiation hard CMOS active pixel sensors for HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Pernegger, Heinz, E-mail: heinz.pernegger@cern.ch

    2016-07-11

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  14. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  15. Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

    Science.gov (United States)

    Li-Shu, Wu; Yan, Zhao; Hong-Chang, Shen; You-Tao, Zhang; Tang-Sheng, Chen

    2016-06-01

    In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal-oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits.

  16. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

    Institute of Scientific and Technical Information of China (English)

    Li Chen; Liao Huai-Lin; Huang Ru; Wang Yang-Yuan

    2008-01-01

    In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.

  17. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II SBIR project a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at sub 1 micro-g levels...

  18. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This Phase I SBIR effort initiates development of a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at...

  19. An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier

    Science.gov (United States)

    Abdalla, M. A.; Fröjdh, C.; Petersson, C. S.

    2001-06-01

    We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32×80 element CMOS active pixel array was implemented in a 0.8 μm CMOS double poly, n-well process with a pixel pitch of 50 μm. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

  20. CMOS color image sensor with overlaid organic photoconductive layers having narrow absorption band

    Science.gov (United States)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi; Komatsu, Takashi; Saito, Takahiro

    2007-02-01

    At EI2006, we proposed the CMOS image sensor, which was overlaid with organic photoconductive layers in order to incorporate in it large light-capturing ability of a color film owing to its multiple-layer structure, and demonstrated the pictures taken by the trial product of the proposed CMOS image sensor overlaid with an organic layer having green sensitivity. In this study, we have tried to get the optimized spectral sensitivity for the proposed CMOS image sensor by means of the simulation to minimize the color difference between the original Macbeth chart and its reproduction with the spectral sensitivity of the sensor as a parameter. As a result, it has been confirmed that the proposed CMOS image sensor with multiple-layer structure possesses high potential capability in terms of imagecapturing efficiency when it is provided with the optimized spectral sensitivity.

  1. Pandemic A/H1N1v influenza 2009 in hospitalized children: a multicenter Belgian survey

    Directory of Open Access Journals (Sweden)

    Blumental Sophie

    2011-11-01

    Full Text Available Abstract Background During the 2009 influenza A/H1N1v pandemic, children were identified as a specific "at risk" group. We conducted a multicentric study to describe pattern of influenza A/H1N1v infection among hospitalized children in Brussels, Belgium. Methods From July 1, 2009, to January 31, 2010, we collected epidemiological and clinical data of all proven (positive H1N1v PCR and probable (positive influenza A antigen or culture pediatric cases of influenza A/H1N1v infections, hospitalized in four tertiary centers. Results During the epidemic period, an excess of 18% of pediatric outpatients and emergency department visits was registered. 215 children were hospitalized with proven/probable influenza A/H1N1v infection. Median age was 31 months. 47% had ≥ 1 comorbid conditions. Febrile respiratory illness was the most common presentation. 36% presented with initial gastrointestinal symptoms and 10% with neurological manifestations. 34% had pneumonia. Only 24% of the patients received oseltamivir but 57% received antibiotics. 10% of children were admitted to PICU, seven of whom with ARDS. Case fatality-rate was 5/215 (2%, concerning only children suffering from chronic neurological disorders. Children over 2 years of age showed a higher propensity to be admitted to PICU (16% vs 1%, p = 0.002 and a higher mortality rate (4% vs 0%, p = 0.06. Infants less than 3 months old showed a milder course of infection, with few respiratory and neurological complications. Conclusion Although influenza A/H1N1v infections were generally self-limited, pediatric burden of disease was significant. Compared to other countries experiencing different health care systems, our Belgian cohort was younger and received less frequently antiviral therapy; disease course and mortality were however similar.

  2. CMOS 射频低噪声放大器的设计%Design of CMOS RF LNA

    Institute of Scientific and Technical Information of China (English)

    王磊; 余宁梅

    2005-01-01

    讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法.在此基础上,采用SMIC 0.25 μm CMOS工艺库,给出了3.8 GHz CMOS LNA的设计方案.HSPICE仿真结果表明:电路的功率增益为13.48dB,输入、输出匹配良好,噪声系数为2.9dB,功耗为46.41 mw.

  3. NEMS/CMOS sensor for monitoring deposition rates in stencil lithography

    OpenAIRE

    Sansa, Marc; Arcamone, Julien; Verd, Jaume; Uranga, Arantxa; Abadal, Gabriel; Núria, Barniol; Savu, Veronica; van den Boogaart, Marc; Brugger, Jürgen; Perez-Murano, Francesc

    2009-01-01

    A nanoelectromechanical mass sensor is used to characterize material deposition rates in stencil lithography. The material flux through micron size apertures is mapped with high spatial (below 1 μm) and deposition rate (below 10 pm/s) resolutions by displacing the stencil apertures over the sensor. The sensor is based on a resonating metallic beam (with submicron size width and thickness) monolithically integrated with a CMOS circuit, resulting in a CMOS/NEMS self-oscillator. The sensor is us...

  4. Design and test challenges in Nano-scale analog and mixed CMOS technology

    OpenAIRE

    2011-01-01

    The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS)technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. ...

  5. Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

    Science.gov (United States)

    Bennett, K.; Lala, P. K.; Busaba, F.

    1997-01-01

    Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

  6. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    OpenAIRE

    S. M. Rezaul Hasan; Yufridin Wahab

    2002-01-01

    This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without a...

  7. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  8. Analog CMOS circuit design and characterization for optical coherence tomography signal processing.

    Science.gov (United States)

    Kariya, Rajesh; Mathine, David L; Barton, Jennifer K

    2004-12-01

    We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 microm low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.

  9. e2v CCD and CMOS sensors and systems designed for astronomical applications

    Science.gov (United States)

    Jorden, Paul; Jerram, Paul; Jordan, Douglas; Pratlong, Jérôme; Robbins, Mark

    2016-08-01

    e2v continues to evolve its product range of sensors and systems, with CCD and CMOS sensors. We describe recent developments of high performance image sensors and precision system components. Several low noise backthinned CMOS sensors have been developed for scientific applications. CCDs have become larger whilst retaining very low noise and high quantum efficiency. Examples of sensors and sub-systems are presented including the recently completed 1.2 GigaPixel J-PAS cryogenic camera.

  10. Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability

    OpenAIRE

    2001-01-01

    Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy dis...

  11. A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes

    Institute of Scientific and Technical Information of China (English)

    CHENG YuHua

    2008-01-01

    This paper overviews design for manufacturing (DFM) for IC design in nano-CMOS technologies. Process/device issues relevant to the manufacturability of ICs in advanced CMOS technologies will be presented first before an exploration on process/device modeling for DFM is done. The discussion also covers a brief in-troduction of DFM-aware of design flow and EDA efforts to better handle the design-manufacturing interface in very large scale IC design environment.

  12. Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

    OpenAIRE

    2012-01-01

    Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables t...

  13. Noise in Large-Signal, Time-Varying RF CMOS Circuits: Theory & Design

    OpenAIRE

    Murphy, David Patrick

    2012-01-01

    RF CMOS design is now a mature field and CMOS radio transceivers have become standard in most consumer wireless devices. Like any wireless RF design, at the heart of the endeavor is the requirement to frequency translate signals between baseband and RF with minimal introduction of noise and distortion. This translation is generally accomplished using time-varying, strongly nonlinear circuits, whose operation and noise performance cannot be understood using standard LTI circuit analysis techni...

  14. A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration

    OpenAIRE

    Chun-Chi Chen; Yi Lin

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel tem...

  15. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    CERN Document Server

    Benoit, M; de Mendizabal, J. Bilbao; Chen, H; Chen, K; Di Bello, F.A; Ferrere, D; Golling, T; Gonzalez-Sevilla, S; Iacobucci, G; Lanni, F; Liu, H; Meng, L; Miucci, A; Muenstermann, D; Nessi, M; Peric, I; Rimoldi, M; Ristic, B; Pinto, M. Vicente Barrero; Vossebeld, J; Weber, M; Wu, W; Xu, L

    2016-01-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  16. Low-Frequency-Noise Reduction Technique for Linear Analog CMOS IC's

    OpenAIRE

    Koh, Jeongwook

    2007-01-01

    For AMS (analog-mixed signal) and RF (radio frequency) implementations CMOS (Complementary Metal Oxide Semiconductor) technology platforms are the mainstream today. These platforms provide great density and power savings on digital parts on the same chip and, in addition, a good mix of components for analog design. The analog performance of CMOS technology is worse compared to other technology options (e.g. bipolar technology), and its major advantage is the lower total cost of system. Severa...

  17. A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance

    DEFF Research Database (Denmark)

    Andreani, Pietro; Fard, Ali

    2006-01-01

    The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3mum CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V...

  18. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    Energy Technology Data Exchange (ETDEWEB)

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  19. CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

    Science.gov (United States)

    de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

    2008-05-01

    CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

  20. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    Science.gov (United States)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-02-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.