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Sample records for 1-v 90-nm cmos

  1. Record RF performance of standard 90 nm CMOS technology

    OpenAIRE

    Tiemeijer, L.F.; Havens, R.J.; Kort, de, YAW Yvonne; Scholten, A.J.; Langevelde, van, H.J.; Klaassen, D.B.M.; Sasse, G.T.; Bouttement, Y.; Petot, C.; Bardy, S.; Gloria, D.; Scheer, P.; Boret, S.; Haaren, van, M.; Clement, C.

    2005-01-01

    We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

  2. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    International Nuclear Information System (INIS)

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported

  3. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    CERN Document Server

    Rivetti, A; Wyss, J; Bisello, D; Costa, M; Kloukinas, K; Demaria, N; Pantano, D; Rousset, J; Battaglia, M; Mansuy, C; Potenza, A; Ikemoto, Y; Giubilato, P; Chalmet, P; Mugnier, H; Silvestrin, L; Marchioro, A

    2013-01-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Omega cm, which is at least one order of magnitude greater than the typical value (1-10 Omega cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. (C) 2013 Elsevier B.V. All rights reserved

  4. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    Science.gov (United States)

    Wenwei, He; Qiao, Meng; Yi, Zhang; Kai, Tang

    2014-08-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity LSB and an integral nonlinearity LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.

  5. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    Science.gov (United States)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  6. 10-bit segmented current steering DAC in 90nm CMOS technology

    Science.gov (United States)

    Bringas, R., Jr.; Dy, F.; Gerasta, O. J.

    2015-06-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

  7. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  8. A 90 nm CMOS, 6 μW Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection

    OpenAIRE

    Badami, Komail; Lauwereins, Steven; Meert, Wannes; Verhelst, Marian

    2016-01-01

    This work presents a sub-6 µW acoustic front-end for speech/non-speech classification in a voice activity detection (VAD) in 90 nm CMOS. Power consumption of the VAD system is minimized by architectural design around a new Power-Proportional sensing paradigm and the use of machine-learning assisted moderate-precision analog analytics for classification. Power-Proportional sensing allows for hierarchical and context-aware scaling of the frontend’s power consumption depending on the complexity ...

  9. The temperature dependence of single-event transients in 90-nm CMOS dual-well and triple-well NMOSFETs

    Institute of Scientific and Technical Information of China (English)

    Li Da-Wei; Qin Jun-Rui; Chen Shu-Ming

    2013-01-01

    This paper investigates the temperature dependence of single-event transients (SETs) in 90-nm complementary metat-oxide semiconductor (CMOS) dual-well and triple-well negative metal-oxide semiconductor field-effect transistors (NMOSFETs).Technology computer-aided design (TCAD) three-dimensional (3D) simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55 ℃C to 125 ℃C,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.

  10. Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

    Science.gov (United States)

    Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

    2012-01-01

    Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

  11. Impact of STI Depth on Charge Sharing in 90nm CMOS Technology%90纳米CMOS双阱工艺下STI深度对电荷共享的影响

    Institute of Scientific and Technical Information of China (English)

    刘衡竹; 刘凡宇; 刘必慰; 梁斌

    2011-01-01

    基于3维TCAD器件模拟,研究了90nm CMOS双阱工艺下STI对电荷共享的影响.研究结果表明:增大STI深度能有效抑制NMOS电荷共享,且550nm为抑制电荷共享的有效深度,超过这个深度收集的电荷量几乎保持不变;而对于PMOS,STI深度的增加使电荷共享线性减小.这对于电荷共享加固具有重要指导意义.%THe dependence of various STI depths on charge sharing in 90nm dual well CMOS technology was investigated. TCAD simulation results show that increasing STI can restrain charge sharing of NMOS effectively, and 550nm is the effective depth for the prevention of charge diffusion, beyond which the collected charge almost keeps constant; for PMOS, charge sharing decreases linearly with the increment of STI depth. This conclusion is useful for irradiation-hardness.

  12. A 1V Phase Frequency Detector (PFD) with 180nm CMOS Technology

    OpenAIRE

    N . K . Kaphungkui

    2013-01-01

    In this paper, designing of a Phase frequency detector with 180nm CMOS technology is presented. The main objective of the designed circuit is to reduce the power dissipation with a low voltage supply of 1V. Phase frequency detector has a wide range of applications but one of the main application is in modern day phased locked loop, it serve as a main building block. PFD (Phase Frequency Detector) is a circuit that measures the phase and frequency difference between two signals, and has two ou...

  13. A sub-1 V high-precision CMOS bandgap voltage reference

    Institute of Scientific and Technical Information of China (English)

    廖峻; 赵毅强; 耿俊峰

    2012-01-01

    A third-order,sub-1 V bandgap voltage reference design for low-power supply,high-precision applications is presented.This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation.The circuit was designed and fabricated by SMIC 0.18μm CMOS technology.It produces an output reference of 713.6 mV.The temperature coefficient is 3.235 pprn/℃ in the temperature range of-40 to 120 ℃,with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V.The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.

  14. 25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

    Science.gov (United States)

    Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-10-10

    We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint. PMID:21997052

  15. A 1V Phase Frequency Detector (PFD with 180nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    N . K . Kaphungkui

    2013-02-01

    Full Text Available In this paper, designing of a Phase frequency detector with 180nm CMOS technology is presented. The main objective of the designed circuit is to reduce the power dissipation with a low voltage supply of 1V. Phase frequency detector has a wide range of applications but one of the main application is in modern day phased locked loop, it serve as a main building block. PFD (Phase Frequency Detector is a circuit that measures the phase and frequency difference between two signals, and has two outputs UP and DOWN which are signalled according to the phase and frequency difference of the two input signals. The designed circuit shows a satisfactory result with the low supply voltage. The detection of phase difference occurs only at the rising edge of the two clock signal. The total power dissipation from the circuit is only 3.88uW which is considerably low. In the field of IC design power dissipation of the circuit is always an important factor. The lower the power dissipation the longer the service time of the battery powered electronics circuit

  16. Designing to win in sub-90nm mask production

    Science.gov (United States)

    Zhang, Yuan

    2005-11-01

    An informal survey conducted with key customers by Photronics indicates that the time gap between technology nodes has accelerated in recent years. Previously the cycle was three years. However, between 130nm and 90nm there was less than a 2 year gap, and between 90nm and 65nm a 1.5 year gap exists. As a result, the technical challenges have increased substantially. In addition, mask costs are rising exponentially due to high capital equipment cost, a shrinking customer base, long write times and increased applications of 193nm EAPSM or AAPSM. Collaboration among EDA companies, mask houses and wafer manufacturers is now more important than ever. This paper will explore avenues for reducing mask costs, mainly in the areas of: write-time reduction through design for manufacturing (DFM), and yield improvement through specification relaxation. Our study conducted through layout vertex modeling suggests that a simple design shape such as a square versus a circle or an angled structure helps reduce shot count and write time. Shot count reduction through mask layout optimization, and advancement in new generation E-beam writers can reduce write time up to 65%. An advanced laser writer can produce those less critical E-beam layers in less than half the time of an e-beam writer. Additionally, the emerging imprint lithography brings new life and new challenges to the photomask industry with applications in many fields outside of the semiconductor industry. As immersion lithography is introduced for 45nm device production, polarization and MEEF effects due to the mask will become severe. Larger magnification not only provides benefits on CD control and MEEF, but also extends the life time of current 90nm/65nm tool sets where 45nm mask sets can be produced at a lower cost.

  17. A low power 20 GHz comparator in 90 nm COMS technology

    International Nuclear Information System (INIS)

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications. (semiconductor integrated circuits)

  18. A low power 20 GHz comparator in 90 nm COMS technology

    Science.gov (United States)

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

    2014-05-01

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

  19. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

    Science.gov (United States)

    Mingyuan, Yu; Ting, Li; Jiaqi, Yang; Shuangshuang, Zhang; Fujiang, Lin; Lin, He

    2016-07-01

    This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

  20. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    Science.gov (United States)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  1. Specifications and methodologies for benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node and beyond

    Science.gov (United States)

    Bunday, Benjamin D.; Bishop, Michael

    2003-05-01

    In this work, an extremely flexible and simple dissolution rate monitor (DRM) based on inexpensive, commercially available, PC card spectrometers has been built that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoreist films. The hardware required in order to construct such a simple apparatus has been discussed along with various experimental configurations that are appropriate for different measurement tasks. A multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single wavelength and multiwavelength DRM data analysis. The multiwavelength DRM and MIDAS software have been found to be very useful in analyzing a variety of resist film dissolution phenomena including monitoring films possessing dissolution rates exceeding 100 nm/s and studying resist film surface inhibition/acceleration. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. The basic approaches and algorithms used for thin film thickness and dissolution rate determination in the MIDAS software are discussed in this paper. Results from the use of the MIDAS software in various applications are presented.

  2. Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE

    OpenAIRE

    Johansson, Mattias; Ehrs, Jonas

    2010-01-01

    The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator. A current mode envelope...

  3. FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

    Science.gov (United States)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Ho, Jonathan; Wu, Xin; Panaite, Petrisor; Chacko, Manoj; Zhang, Yunqiang; Lei, Wen-Kang

    2005-11-01

    In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  4. Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

    Science.gov (United States)

    Cantu, Pietro; Capetti, Gianfranco; Loi, Sara; Lupo, Marco; Pepe, Annalisa; Saitoh, Kenji; Yamazoe, Kenji; Hasegawa, Yasuo; Iwasa, Junji; Toublan, Olivier R.

    2004-05-01

    According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

  5. Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology

    OpenAIRE

    Sarafianos, Alexandre; Gagliano, Olivier; Serradeil, Valérie; Lisart, Mathieu; DUTERTRE, Jean-Max; Tria, Assia

    2013-01-01

    International audience; This paper presents measurements of pulsed photoelectrical laser stimulation of an NMOS transistor in 90nm technology. The laser power was able to trig the NPN parasitic bipolar Drain/Psubstrate/Source. An electrical model is proposed in order to simulate effects induced by the laser. Results extracted from the electrical simulator are compared to measurements.

  6. DOE experiment for scattering bars optimization at the 90nm node

    Science.gov (United States)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  7. Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications

    OpenAIRE

    Srinivasan, R; Bhat, Navakanta

    2005-01-01

    In this paper, we have studied and compared the RF performance metrics, unity gain frequency $(f_t)$ and Noise Figure (NF), of the devices with channel engineering consisting of halo and super steep retrograde channel (SSRC) implants, and the devices with uniform channel doping concentration, using process, device, and mixed mode simulations. The simulation results show that at 90nm gate lengths, for a given off-state leakage constraint $(I_O_F_F)$, devices with uniform channel doping conc...

  8. ESD protection device and circuit design for advanced CMOS technologies

    CERN Document Server

    Semenov, Oleg; Sachdev, Manoj

    2008-01-01

    Strategies for design-oriented ESD protectionDistributed ESD protection networks optimized for sub-90nm CMOS ICsESD protection strategies for smart power ICs used in automotive industryThe impact of burn-in testing (accelerated test methods) on the ESD robustnessThe charge board ESD (CBM) testing used for wireless products

  9. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    Science.gov (United States)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  10. High precision CMOS clock duty-cycle corrector%高精度CMOS时钟占空比纠正器的设计

    Institute of Scientific and Technical Information of China (English)

    孙烨辉; 高静

    2013-01-01

    设计并实现了一种使用90nm CMOS工艺制造的高精度CMOS占空比纠正器.它的核心电路工作电压为1V,最高工作频率为10GHz.占空比纠正器负责对高速数字电路中的时钟占空比进行纠正,以减小占空比失真造成的确定性抖动.设计利用差分电荷泵方式完成对时钟占空比信息的提取,然后通过闭环负反馈环路来完成失真纠正工作.仿真结果表明,占空比纠正精度非常高,占空比剩余误差在1%以内.%A CMOS clock duty-cycle correction circuit with high precision is described.The circuit is implemented in 90nm CMOS process and power supply voltage is 1V.The maximum frequency is 10GHz.The duty-cycle corrector is used to correct the duty-cycle of the clock to reduce the deterministic jitter introduced by the duty-cycle distortion.The circuits extract the duty-cycle information by differential charge pump and correct the clock distortion by a negative feedback loop.The simulation result shows that the residual error of the duty-cycle distortion is within 1%.

  11. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  12. Optimization of building blocks for multi-stage 17-44 dB 6.1-9.6 mW 90-nm K-band front-ends

    Science.gov (United States)

    Roy, Apratim; Harun Rashid, A.

    2013-12-01

    In this article, five two-stage ˜6-mW and four three-stage ˜9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains building blocks in twostage low-power (6.1-6.6 mW) amplifiers achieve linearity (IIP3) in the range of -5.2˜-13.5 dBm, good reverse isolation (better than -26 dB), 2.89-3.82 dB noise penalties, and 17.2-25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2-9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve -2.5˜18.3 dBm IIP3, <-39 dB reverse isolation, and <-17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

  13. Hot-carrier degradation for 90 nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

    Institute of Scientific and Technical Information of China (English)

    Chen Hai-Feng; Hao Yue; Ma Xiao-Hua; Li Kang; Ni Jin-Yu

    2007-01-01

    The hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide under the low gate voltage (LGV) (at Vg=Vth,where Vth is the threshold voltage) stress has been investigated.It is found that the drain current decreases and the threshold voltage increases after the LGV (Vg=Yth) stress.The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress.By analysing the gate-induced drain leakage (GIDL) current before and after stresses,it is confirmed that under the LGV stress in uItra-short gate LDD-NMOSFET with ultra-thin gate oxide,the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do.which leads to the different degradation phenomena from those of the conventional NMOS devices.This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Vg=Vth with various drain biases.Experimental results show that the degradation slopes(n) range from 0.21 to 0.41.The value of n is less than that of conventional MOSFET(0.5-0.6) and also that of the long gate length LDD MOSFET (~0.8).

  14. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, wh...

  15. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  16. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

    International Nuclear Information System (INIS)

    Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from −354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply. (semiconductor integrated circuits)

  17. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    OpenAIRE

    Chun-Chi Chen; Chao-Lieh Chen; Yi Lin

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point cal...

  18. CMOS Direct-Injection Divide-by-3 Injection-Locked Frequency Dividers

    Institute of Scientific and Technical Information of China (English)

    Chia-Wei; Chang; Jhin-Fang; Huang; Sheng-Lyang; Jang; Ying-Hsiang; Liao; Miin-Horng; Juang

    2010-01-01

    <正>This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.

  19. Design of Current steering DAC using 250nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Vineet Tiwari

    2012-06-01

    applied at the reference terminal. Analog to digital converter performs the reverse operation. It has many era of operations in audio and Video form and whiffletree electromagnetic device uses DAC linkage in typewriter. It describes the 3.3 volt, 65 MHz 8 bit CMOS digital to analog converter, includes two stage current cell matrix. This paper describes a 1v CMOS 8 bit DAC with two stage current cell matrix architecture which consists of 4 MSB and 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the no of high swing current mirrors. The designed DAC with a by 90 nm nwell CMOS standard process. The experiment is based on settling time, Integrity, or non linearity. The designed DAC is fully operational for power supply down to 1 volt such that DAC is suitable for low voltage and low power applications.

  20. A novel colour-sensitive CMOS detector

    Science.gov (United States)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  1. The modulation effect of substrate doping on multi-node charge collection and single-event transient propagation in 90-nm bulk complementary metal-oxidesemiconductor technology

    Institute of Scientific and Technical Information of China (English)

    Qin Jun-Rui; Chen Shu-Ming; Liu Bi-Wei; Liu Zheng; Liang Bin; Du Yan-Kang

    2011-01-01

    Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor (CMOS) technologies,which are significant for charge sharing,thus affecting the propagated single event transient pulsewidths in circuits.The trends of charge collected by the drain of a positive channel metal-oxide semiconductor (PMOS) and an N metal-oxide semiconductor (NMOS) are opposite as the substrate doping increases.The PMOS source will inject carriers after strike and the amount of charge injected will increase as the substrate doping increases,whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough.Additionally,it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current,and has little effect on the drift and diffusion.The change in substrate doping has a much greater effect on PMOS than on NMOS.

  2. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  3. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  4. Customized CMOS wavefront sensor

    OpenAIRE

    Monteiro, D. W. L.; Vdovin, G.; Rocha, J.G.; Iordanov, V.; Loktev, M.; Sarro, P.

    2002-01-01

    We report on an integrated Hartmann wavefront sensor (WFS) using passive-pixel architecture and pixels clustered as position-sensitive detectors for dynamic wavefront analysis. This approach substitutes a conventional imager, such as a CCD or CMOS imager, by a customized detector, thus improving the overall speed performance. CMOS (complementary-metal- oxide-semiconductor) technology enables on-chip integration of several analog and digital circuitry. The sensor performance depends on the fea...

  5. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  6. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  7. Main: 1V08 [RPSD[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V08 トウモロコシ Corn Zea mays L. Beta-Glucosidase, Chloroplast Precursor Name=Glu1; Zea...EGLKDLLMIMKNKYGNPPIYITENGIGDVDTKETPLPMEAALNDYKRLDYIQRHIATLKESIDLGSNVQGYFAWSLLDNFEWFAGFTERYGIVYVDRNNNCTRYMKESAKWLKEFNTAKKPSKKILTPA corn_1V08.jpg ...

  8. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  9. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  10. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  11. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    Science.gov (United States)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  12. Implantable CMOS Biomedical Devices

    Directory of Open Access Journals (Sweden)

    Toshihiko Noda

    2009-11-01

    Full Text Available The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

  13. Further developments on a novel color sensitive CMOS detector

    Science.gov (United States)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-05-01

    The Transverse Field Detector (TFD) is a recently proposed Silicon pixel device designed to perform color imaging without the use of color filters. The color detection principle is based on the dependence of the Silicon absorption coefficient from the wavelength and relies on the generation of a suitable transverse electric field configuration, within the semiconductor active layer, to drive photocarriers generated at different depths towards different collecting electrodes. Each electrode has in this way a different spectral response with respect to the incoming wavelength. Pixels with three or four different spectral responses can be implemented within ~ 6 μm of pixel dimension. Thanks to the compatibility with standard triple well CMOS processes, the TFD can be used in an Active Pixel Sensor exploiting a dedicated readout topology, based on a single transistor charge amplifier. The overall APS electronics includes five transistors (5T) and a feedback capacitance, with a resulting overall fill factor around 50%. In this work the three colors and four colors TFD pixel simulations and implementations in a 90 nm standard CMOS triple well technology are described. Details on the design of a TFD APS mini matrix are provided and preliminary experimental results on four colors pixels are presented.

  14. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  15. A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

    Institute of Scientific and Technical Information of China (English)

    Yang Jinda; Wang Xianbiao; Li Li; Cheng Xu; Guo Yawei; Zeng Xiaoyang

    2011-01-01

    A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13 μm CMOS technology.The contrast experimental resuits verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.

  16. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-07-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layoutsimulation results.

  17. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  18. 增强90nm以下节点应用的工艺控制适应性%Enhancing Process Control Flexibility for Sub-90 nm Applications

    Institute of Scientific and Technical Information of China (English)

    John Yamartino; Vivien Chang; James Holland; Andrey Poliektov

    2007-01-01

    器件尺寸正在对半导体加工工艺从多方面提出新的挑战.对于在90nm节点之后的应用,需要更大改进,且用适应性强的先进工艺来克服更大节点工艺中已得到验证的固有技术的限制.不仅基于先进工艺控制(APC)的下一代工艺设备能够得到来自一个以上信息来源的测量数据,而且将这些测量数据转换成为工艺控制参数以减少性能变化,下一代工艺设备必须提供生产线许多表明圆片经过工艺设备的整个控制程序特性.这种先进工艺控制系统将给予生产线高度理想的、适合先进工艺控制的适应能力需求,实现对其独特的生产线提供最大的优势.%Device scaling is posing new challenges for many aspects of semiconductor processing. More sophisticated and flexible advanced process controls (APC) are needed for sub-90-nm applications to overcome limitations inherent in techniques that have proven effective for larger nodes. Not only must next-generation process-tool-based APC systems be able to receive metrology data from more than one source and translate them into process-control parameters to reduce performance variations, they must provide the fab host with features for designating the entire process control sequence for wafers passing through the system. Such APC systems will give fabs the highly desirable versatility needed for tailoring APC implementation to best advantage for its particular production lines.

  19. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  20. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  1. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  2. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis descri...

  3. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  4. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  5. High-voltage CMOS detectors

    Science.gov (United States)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  6. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  7. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  8. A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

    Directory of Open Access Journals (Sweden)

    A. Oncu

    2015-04-01

    Full Text Available A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF. The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW.

  9. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    International Nuclear Information System (INIS)

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption

  10. Fabrication of CMOS image sensors

    Science.gov (United States)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  11. A Surface Micromachined CMOS MEMS Humidity Sensor

    OpenAIRE

    Jian-Qiu Huang; Fei Li; Min Zhao; Kai Wang

    2015-01-01

    This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. A...

  12. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  13. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  14. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  15. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  16. JFET-CMOS microstrip front-end

    International Nuclear Information System (INIS)

    While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper. (orig.)

  17. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  18. Main: 1V3H [RPSD[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V3H 大豆 Soybean Glycine max (L.) Merrill Beta-Amylase Name=Bmy1; Glycine Max Molecule: Beta-Amylase; Chai... 495 AA, Molecular weight: 56011 Da ATSDSNMLLNYVPVYVMLPLGVVNVDNVFEDPDGLKEQLLQLRAAGVDGVMVDVWWGIIELKGPKQYDWRAYRSLFQLVQECGLTLQAI...MSFHQCGGNVGDIVNIPIPQWVLDIGESNHDIFYTNRSGTRNKEYLTVGVDNEPIFHGRTAIEIYSDYMKSFRENMSDFLESGLIIDIEVG...FLTWYSNKLLNHGDQILDEANKAFLGCKVKLAIKVSGIHWWYKVENHAAELTAGYYNLNDRDGYRPIARMLSRHHAILNFTCLEMRDSEQPSDAKSGPQELVQQVLSG...GWREDIRVAGENALPRYDATAYNQIILNAKPQGVNNNGPPKLSMFGVTYLRLSDDLLQKSNFNIFKKFVLKMHADQDYCANPQKYNHAITPLKPSAPKIPIEVLLEATKPTLPFPWLPETDMKVDG soybean_1V3H.jpg ...

  19. Main: 1V3I [RPSD[Archive

    Lifescience Database Archive (English)

    Full Text Available 1V3I 大豆 Soybean Glycine max (L.) Merrill Beta-Amylase Name=Bmy1; Glycine Max Molecule: Beta-Amylase; Chai... 495 AA, Molecular weight: 56011 Da ATSDSNMLLNYVPVYVMLPLGVVNVDNVFEDPDGLKEQLLQLRAAGVDGVMVDVWWGIIELKGPKQYDWRAYRSLFQLVQECGLTLQAI...MSFHQCGGNVGDIVNIPIPQWVLDIGESNHDIFYTNRSGTRNKEYLTVGVDNEPIFHGRTAIEIYSDYMKSFRENMSDFLESGLIIDIEVG...FLTWYSNKLLNHGDQILDEANKAFLGCKVKLAIKVSGIHWWYKVENHAAELTAGYYNLNDRDGYRPIARMLSRHHAILNFTCLEMRDSEQPSDAKSGPQELVQQVLSG...GWREDIRVAGENALPRYDATAYNQIILNAKPQGVNNNGPPKLSMFGVTYLRLSDDLLQKSNFNIFKKFVLKMHADQDYCANPQKYNHAITPLKPSAPKIPIEVLLEATKPTLPFPWLPETDMKVDG soybean_1V3I.jpg ...

  20. Carbon Nanotube Integration with a CMOS Process

    Directory of Open Access Journals (Sweden)

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  1. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  2. Fully CMOS Memristor Based Chaotic Circuit

    Directory of Open Access Journals (Sweden)

    S. C. Yener

    2014-12-01

    Full Text Available This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.

  3. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    process scheme allows for post processing of feedthroughs in any kind of fully processed CMOS wafer. The fabrication of the electrical feedthroughs is based on wet etching of through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and feedthrough metal. The...... feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  4. Fully CMOS Memristor Based Chaotic Circuit

    OpenAIRE

    Yener, S. C.; H. H. Kuntman

    2014-01-01

    This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the succ...

  5. On evolution of CMOS image sensors

    OpenAIRE

    Choubey, Bhaskar; Gouveia, Luiz

    2014-01-01

    CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the...

  6. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    Science.gov (United States)

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  7. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  8. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  9. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr...... arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on...

  10. Characterization and reliability of CMOS microstructures

    Science.gov (United States)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  11. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  12. CMOS-compatible LVOF-based visible microspectrometer

    NARCIS (Netherlands)

    Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabricati

  13. Noise in sub-micron CMOS image sensors

    OpenAIRE

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  14. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Oleg Nizhnik; Kazusuke Maenaka; Kohei Higuchi

    2011-01-01

    A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  15. An RF (R) MS Power Detector in Standard CMOS

    NARCIS (Netherlands)

    Aa, van der F.H.J.

    2006-01-01

    This Master thesis describes the research towards the integration of RF power detectors for 3G cellular phones and base stations in CMOS technology1. It is a feasibility study with the emphasis on the identification of fundamental limitations of CMOS (particularly CMOS9) and of a number of squaring

  16. Scaling CMOS devices through alternative structures

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  17. Radiation-hardened bulk CMOS technology

    International Nuclear Information System (INIS)

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  18. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  19. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  20. Switched Transconductor Mixer Compatible with Future CMOS

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, Simon M.; Wienk, Gerard J.M.; Nauta, Bram

    2003-01-01

    Mixers are commonly used in communication systems for frequency translation, and usually exploit switching in some form to implement multiplication by a square wave. However, at the low supply voltages required for new CMOS technologies, switches are non- or poorly conducting in the "middle voltage

  1. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  2. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  3. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, E.A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    2001-01-01

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important transmissi

  4. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transisto

  5. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  6. Smart temperature sensors in standard CMOS

    NARCIS (Netherlands)

    Makinwa, K.A.A.

    2010-01-01

    A smart temperature sensor is an integrated system consisting of a temperature sensor, its bias circuitry and an analog-to-digital converter (ADC). When manufactured in CMOS technology, such sensors have found widespread use due to their low cost, small size and ease of use. In this paper the basic

  7. Low energy CMOS for space applications

    Science.gov (United States)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  8. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  9. Fully CMOS-compatible titanium nitride nanoantennas

    International Nuclear Information System (INIS)

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing

  10. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  11. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa−1 in the pressure range of 0–300 kPa. (paper)

  12. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  13. A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    Zhitang Song; YiPeng Zhan; Daolin Cai; Bo Liu; Yifeng Chen; Jiadong Ren

    2015-01-01

    In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

  14. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  15. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  16. IR CMOS: infrared enhanced silicon imaging

    Science.gov (United States)

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  17. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips. PMID:26654281

  18. Noise in a CMOS digital pixel sensor

    International Nuclear Information System (INIS)

    Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS. (semiconductor integrated circuits)

  19. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  20. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  1. Air Quality Monitoring Using CCD/ CMOS Devices

    OpenAIRE

    Low, Khee Lam; Joanna, Tan Choay Ee; Sim, Keat; Jafri, Mohd Zubir Mat; and, Khiruddin Abdullah

    2010-01-01

    In this chapter, we showed a method for measuring of the air quality index by using the CCD/CMOS sensor. We showed two examples to obtain index values by using webcam and CCTV. Both devices provided a high correlation between the measured and estimated PM10. So, the imaging method is capable to measure PM10 values in the environment. Futher application can be conducted using different devices.

  2. Cantilever-Based Biosensors in CMOS Technology

    CERN Document Server

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  3. A Light Source for Testing CMOS Imagers

    OpenAIRE

    Hancock, Jed J.; Baker, Doran

    2003-01-01

    Testing the optical properties of complementary metal oxide (CMOS) imagers requires a light source. The light source must produce stable uniform light with calibrated wavelength and intensity. Available commercial light source units are costly and often unalterable to a custom test setup. The proposed light source is designed to be affordable and adaptable while maintaining the necessary optical quality. The design consists of an array of light emitting diodes (LED), an infrared (IR) cut-off ...

  4. CMOS Camera Array With Onboard Memory

    Science.gov (United States)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  5. CMOS-controlled rapidly tunable photodetectors

    Science.gov (United States)

    Chen, Ray

    With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

  6. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  7. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

    OpenAIRE

    Wang, Bindi; Liu, Yao-Hong; Harpe, Pieter; Staszewski, Robert Bogdan; et al.

    2015-01-01

    In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measu...

  8. A Standard CMOS Humidity Sensor without Post-Processing

    Directory of Open Access Journals (Sweden)

    Oleg Nizhnik

    2011-06-01

    Full Text Available A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  9. Interferometric comparison of the performance of a CMOS and sCMOS detector

    Science.gov (United States)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  10. On-chip solar battery structure for CMOS LSI

    OpenAIRE

    Arima, Yutaka; Ehara, Masaya

    2006-01-01

    A built-in method of on-chip solar battery in a CMOS LSI is proposed. The proposed solar battery can be formed using conventional CMOS process technology. It can generate a high voltage of 0.6-0.83 V by a series connection structure of two types of p-n junction diodes formed with the CMOS circuit simultaneously on the LSI chip. The generated voltage is sufficient to drive the conventional CMOS circuit without modi. cation. The test chip was produced experimentally using conventional 0.35 mu m...

  11. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T; Barbero, M; Degerli, Y; Godiot, S; Guilloux, F; Hemperek, T; Hirono, T; Krüger, H; Liu, J; Orsini, F; Pangaud, P; Rozanov, A; Wermes, N

    2016-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  12. Current-mode CMOS hybrid image sensor

    Science.gov (United States)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  13. Current Development of CMOS Image Sensors%CMOS 图像传感器的发展现状

    Institute of Scientific and Technical Information of China (English)

    王宝元; 吴三灵; 温波; 焦明纲; 周发明

    2000-01-01

    Aim To review the current development of CMOS image sensors. Methods The background, architecture and current development of CMOS image sensors is describled. The trade-offs between the CMOS image sensors and the CCD image sensors are put forword. Results The development tendency of CMOS image sensors is discussed. Conclusion The CMOS image sensor has the potential of a wide range of application.%目的 了解当前CMOS图像传感器的发展状况. 方法 详细介绍了图像传感器的历史背景、发展现状、像素单元的结构、工作原理以及 CMOS 图像传感器芯片的整体结构,并比较了 CMOS 图像传感器和 CCD 图像传感器的优、 缺点. 结果 指出了 CMOS 图像传感器发展趋势. 结论 CMOS 图像传感器具有美好的发展前途.

  14. High Efficiency 3-Phase Cmos Rectifier with Step Up and Regulated

    CERN Document Server

    Crebier, J -C; Raisigel, H; Deleage, O; Delamare, J; Cugat, O

    2008-01-01

    This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditioning. Reduced input voltage operation (down to 1V), high efficiency, and output voltage regulations are implemented, based on commercially available CMOS technology. Global design and system issues are detailed. The management of start-up sequences under self supplied conditions as well as output voltage regulations are specifically addressed. Simulation results, practical implementation and validation are presented. They are based on the association of three micro elements : a 3-phase micro-generator, a stand alone 3-phase AC to DC integrated rectifier, and an output voltage conditioner based on a commercially available IC.

  15. 0.18μm CMOS Low Voltage Power Amplifier For WSN Application

    Directory of Open Access Journals (Sweden)

    Wu Chenjian

    2013-08-01

    Full Text Available This paper presents the design of a Class A/B power amplifier (PA for 2.4-2.4835GHz Wireless Sensor Network (WSN system in 0.18μm CMOS technology. The PA adopts the single-stage differential structure and the output power of the PA can be controlled by switching the sizes of transistors. Seven different level of output power can be obtained through a three- bit control code. The tested results shows that the proposed PA achieves power added efficiency (PAE of 26.73% while delivering an output power of 6.35dBm at 1dB compression point. Its power gain is 15.87dB. With a low DC voltage supply of 1V, its power consumption is 15.3mW. The PA die size is 1070×610μm2.

  16. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-01-01

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

  17. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.;

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  18. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  19. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  20. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    OpenAIRE

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radiation and device physics amongst each other.

  1. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  2. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    NARCIS (Netherlands)

    R. Turchetta; A. Fant; P. Gasiorek; C. Esbrand; J.A. Griffiths; M.G. Metaxas; G.J. Royle; R. Speller; C. Venanzi; P.F. van der Stelt; H.G.C. Verheij; G. Li; S. Theodoridis; H. Georgiou; D. Cavouras; G. Hall; M. Noy; J. Jones; J. Leaver; D. Machin; S. Greenwood; M. Khaleeq; H. Schulerud; J.M. Østby; F. Triantis; A. Asimidis; D. Bolanakis; N. Manthos; R. Longo; A. Bergamaschi

    2007-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end app

  3. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    NARCIS (Netherlands)

    R. Turchetta; A. Fant; P. Gasiorek; C. Esbrand; J.A. Griffiths; M.G. Metaxas; G.J. Royle; R. Speller; C. Venanzi; P.F. van der Stelt; H.G.C. Verheij; G. Li; S. Theodoridis; H. Georgiou; D. Cavouras; G. Hall; M. Noy; J. Jones; J. Leaver; D. Machin; S. Greenwood; M. Khaleeq; H. Schulerud; J.M. Østby; F. Triantis; A. Asimidis; D. Bolanakis; N. Manthos; R. Longo; A. Bergamaschi

    2006-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end app

  4. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  5. Silicon Light Emitting Devices in CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    CHEN Hong-Da; LIU Hai-Jun; LIU Jin-Bin; GU Ming; HUANG Bei-Ju

    2007-01-01

    @@ Two silicon light emitting devices with different structures are realized in standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/cm2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm.

  6. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  7. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...... is obtained by varying the ca rrier concentration of th e transparent conducting oxide layer and exciting plasmonic resonance in the structure. The analysis shows that an extinction ratio of 46 dB/μm can be achieved at the telecommunication wavelength. Proposed structure is particularly convenient...

  8. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  9. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  10. A CMOS high speed imaging system design based on FPGA

    Science.gov (United States)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  11. Theoretical performance analysis for CMOS based high resolution detectors.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  12. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  13. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  14. Modulated CMOS camera for fluorescence lifetime microscopy.

    Science.gov (United States)

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  15. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  16. Data of evolutionary structure change: 1C3AB-1V4LC [Confc[Archive

    Lifescience Database Archive (English)

    Full Text Available uence>AWSGG--SDCIV > --EEEEEe> AT...>1V4L C 1V4LC NLYKQSSKKCYA ...> GGG EEE> ATOM 2895 CA ASN C 95 14.946 47.67...ence>SKTTD--NQWLS >E -- EEEEe> AT...dbChain>C 1V4LC LKKGTELRTWFN ture>EE EEEE

  17. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  18. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  19. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    OpenAIRE

    Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage...

  20. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  1. CMOS-compatible LVOF-based visible microspectrometer

    OpenAIRE

    Emadi, A.; Wu, H; De Graaf, G.; Wolffenbuttel, R F

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabrication of LVOF involves a process for fabrication of very small taper angles, ranging from 0.001° to 0.1°, in SiO2. These layers can be fabricated flexibly in a resist layer by just one lithography ste...

  2. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  3. CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors

    International Nuclear Information System (INIS)

    This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good performance in terms of spatial resolution, efficiency, radiation hardness have been demonstrated and work is now well under way to deliver the first MAPS-based vertex detectors

  4. CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors

    CERN Document Server

    Turchetta, R

    2006-01-01

    This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good performance in terms of spatial resolution, efficiency, radiation hardness have been demonstrated and work is now well under way to deliver the first MAPS-based vertex detectors.

  5. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  6. A 150-nA 13.4-ppm/deg. C switched-capacitor CMOS sub-bandgap voltage reference

    International Nuclear Information System (INIS)

    A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 0.35-μm 3.3-V/5-V dual gate mixed-signal CMOS process. The proposed circuit generates a precise sub-bandgap voltage of 1 V. The temperature coefficient of the output voltage is 13.4 ppm/deg. C with the temperature varying from -20 to 80 deg. C. The proposed circuit operates properly with the supply voltage down to 1.3 V, and consumes 150 nA at room temperature. The line regulation is 0.27%/V. The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB, respectively. The chip area is 0.2 mm2. (semiconductor integrated circuits)

  7. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise...... model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...

  8. Silicon light emitting device in CMOS technology

    Institute of Scientific and Technical Information of China (English)

    LIU Hai-jun; GU Ming; LIU Jin-bin; HUANG Bei-ju; CHEN Hong-da

    2007-01-01

    A novel silicon light emitting device was realized with standard 0.35 μ m 2P4M Mixed Mode/RF CMOS technology. The device functions in a reverse breakdown mode and can be turned on at 8.3 V and operated normally at a wide voltage range of 8.3 V-12.0 V. An output optical power of 13.6 nW was measured at the bias of 10 V and 100 mA, and the emitted light intensity was calculated to be more than 1 mW/cm2. The optical spectrum of the device is in the range of 500-820 nm.

  9. CMOS digital pixel sensors: technology and applications

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  10. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    Institute of Scientific and Technical Information of China (English)

    ZHANG Guo-An; ZHANG Dong-Wei; HE Jin; SU Yan-Mei; WANG Cheng; CHEN Qin; LIANG Hai-Lang; YE Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1T CMOS APS) architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus,the reset and selected transistors can be removed. In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

  11. System and Circuit Design Aspects for CMOS Wireless Handset Receivers

    DEFF Research Database (Denmark)

    Mikkelsen, Jan H.

    developments in CMOS technology are considered and the short-comings from an analog design perspective are evaluated. The lack of high quality passive devices, inductors in particular, is found to be one of the major obstacles in achieving a fully integrated RF design based on CMOS. Following this, an overview......The presented work deals with system and circuit design aspects for Complementary Metal Oxide Semiconductor (CMOS) implementations of wireless handset receivers. First, an overview, from a historic perspective, on the use of CMOS in cellular applications is provided. Based on this the tremendous...... Division Duplex) direct-conversion receiver (DCR). The wideband nature of the UMTS signal opens up for simple DC-offset cancellation schemes. In line of this the use of highpass filtering as a means to reduce the DC-offset is pursued using link simulations. To simplify receiver planning it is common...

  12. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  13. Depleted CMOS pixels for LHC proton-proton experiments

    Science.gov (United States)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  14. OLED-on-CMOS integration for optoelectronic sensor applications

    Science.gov (United States)

    Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Törker, Michael; Grillberger, Christiane; Amelung, Jörg

    2007-02-01

    Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

  15. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit solut...... poor performance compared to the bipolar designs, but CMOS has a potential for CFB op-amp design if more ingenious circuit configurations are applied...

  16. Delta Doping High Purity CCDs and CMOS for LSST

    Science.gov (United States)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  17. A Low Power Low Voltage High Performance CMOS Current Mirror

    OpenAIRE

    Sirish Rao,; Sampath Kumar V

    2015-01-01

    The current mirrors are one of the most important circuits in designing the analog and mixed-mode circuit. A low power and low voltage high-performance CMOS current mirror with optimized input and output resistance are presented in this paper. SPICE simulations confirm the high-performance CMOS current mirror with power supply close to the threshold voltage of the transistor. In this paper, for achieving the low input resistance and a very high output resistance, the combination o...

  18. High performances monolithic CMOS detectors for space applications

    OpenAIRE

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Vignon, Bruno; Magnan, Pierre; Farre, Jean; Corbière, Franck; Martin-Gonthier, Philippe

    2001-01-01

    During the last 10 years, research about CMOS image sensors (also called APS -Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level ofradiation tolerance... Many imag...

  19. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    D Contarato; J-M Bussat; P Denes; L Griender; T Kim; T Stezeberger; H Weiman; M Battaglia; B Hooberman; L Tompkins

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  20. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  1. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    OpenAIRE

    Fangming Deng; Yigang He; Chaolong Zhang; Wei Feng

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate ...

  2. Integrating security solutions to support nanoCMOS electronics research

    OpenAIRE

    Sinnott, R.O.; Bayliss, C.; T. Doherty; Martin, D.; Millar, C.; Stewart, G; Watt, J; A. Asenov; Roy, G.; S Roy; Davenhall, C.; Harbulot, B.; Jones, M

    2008-01-01

    The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative electronics research across multiple institutions in the UK with especially strong industrial and commercial involvement. Unlike other domains, the electronics industry is driven by the necessity of protecting the intellectual property of the data, designs and software associated with next generation...

  3. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  4. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  5. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  6. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  7. Low Power CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Sujata Pandey,

    2010-08-01

    Full Text Available Here, two new designs of CMOS digitally controlled oscillators (DCO for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and withtwo NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 - 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 - 700.2977] μW and [617.6616 -6 77.3996] μW respectively.

  8. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  9. CMOS absorbance detection system for capillary electrophoresis

    International Nuclear Information System (INIS)

    This paper presents a cost-effective portable photodetection system for capillary electrophoresis absorptiometry. By using a CMOS BDJ (buried double p-n junction) detector, a dual-wavelength method for absorbance measurement is implemented. This system includes associated electronics for low-noise pre-amplification and A/D conversion, followed by digital signal acquisition and processing. Two signal processing approaches are adopted to enhance the signal to noise ratio. One is variable time synchronous detection, which optimizes the sensitivity and measuring rate compared to a conventional synchronous detection technique. The other is a statistical approach based on principal component analysis, which allows optimal estimation of detected signal. This system has been designed and tested in capillary electrophoresis conditions. Its operation has been verified with performances comparable to those of a commercialized spectrophotometric system (HP-3D CE). With potential on-chip integration of associated electronics, it may be operated as an integrable detection module for microchip electrophoresis and other microanalysis systems

  10. NSC 800, 8-bit CMOS microprocessor

    Science.gov (United States)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  11. A CMOS readout circuit for microstrip detectors

    International Nuclear Information System (INIS)

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation

  12. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  13. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Orit Skorka

    2011-04-01

    Full Text Available Technologies to fabricate integrated circuits (IC with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  14. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  15. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  16. CMOS Cell Sensors for Point-of-Care Diagnostics

    Directory of Open Access Journals (Sweden)

    Haluk Kulah

    2012-07-01

    Full Text Available The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS. CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  17. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Liu, Wei; Kovalgin, Alexey Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  18. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  19. A 1.5V 120nW CMOS programmable monolithic reference generator for wireless implantable system.

    Science.gov (United States)

    Chang, Sun-Il; AlAshmouny, Khaled; Yoon, Euisik

    2011-01-01

    We implement and characterize a 1.5 V 120 nW CMOS programmable monolithic reference generator for wireless implantable system. The proposed generator is optimized to be tolerable for power supply variation in a small area with programmability to generate various reference voltages and currents. The measured power line sensitivity are 0.02 / 1.1%/V for voltage and current reference, respectively. This reference generator can operate for input voltage ranging from 1.5 V to 3.5 V and implemented in an area of 0.011 mm(2), which is the smallest monolithic reference generator in 0.25 μm technology to the best of our knowledge. The output can vary from 20 nA to 33 nA for current reference and from 0.71 V to 1.03 V for voltage reference. PMID:22254967

  20. A CMOS-compatible electronic synapse device based on Cu/SiO2/W programmable metallization cells

    Science.gov (United States)

    Chen, Wenhao; Fang, Runchen; Balaban, Mehmet B.; Yu, Weijie; Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

    2016-06-01

    In this work, the resistance plasticity of Cu/SiO2/W programmable metallization cell devices is experimentally explored for the emulation of biological synapses. PMC devices were fabricated with foundry friendly materials using standard processes. The resistance can be continuously increased or decreased with both dc and voltage pulse programming. Impedance spectroscopy results indicate that the gradual change of resistance is attributable to the expansion or contraction of a Cu-rich layer within the device. Pulse programming experiments further show that the pulse amplitude plays a more important role in resistance change than pulse width, which is consistent with the proposed ‘dual-layer’ device model. The dense resistance-state distribution, 1 V operating voltage and inherent CMOS-compatibility suggests its potential application as electronic synapse in neuromorphic computing.

  1. Microinjection of antisense c-mos oligonucleotides prevents meiosis II in the maturing mouse egg.

    OpenAIRE

    O'Keefe, S J; Wolfes, H; Kiessling, A A; Cooper, G M

    1989-01-01

    Injection of antisense oligonucleotides was used to investigate the function of c-mos in murine oocytes. Oocytes injected with antisense c-mos oligonucleotides completed the first meiotic division but failed to initiate meiosis II. Instead, loss of c-mos function led to chromosome decondensation, reformation of a nucleus after meiosis I, and cleavage to two cells. Therefore, c-mos is required for meiosis II during murine oocyte maturation.

  2. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2014-05-01

    Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  3. A CMOS humidity sensor for passive RFID sensing applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  4. Operation and biasing for single device equivalent to CMOS

    Science.gov (United States)

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  5. High-speed polysilicon CMOS photodetector for telecom and datacom

    Science.gov (United States)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  6. Design and characterization of avalanche photodiodes in submicron CMOS technologies

    Science.gov (United States)

    Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

    2014-03-01

    The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

  7. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  8. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  9. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)], E-mail: r.turchetta@rl.ac.uk; Fant, A.; Gasiorek, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Esbrand, C.; Griffiths, J.A.; Metaxas, M.G.; Royle, G.J.; Speller, R.; Venanzi, C. [Department of Medical Physics and Bioengineering, University College London (United Kingdom); Stelt, P.F. van der; Verheij, H.; Li, G. [Academic Centre for Dentistry, Vrije Universiteit and University of Amsterdam (Netherlands); Theodoridis, S.; Georgiou, H. [Department of Informatics and Telecommunications, University of Athens (Greece); Cavouras, D. [Medical Image and Signal Processing Laboratory, Department of Medical Instrument Technology, Technological Education Institution of Athens (Greece); Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D. [High Energy Physics Group, Department of Physics, Imperial College, London (United Kingdom)] (and others)

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS)

  10. Design of Low Voltage Low Power CMOS OP-AMP

    Directory of Open Access Journals (Sweden)

    Shahid Khan,

    2014-11-01

    Full Text Available Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.

  11. Fabrication of the planar angular rotator using the CMOS process

    Science.gov (United States)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  12. IGBT scaling principle toward CMOS compatible wafer processes

    Science.gov (United States)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  13. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  14. E-Beam Effects on CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  15. New Multiple-Times Programmable CMOS ROM Cell

    Science.gov (United States)

    Chung, In-Young; Jeong, Seong Yeol; Seo, Sung Min; Lee, Myungjin; Jang, Taesu; Cha, Seon-Yong; Park, Young June

    New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

  16. From vertex detectors to inner trackers with CMOS pixel sensors

    OpenAIRE

    Besson, A.; Pérez, A. Pérez; Spiriti, E.; Baudot, J.; Claus, G; Goffe, M.; de Winter, M.

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming ...

  17. Modifications in CMOS Dynamic Logic Style: A Review Paper

    Science.gov (United States)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  18. Process optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed

  19. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  20. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  1. Proton therapy beam dosimetry with silicon CMOS image sensors

    International Nuclear Information System (INIS)

    In a previous publication, it has been shown how neutron and proton beams in a quite broad energy interval, could be simply monitored with a position sensitive CMOS image detector. The direct read out, the lack of pile up effects, the stability of the signal, the detector linear response with proton energy and current and the very low costs of the device could make the CMOS detector a good candidate in addition to other well established detectors for proton radiation dosimetry. (N.T.)

  2. Effects of Proton Irradiation on a CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    HUANG Qiang; MENG Xiang-Ti

    2007-01-01

    We perform 9 MeV proton irradiation of a complementary metal oxide semiconductor (CMOS) image sensor at doses from 1×109 to 4×1010 cm-2. In general, the average brightness of dark output images increases with an increasing dose, and reaches the maximum at 1×1010 cm-2. The captured colour images become very blurry at 4×1010 cm-2. These can be explained by change of concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of CMOS image sensor calculated by the TRIM simulation programme with dose.

  3. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  4. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  5. A 65 nm CMOS LNA for Bolometer Application

    Science.gov (United States)

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  6. Low-power CMOS circuit design for fast infrared imagers

    OpenAIRE

    Margarit Taule, Josep Maria

    2008-01-01

    La present tesi de màster detalla novedoses tècniques circuitals per al disseny de circuits integrats digitals CMOS de lectura compactes, de baixa potència i completament programables, destinats a aplicacions d'IR d'alta velocitat operant a temperatura ambient. En aquest sentit, el treball recull i amplia notablement la recerca iniciada en el Projecte Final de Carrera "Tècniques de disseny CMOS per a sistemes de visió híbrids de pla focal modular" obtenint-se resultats específics en tres dife...

  7. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  8. New Curvature-Compensated CMOS Bandgap Voltage Reference

    Institute of Scientific and Technical Information of China (English)

    Lu Shen; Ning Ning; Qi Yu; Yan Luo; Chun-Sheng Li

    2007-01-01

    A novel curvaturecompensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit,designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from 40 ℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is 56 dB at 10 MHz.

  9. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  10. CMOS-compatible photonic devices for single-photon generation

    Science.gov (United States)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  11. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  12. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  13. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Science.gov (United States)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  14. Integrated Circuit of CMOS DC-DC Buck Converter with Differential Active Inductor

    Directory of Open Access Journals (Sweden)

    Kaoutar Elbakkar

    2011-11-01

    Full Text Available In this paper, we propose a new design of DC-DC buck converter (BC, which the spiral inductor is replaced by a differential gyrator with capacitor load (gyrator-C implemented in 0.18um CMOS process. The gyrator-C transforms the capacitor load (which is the parasitic capacitor of MOSFETS to differential active inductor DAI. The low-Q value of DAI at switching frequency of converter (few hundred kHz is boosted by adding a negative impedance converter (NIC. The transistor parameters of DAI and NIC can be properly chosen to achieve the desirable value of equivalent inductance L (few tens H, and the maximum-Q value at the switching frequency, and thus the efficiency of converter is improved. Experimental results show that the converter supplied with an input voltage of 1V, provides an output voltage of 0.74V and output ripple voltage of 10mV at 155 kHz and Q-value is maximum (#8776;4226 at this frequency.

  15. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Directory of Open Access Journals (Sweden)

    Haiyun Huang

    2015-10-01

    Full Text Available This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  16. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-01-01

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

  17. Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology

    CERN Document Server

    Kuczynska, Marika; Bugiel, Szymon; Firlej, Miroslaw; Fiutowski, Tomasz; Idzik, Marek; Michelis, Stefano; Moron, Jakub; Przyborowski, Dominik; Swientek, Krzysztof

    2015-01-01

    A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, w...

  18. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  19. CMOS image sensors as an efficient platform for glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-01

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

  20. CMOS-compatible LVOF-based visible microspectrometer

    Science.gov (United States)

    Emadi, Arvin; Wu, Huaiwen; de Graaf, Ger; Wolffenbuttel, Reinoud F.

    2010-04-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabrication of LVOF involves a process for fabrication of very small taper angles, ranging from 0.001° to 0.1°, in SiO2. These layers can be fabricated flexibly in a resist layer by just one lithography step and a subsequent reflow process. The 3D pattern of the resist structures is subsequently transferred into SiO2 by appropriate etching. Complete LVOF fabrication involves CMOS-compatible deposition of a lower dielectric mirror using a stack of dielectrics on the wafer, tapered layer formation and deposition of the top dielectric mirror. The LVOF has been optimized for 580 nm - 720 nm spectral operating range and has also been mounted on a CCD camera for characterization. The design of LVOF micro-spectrometer, the fabrication and characterization results are presented.

  1. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    consideration. In this work, delay and power metrics for both MCML and CMOS have been studied and a broader analysis of MCML is presented. Near minimum sized transistors are used and power consumption is measured for a wide variety of circuit blocks. The most important goal of this project is to evaluate...

  2. Analysis of the Noise Characteristics of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1997-01-01

    is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches...

  3. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  4. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  5. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    OpenAIRE

    Rescigno R.; Finck Ch.; Juliani D.; Baudot J.; Dauvergne D.; Dedes G.; Krimmer J.; Ray C.; Reithinger V.; Rousseau M.; Testa E; Winter M.

    2014-01-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  6. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  7. New source of random telegraph signal in CMOS image sensors

    OpenAIRE

    Goiffon, Vincent; Magnan, Pierre; Martin-Gonthier, Philippe; Virmontois, Cédric; Gaillardin, Marc

    2012-01-01

    We report a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley-Read-Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations.

  8. Study of CMOS image sensors for laser beam position detection

    International Nuclear Information System (INIS)

    We report on the study made on commercial CMOS image sensors in order to determine their feasibility for light beam position reconstruction. Measurements of the intrinsic position resolution, sensor photoresponse and uniformity were done. The effect of eventual background illumination was evaluated. The precision on the spatial point reconstruction was determined from linearity measurements. First results on gamma-ray radiation tolerance are presented

  9. Fundamental Characteristics of a Pinned Photodiode CMOS Pixels

    NARCIS (Netherlands)

    Xu, Y.

    2015-01-01

    This thesis gives an insightful analysis of the pinned photodiode 4T CMOS pixel from three different aspects. Firstly, from the charge accumulated aspect, the PPD full well capacity and related parameters of influence are investigated such as the pinning voltage, and transfer gate potential barrier.

  10. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  11. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico;

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  12. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  13. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...

  14. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  15. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the outpu

  16. Planar CMOS analog SiPMs: design, modeling, and characterization

    Science.gov (United States)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  17. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  18. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    Science.gov (United States)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  19. An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

    Science.gov (United States)

    Guo, Zhiyong; Li, Qiang; Liu, Haiqi; Yan, Bo; Li, Guangjun

    2011-06-01

    This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), ? input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

  20. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  1. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  2. [Influenza A H1N1v treated with extra-corporal membrane oxygenation.

    DEFF Research Database (Denmark)

    Jensen, Reinhold; Severinsen, Inge Krogh; Terp, Kim;

    2010-01-01

    A 37-year-old woman with body mass index > 30 was admitted to hospital with severe pneumonia due to H1N1v. Thoracic X-ray showed bilateral, diffuse infiltrates. There was no sign of complicating bacterial infection and all microbiological tests of tracheal secretion, blood and urine were negative....... Polymerase chain reaction test for H1N1v was positive until day ten. No mutations were found in the virus. The patient was given oseltamivir tablets and inhalable zanamivir as well as antibiotics. The patient was treated with extra-corporal membrane oxygenation (EcmO) for 12 days followed by ventilator...

  3. Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

    Directory of Open Access Journals (Sweden)

    Edwin Becerra‐Álvarez

    2009-04-01

    Full Text Available This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA for the next generation of wireless hand‐held devicesby using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing thefulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such thatthe mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit underanalysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topologyincluding inductive‐source degeneration, MOS‐varactor based tuning networks, and programmable bias currents. This proposal,with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications;the LNA is designed to cope with the requirements of GSM (PCS1900, WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g. In orderto evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA featuresNF16dB, S11‐3.3 dBm over the 1.85‐2.48 GHz band. For all the standards understudy the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of thereconfigurable LNA occupies an area of 1.8mm2.

  4. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  5. TID Simulation of Advanced CMOS Devices for Space Applications

    Science.gov (United States)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  6. 65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction

    CERN Document Server

    Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

    2014-01-01

    Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

  7. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  8. Effect of Threshold Voltage on Various CMOS Performance Parameter

    Directory of Open Access Journals (Sweden)

    Mr. Abhishek Verma

    2014-04-01

    Full Text Available SiO2, once thought of as the most precious element in the design of CMOS circuits has not lived up to the expectations of being the perfect gate oxide. Efforts have been made to replace it with High K oxides such as Lanthanum Oxide (La2O3, Hafnium Oxide (HfO2 and many more. This review covers the problems faced by the High K oxides, one of them being escalation in threshold voltage which results in increased power dissipation. The solution to the above stated problem is to reduce the threshold voltage by several techniques, also covered in the review. Effect of threshold voltage on leakage current and power and reliability of CMOS are also taken under consideration.

  9. A linear stepping PGA used in CMOS image sensors

    International Nuclear Information System (INIS)

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  10. A linear stepping PGA used in CMOS image sensors

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 李斌桥; 赵士彬; 李红乐; 姚素英

    2009-01-01

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  11. Monolithic CMOS-compatible zero-index metamaterials

    CERN Document Server

    Vulis, Daryl I; Reshef, Orad; Camayd-Muñoz, Philip; Yin, Mei; Kita, Shota; Lončar, Marko; Mazur, Eric

    2016-01-01

    Zero-index materials exhibit exotic optical properties that can be utilized for integrated-optics applications. However, practical implementation requires compatibility with complementary metallic-oxide-semiconductor (CMOS) technologies. We demonstrate a CMOS-compatible zero-index metamaterial consisting of a square array of air holes in a 220-nm-thick silicon-on-insulator (SOI) wafer. This design is achieved through a Dirac-cone dispersion. The metamaterial is entirely composed of silicon and offers compatibility through low-aspect-ratio structures that can be simply fabricated in a standard device layer. This platform enables mass adoption and exploration of zero-index-based photonic devices at low cost and high fidelity.

  12. A New CMOS Current Reference with High Order Temperature Compensation

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 (m standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [(50~100℃] at a 1.8 V supply, and also achieves line regulation of 0.01%/V and (120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.

  13. Photon imaging using post-processed CMOS chips

    OpenAIRE

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic signals (in the extreme case this conversion is from a single photon into a single electron), an electron multiplication structure to increase the magnitude of the signal pulse and a position sensit...

  14. CMOS Image Sensor with a Built-in Lane Detector

    OpenAIRE

    Li-Chen Fu; Hsien-Chein Cheng; Pei-Yung Hsiao; Shih-Shinh Huang

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chi...

  15. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  16. Nanocantilever based mass sensor integrated with cmos circuitry

    OpenAIRE

    Davis, Zachary James; Abadal, G.; Campabadal, F; Figueras, E.; Esteve, J.; Verd, J.; Perez-Murano, F.; Borrise, X.; Nilsson, S. G.; Miximov, I.; Montelius, L.; Barniol, N.; Boisen, Anja

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The d...

  17. CMOS Terahertz Sensors and Circuits for Imaging Applications

    OpenAIRE

    Domingues, Suzana

    2014-01-01

    A low-cost THz sensor, with a broadband high responsivity, low noise equivalent power, and capable of working at room temperature is still a challenge. Moreover, sensor integration with signal processing electronics is required in order to realize compact systems to be used in commercial imaging applications. In this thesis, CMOS FET-based THz detectors and with integrated noise-efficient readout circuits are presented as a solution. In an attempt to improve the THz focal plane arrays stat...

  18. Photon detection with CMOS sensors for fast imaging

    OpenAIRE

    Baudot, J.; Dulinski, W.; de Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N

    2008-01-01

    International audience Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e-, and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of have been reached for 100 kilo-pixels sens...

  19. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  20. Performance Analysis of Visible Light Communication Using CMOS Sensors

    OpenAIRE

    Trong-Hop Do; Myungsik Yoo

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulat...

  1. CMOS bandgap references and temperature sensors and their applications

    OpenAIRE

    Wang, G.

    2005-01-01

    Two main parts have been presented in this thesis: device characterization and circuit. In integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors have been investigated over a wide tempe...

  2. Proton therapy beam dosimetry with silicon CMOS image sensors

    International Nuclear Information System (INIS)

    A 16 mm2 CMOS Image Sensor with more than 100 000 pixels and with a standard video output was irradiated with 48, 95 and 180 MeV protons. Proton-induced nuclear reactions in silicon were detected as bright spots or tracks in the images. The angular and energy-dependent response of the detector were studied. The application to proton dosimetry is discussed

  3. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    OpenAIRE

    Orit Skorka; Dileepan Joseph

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensor...

  4. A CMOS Smart Temperature and Humidity Sensor with Combined Readout.

    OpenAIRE

    Clemens Eder; Virgilio Valente; Nick Donaldson; Andreas Demosthenous

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ra...

  5. CMOS Smart Sensor for Monitoring the Quality of Perishables

    OpenAIRE

    Ueno, K.; Hirose, T; Asai, T.; Amemiya, Y.

    2007-01-01

    We developed a CMOS integrated-circuit sensor to monitor the change in quality of perishables that depends on surrounding temperatures. Our sensor makes use of the fact that the temperature dependence of the subthreshold current in MOSFETs is analogous to that of the degradation of perishables. The sensor is attached to perishable goods such as farm and marine products and is distributed from producers to consumers along with the goods. During their distribution process, the sensor measures t...

  6. CMOS circuits generating arbitrary chaos by using pulsewidthmodulation techniques

    OpenAIRE

    Morie, Takashi; Sakabayashi, S; Nagata, M.; Iwata, A

    2000-01-01

    This paper describes CMOS circuits generating arbitrary chaotic signals. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain. Arbitrary nonlinear transformation functions can be generated by using the conversion from an analog voltage to a pulsewidth modulation (PWM) signal; for the transformation, time-domain nonlinear voltage waveforms having the same shape as the inverse function of the desired transformation function are u...

  7. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  8. High-performance imagers for space applications: The strong benefits of CMOS image sensors processes

    International Nuclear Information System (INIS)

    Space community has quickly understood the benefits that CMOS technology can procure for the design and manufacture of image sensors, with respect to CCDs which have been the detector of choice for most optical applications during the last 25 years. On the other hand, a majority of space applications is requesting high electro-optics performances to avoid payload oversizing. This was not reachable by CMOS monolithic devices built with standard mixed signal processes. Since the end of the 90s, foundries have developed outstanding CMOS processes optimised for Image Sensors. Combined with the intrinsic advantages of CMOS, they allow developing powerful imagers for space missions. After explaining specificity of CIS processes, the development of a first generation of CMOS Image Sensors for optical instrument will be detailed. Continuation of this route, thanks to the use of advanced CMOS processes, will then be presented.

  9. The Influenza A(H1N1)v Pandemic: An Exploratory System Dynamics Approach

    NARCIS (Netherlands)

    Pruyt, E.; Hamarat, C.

    2010-01-01

    This paper presents a small exploratory System Dynamics model related to the dynamics of the 2009 flu pandemic, also known as the Mexican flu, swine flu, or A(H1N1)v. The model was developed in May 2009 in order to quickly foster understanding about the possible dynamics of this new flu variant and

  10. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A; Spiriti, E; Baudot, J; Claus, G; Goffe, M; Winter, M

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  11. Noise sources and noise suppression in CMOS imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  12. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    International Nuclear Information System (INIS)

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development

  13. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  14. Optimization of precision localization microscopy using CMOS camera technology

    Science.gov (United States)

    Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

    2012-02-01

    Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, super resolution precision localization microscopy.

  15. CMOS integration of inkjet-printed graphene for humidity sensing

    Science.gov (United States)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  16. CMOS-compatible graphene photodetector covering all optical communication bands

    Science.gov (United States)

    Pospischil, Andreas; Humer, Markus; Furchi, Marco M.; Bachmann, Dominic; Guider, Romain; Fromherz, Thomas; Mueller, Thomas

    2013-11-01

    Optical interconnects are becoming attractive alternatives to electrical wiring in intra- and interchip communication links. Particularly, the integration with silicon complementary metal-oxide semiconductor (CMOS) technology has received considerable interest because of the ability of cost-effective integration of electronics and optics on a single chip. Although silicon enables the realization of optical waveguides and passive components, the integration of another, optically absorbing, material is required for photodetection. Traditionally, germanium or compound semiconductors are used for this purpose; however, their integration with silicon technology faces major challenges. Recently, graphene emerged as a viable alternative for optoelectronic applications, including photodetection. Here, we demonstrate an ultra-wideband CMOS-compatible photodetector based on graphene. We achieved a multigigahertz operation over all fibre-optic telecommunication bands beyond the wavelength range of strained germanium photodetectors, the responsivity of which is limited by their bandgap. Our work complements the recent demonstration of a CMOS-integrated graphene electro-optical modulator, and paves the way for carbon-based optical interconnects.

  17. CMOS IC design for wireless medical and health care

    CERN Document Server

    Wang, Zhihua; Chen, Hong

    2014-01-01

    This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to tu...

  18. First result on biased CMOS MAPs-on-diamond devices

    Energy Technology Data Exchange (ETDEWEB)

    Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    OpenAIRE

    Esposito, M.; Anaxagoras, T; Konstantinidis, AC; Zheng, Y.; Speller, RD; Evans, PM; Allinson, NM; Wells, K

    2014-01-01

    Recently CMOS Active Pixels Sensors (APSs) have become a valuable alternative to amorphous Silicon and Selenium Flat Panel Imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non...

  20. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  1. SiGe BiCMOS RF ICs and Components for High Speed Wireless Data Networks

    OpenAIRE

    Svitek, Richard M

    2005-01-01

    The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvem...

  2. Single photon detection and localization accuracy with an ebCMOS camera

    Science.gov (United States)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  3. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Kazusuke Maenaka; Kohei Higuchi; Oleg Nizhnik

    2011-01-01

    A 1.1 µW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  4. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures...

  5. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    Energy Technology Data Exchange (ETDEWEB)

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  6. Design, Implementation And Characterization Of Xor Phase Detector For Dpll In 45 Nm Cmos Technology

    OpenAIRE

    Delvadiya Harikrushna I; Mr. Mukesh Tiwari; Jay Karan Singh; Jay Karan Sing

    2011-01-01

    In this paper the implementation of XOR phase detector in 45 nm submicron CMOS technology and it’sCMOS design layout using Microwind 3.1 for Digital Phase Locked Loop in sub-nanometres CMOSTechnology is presented. The input-output transfer characteristic of XOR phase detector is presented. TheCMOS XOR phase detector produces error pulses on both rising and falling edges while the CMOS phasefrequency detector will respond only to positive or negative transitions. XOR phase detector will try to...

  7. Investigation of CMOS photodiodes integrated on an ASIC by a 0.5-µm analog CMOS process

    Science.gov (United States)

    Luo, H.; Ricklefs, U.; Hillmer, H.

    2010-04-01

    The characteristics of photodiodes integrated on CMOS ASICs depend on wavelength of radiation, structure of the photodiode itself and the parameters of the process of production. In this paper, the influence of the structure of integrated CMOS photodiodes produced in a standard 0.5 μm mixed signal CMOS process on the sensitivity is described. These photodiodes are used as image sensor elements arranged in an array for noncontact optoelectronic measurements. Models of integrated photodiodes distinguish the lateral and the vertical region of the photodiodes. The standard 0.5 μm CMOS process offers three types of pn-junctions: n+/p-substrate, p+/n-well and n-well/p-substrate. Based on our previous research and on the results from other authors the p+/n-well is chosen due to its better sensitivity and isolation against other structures. The local sensitivity is measured with a scanning setup by applying a diffraction limited spot spot of light on the surface of the diodes. Independent of the wavelength of radiation the charge carriers are generated mainly in the lateral region and not - as expected - in the vertical region. The maximum value of the local sensitivity is found in photodiodes with subdivided p+ regions showing a distance of 1.5 μm between these regions in the space between these two adjacent p+ regions. This local sensitivity is three times smaller than that of a reference PIN photodiode. According to this result, the new photodiodes will be constructed with optimized geometries. All examined structures of this type of photodiodes show a maximal spectral sensitivity in the range of 650 nm - 700 nm.

  8. CMOS APS 器件及其在星敏感器中的应用%Application of CMOS APS in Star Tracker

    Institute of Scientific and Technical Information of China (English)

    李杰; 刘金国; 刘亚侠; 郝志航

    2004-01-01

    介绍了CMOS有源像元图像传感器(APS)的原理与结构特点,阐述了CMOS APS与CCD比较应用于星敏感器的潜在优势,详细介绍了CMOS图像传感器在星敏感器中的应用现状,并对基于CMOS APS与基于CCD的星敏感器的测量精度结果进行对比,展望了CMOS APS星敏感器的发展前景.

  9. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    Science.gov (United States)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  10. A New 1-V Second-Order Temperature-Compensated Current Reference

    Institute of Scientific and Technical Information of China (English)

    YI Jun; ZHANG Bo; FANG Jian; LI Zhaoji

    2004-01-01

    A new bipolar temperature-compensated current reference is proposed.The first-order temperature compensation is achieved by the idea of self temperature-compensation configuration exploiting the temperature coefficient of a combined resistor.The second-order compensation employs a VBE-tracking thermal-startup technique to obtain improved temperature performance.The proposed circuit can operate down to a 1-V supply.A temperature coefficient of 46.6 ×10-6/ ℃ [0,100 ℃] at a 1-V supply and a supply regulation of 0.036%/V at 25 ℃ are achieved.Compared with present works,the proposed circuit shows better results of the temperature coefficient and supply regulation.The current matching issue frequently encountered in current references is also discussed in detail.

  11. Inside the outbreak of the 2009 influenza A (H1N1v virus in Mexico.

    Directory of Open Access Journals (Sweden)

    Hector M Zepeda-Lopez

    Full Text Available BACKGROUND: Influenza viruses pose a threat to human health because of their potential to cause global disease. Between mid March and mid April a pandemic influenza A virus emerged in Mexico. This report details 202 cases of infection of humans with the 2009 influenza A virus (H1N1v which occurred in Mexico City as well as the spread of the virus throughout the entire country. METHODOLOGY AND FINDINGS: From May 1st to May 5th nasopharyngeal swabs, derived from 751 patients, were collected at 220 outpatient clinics and 28 hospitals distributed throughout Mexico City. Analysis of samples using real time RT-PCR revealed that 202 patients out of the 751 subjects (26.9% were confirmed to be infected with the new virus. All confirmed cases of human infection with the strain influenza (H1N1v suffered respiratory symptoms. The greatest number of confirmed cases during the outbreak of the 2009 influenza A (H1N1v were seen in neighbourhoods on the northeast side of Mexico City including Iztapalapa, Gustavo A. Madero, Iztacalco, and Tlahuac which are the most populated areas in Mexico City. Using these data, together with data reported by the Mexican Secretariat of Health (MSH to date, we plot the course of influenza (H1N1v activity throughout Mexico. CONCLUSIONS: Our data, which is backed up by MSH data, show that the greatest numbers of the 2009 influenza A (H1N1 cases were seen in the most populated areas. We speculate on conditions in Mexico which may have sparked this flu pandemic, the first in 41 years. We accept the hypothesis that high population density and a mass gathering which took in Iztapalapa contributed to the rapid spread of the disease which developed in three peaks of activity throughout the Country.

  12. Inside the Outbreak of the 2009 Influenza A (H1N1)v Virus in Mexico

    Science.gov (United States)

    Zepeda-Lopez, Hector M.; Perea-Araujo, Lizbeth; Miliar-García, Angel; Dominguez-López, Aarón; Xoconostle-Cázarez, Beatriz; Lara-Padilla, Eleazar; Ramírez Hernandez, Jorge A.; Sevilla-Reyes, Edgar; Orozco, Maria Esther; Ahued-Ortega, Armando; Villaseñor-Ruiz, Ignacio; Garcia-Cavazos, Ricardo J.; Teran, Luis M.

    2010-01-01

    Background Influenza viruses pose a threat to human health because of their potential to cause global disease. Between mid March and mid April a pandemic influenza A virus emerged in Mexico. This report details 202 cases of infection of humans with the 2009 influenza A virus (H1N1)v which occurred in Mexico City as well as the spread of the virus throughout the entire country. Methodology and Findings From May 1st to May 5th nasopharyngeal swabs, derived from 751 patients, were collected at 220 outpatient clinics and 28 hospitals distributed throughout Mexico City. Analysis of samples using real time RT-PCR revealed that 202 patients out of the 751 subjects (26.9%) were confirmed to be infected with the new virus. All confirmed cases of human infection with the strain influenza (H1N1)v suffered respiratory symptoms. The greatest number of confirmed cases during the outbreak of the 2009 influenza A (H1N1)v were seen in neighbourhoods on the northeast side of Mexico City including Iztapalapa, Gustavo A. Madero, Iztacalco, and Tlahuac which are the most populated areas in Mexico City. Using these data, together with data reported by the Mexican Secretariat of Health (MSH) to date, we plot the course of influenza (H1N1)v activity throughout Mexico. Conclusions Our data, which is backed up by MSH data, show that the greatest numbers of the 2009 influenza A (H1N1) cases were seen in the most populated areas. We speculate on conditions in Mexico which may have sparked this flu pandemic, the first in 41 years. We accept the hypothesis that high population density and a mass gathering which took in Iztapalapa contributed to the rapid spread of the disease which developed in three peaks of activity throughout the Country. PMID:20949040

  13. 技术手册:prb 1v3技术分析

    Institute of Scientific and Technical Information of China (English)

    Lucid; Dreaming

    2005-01-01

    Cpl_Mill A炸点左侧通道,从来都是兵家必争之地,狭长的地形对选手的个人能力提出了极高的要求,在Tearn9与SK.swe比赛的关键局中,Team9的新人prb就在这个位置上演了一出精彩的1v3,使得Team9拿下了这个关键局,把SK.swe在上半场的经济打入谷底,为最终的胜利奠定了良好的基础。下面我们就从技术角度来分析一下这个1v3。(由于比赛的hltv录像质量原因,为了让读者更好地看到这次1v3的精髓,小编们亲自上阵做了一次示意图。)

  14. Design and experimental verification of low-voltage two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array

    Science.gov (United States)

    Yamaji, Yuuki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Electrophoresis is widely used in biomedical applications. However, conventional (centimeter-order) electrophoresis requires a high-voltage power supply, which is not suitable for point-of-care testing (POCT). Electrophoresis is driven by electric fields, and miniaturization (from the centimeter order to the micrometer order) is effective for low-voltage operation. A CMOS platform is a cost-competitive and promising candidate for miniaturization and enables the integration of biomolecule manipulation by electrophoresis and its electrochemical sensing. These features will contribute to the development of a biochemical analyzer called the micro-total analysis system (µ-TAS). To realize a truly portable electrophoresis system, we present the design and experimental verification of a low-voltage (<1 V), two-dimensional CMOS electrophoresis platform with 32 × 32 sample/hold cell array. Experimental results showed successful constant voltage outputs to each electrode. By miniaturizing the electrode structure to a 60 µm pitch, we achieved sufficient electric field strength even at low voltages.

  15. Structures of HIV-1-Env V1V2 with broadly neutralizing antibodies reveal commonalities that enable vaccine design

    OpenAIRE

    Gorman, Jason; Soto, Cinque; Yang, Max M.; Davenport, Thaddeus M.; Guttman, Miklos; Robert T Bailer; Chambers, Michael; Chuang, Gwo-Yu; DeKosky, Brandon J.; Doria-Rose, Nicole A.; Druz, Aliaksandr; Ernandes, Michael J.; Georgiev, Ivelin S.; Jarosinski, Marissa C.; Joyce, M. Gordon

    2015-01-01

    Broadly neutralizing antibodies (bNAbs) against HIV-1-Env V1V2 arise in multiple donors. However, atomic-level interactions had only been determined with antibodies from a single donor, making commonalities in recognition uncertain. Here we report the co-crystal structure of V1V2 with antibody CH03 from a second donor and model Env interactions of antibody CAP256-VRC26 from a third. These V1V2-directed bNAbs utilized strand-strand interactions between a protruding antibody loop and a V1V2 str...

  16. Leakage Power Reduction and Analysis of CMOS Sequential Circuits

    Directory of Open Access Journals (Sweden)

    M. Janaki Rani

    2012-02-01

    Full Text Available A significant portion of the total power consumption in high performance digital circuits in deep sub micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

  17. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Kovalgin, Alexey Y.; Werf, van der Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  18. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  19. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Science.gov (United States)

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors...

  20. CMOS instrumentation amplifier with offset cancellation circuitry and high PSRR for low power application

    International Nuclear Information System (INIS)

    This paper presents the design and development of a CMOS instrumentation amplifier for biomedical application. The instrumentation amplifier possesses a very high power-supply rejection ratio (PSRR) and is able to operate at single supply voltage for low power application with improved performance compared to existing work. It also has a full CMOS implementation of offset cancellation circuitry. (author)

  1. An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.

    2013-01-01

    This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...

  2. Monolithic CMOS Pixel R&D for the ILC at LBNL

    OpenAIRE

    M. Battaglia; Abrams, G.; Denes, P.; Greiner, L. C.; Hooberman., B; Tompkins, L.; Wieman, H. H.

    2005-01-01

    An R&D program on monolithic CMOS pixel sensors for application at the ILC has been started at LBNL. This program profits of significant synergies with other R&D activities on CMOS pixel sensors. The project activities after the first semester of the R&D program are reviewed.

  3. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

    Institute of Scientific and Technical Information of China (English)

    Yin-Shui Xia; Lun-Yao Wang; A. E. A. Almaini

    2005-01-01

    A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. Pspice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.

  4. Spatial and temporal expression of c-mos in mouse testis during postnatal development

    Institute of Scientific and Technical Information of China (English)

    Shao-Feng Cao; Ding Li; Qing Yuan; Xin Guan; Chen Xu

    2008-01-01

    Aim: To immunolocalize the c-mos gene product and to investigate its spatial and temporal expression in mouse testis during postnatal development. Methods: Semi-quantitative reverse transcription-polymerase chain reaction (RT-PCR) and in situ hybridization techniques were used to examine c-mos mRNA and indirect immunofluorescence was used to localize c-Mos protein in mouse testis on postnatal days 14, 21, 25, 28, 30, 35, 49 and 70. Results: c-mos mRNA remained low on postnatal days 14-21, increased abruptly from day 25 and peaked on day 30. Its levels decreased a little on day 35 and became almost stable thereafter until day 70. c-mos mRNA was localized in the nucleus and cytoplasm of the spermatocytes and round spermatids. The nuclear staining was much stronger than the cytoplasmic staining. Using a polyclonal anti-c-Mos antibody, Western blotting detected a single band at 43 kDa in testis lysate, c-Mos protein was exclusively localized to the elongating spermatids and was first detected on postnatal day 30. The number of c-Mos-positive spermatids increased progressively till day 49 and stabilized thereafter.Conclusion: The c-mos gene displays a spatial and temporal expression pattern in the mouse testis during postnatal development at both the mRNA and protein level. This suggests that c-mos might play important roles in spermatogenesis.

  5. Feasibility Study of Analogue and Digital Temperature Sensors in Nanoscale CMOS Technologies

    NARCIS (Netherlands)

    Geljon, M.; Sill, F.; De Lima Monteiro, D.W.

    2009-01-01

    The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Te

  6. Solar Battery Charger in CMOS 0.25 um Technology

    OpenAIRE

    Tao Wang; Chang-Ching Huang; Tian-Jen Wang

    2014-01-01

    A solar cell powered Li-ion battery charger in CMOS 0.25um is proposed. The solar battery charger consists of a DC/DC boost converter and a battery charger. The voltage generated by a solar cell is up converted from 0.65V to 1.8V, which is used as the VDD of the battery charger.  In this way, the solar battery charger automatically converts solar energy to electricity and stores it directly to a Li-ion rechargeable battery. In this system, a super capacitor is needed as a charge buffer betwee...

  7. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    Science.gov (United States)

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  8. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  9. 0.18μm CMOS, MONOLITHIC MSTP ASIC

    Institute of Scientific and Technical Information of China (English)

    Wang Peng; Jin Depeng; Zeng Lieguang

    2006-01-01

    A highly integrated monolithic Multi-Service Transport Platform (MSTP) Application Specified Integrated Circuit (ASIC) MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×106 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring (RPR) and E1 traffics into protected Synchronous Digital Hierarchy (SDH) STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.

  10. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    Science.gov (United States)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration

  11. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  12. Design procedure for optimizing CMOS low noise operational amplifiers

    Institute of Scientific and Technical Information of China (English)

    Li Zhiyuan; Ye Yizheng; Ma Jianguo

    2009-01-01

    This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

  13. Displacement damage effects in pinned photodiode CMOS image sensors

    International Nuclear Information System (INIS)

    This paper investigates the effects of displacement damage in Pinned Photodiode (PPD) CMOS Image Sensors (CIS) using proton and neutron irradiations. The DDD ranges from 12 TeV/g to 1.2 * 106 TeV/g. Particle fluence up to 5 * 1014 n.cm-2 is investigated to observe electro-optic degradation in harsh environments. The dark current is also investigated and it would appear that it is possible to use the dark current spectroscopy in PPD CIS. The dark current random telegraph signal is also observed and characterized using the maximum transition amplitude. (authors)

  14. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  15. Trade-offs in Specific CMOS RF Communication Circuits

    Institute of Scientific and Technical Information of China (English)

    李效龙; 田雨波

    2009-01-01

    The design trade-off in the front-end of the transceiver, such as LNA, mixer, local oscillator and PA, is concerned. The advantages and limitations of the circuit topologies and key parameters of the state-of-the-art CMOS transceiver building blocks are discussed in order to gain more insight about a specific block design. A normalized formula of the figures of merit for each building block is also proposed to evaluate the overall performance of various circuits for fair comparison.

  16. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.;

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... to solve the problem, namely freeze-drying and resist-assisted release. The fabrication results of cantilevers defined by laser and E-beam lithography are shown. Finally, an AFM based characterization setup is presented and the electrical characterization of a laser-defined cantilever fully integrated...

  17. Extrinsic parameter extraction and RF modelling of CMOS

    Science.gov (United States)

    Alam, M. S.; Armstrong, G. A.

    2004-05-01

    An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation.

  18. Monolithic CMOS-MEMS resonant beams for ultrasensitive mass detection

    OpenAIRE

    Verd Martorell, Jaume

    2008-01-01

    Estructures ressonants en forma de biga (p.e. ponts o palanques) són molt interessants com a element transductor en sensors físics, químics i biològics basats en sistemes micro-/nanoelectromecànics (M-/NEMS) degut a la seva simplicitat, al gran rang de dominis que poden sensar, i a la seva extremada alta sensibilitat. Aquesta tesis està focalitzada en el disseny, fabricació i caracterització de CMOS-MEMS monolítics basats en bigues ressonants a escala sub-micromètrica per a la seva utilitzaci...

  19. Flow characteristics in stepped spillways with 1V: 0,75H slope; Caracterizacao do escoamento sobre vertedouros em degraus de declividade 1V: 0,75H

    Energy Technology Data Exchange (ETDEWEB)

    Sanagiotto, Daniela Guzzon; Marques, Marcelo Giulian [Universidade Federal de Santa Maria (UFSM), RS (Brazil). Dept. de Engenharia Sanitaria e Ambiental. Centro de Tecnologia], E-mail: dsanagiotto@gmail.com

    2011-07-15

    Stepped spillways are structures characterized by the significant resistance imposed to the flow and by the increase in the energy dissipation associated with the friction inserted by the steps. Stepped chutes conduct to economical designs of downstream protection structures in comparison to the ones required in conventional chute spillways (smooth chute). In this work measurements were carried out in physical models of spillways with 1V: 0.75H (53,13 deg) slope and steps height of (1) 0.03 m; (2) 0.06 m and (3) 0.09 m and in a smooth chute with the same slope. The models were installed in a channel with 0.40 m wide and 2.44 m height, evaluating specific discharges between 0.027 and 0.700 m{sup 3}/s/m, that, for a 1:10 scale, corresponds to discharges between 0.8 and 22.1 m{sup 3}/s/m in prototype. According to the results, a methodology was defined for the evaluation of the inception point of air entrainment, the friction factor and the energy dissipation along the flume. (author)

  20. Development of high gain photodiode array based on commercial CMOS process

    International Nuclear Information System (INIS)

    Developing photodiodes in commercial CMOS process and integrating it with readout electronics without any process modification involves formidable challenges. Due to low resistivity of the wafer used in commercial CMOS process, the junction capacitance per area of the PN junction is quite large thereby limiting the size of the active area of the photodiode leading to degradation in high speed response. On the contrary, the sensitivity and quantum efficiency of the optical detector tends to improve with increase in active area of the detector. The major challenge in designing high gain photodiode in sub micron CMOS technology is to avoid the premature perimeter edge breakdown or the soft breakdown. This paper reports two different design approaches of high gain photodiode arrays in commercial 0.35 um CMOS technology and HV CMOS process

  1. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  2. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    International Nuclear Information System (INIS)

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  3. The Dexela 2923 CMOS X-ray detector: A flat panel detector based on CMOS active pixel sensors for medical imaging applications

    OpenAIRE

    Konstantinidis, A. C.; Szafraniec, M. B.; Speller, R.D.; Olivo, A.

    2012-01-01

    Complementary metal-oxide-semiconductors (CMOS) active pixel sensors (APS) have been introduced recently in many scientific applications. This work reports on the performance (in terms of signal and noise transfer) of an X-ray detector that uses a novel CMOS APS which was developed for medical X-ray imaging applications. For a full evaluation of the detector's performance, electro-optical and X-ray characterizations were carried out. The former included measuring read noise, full well capacit...

  4. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    Science.gov (United States)

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  5. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

  6. CMOS mm-wave transceivers for Gbps wireless communication

    Science.gov (United States)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  7. Smart CMOS image sensor for lightning detection and imaging.

    Science.gov (United States)

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

  8. Improvement to the signaling interface for CMOS pixel sensors

    Science.gov (United States)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  9. A CMOS Imager with Focal Plane Compression using Predictive Coding

    Science.gov (United States)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  10. Single donor electronics and quantum functionalities with advanced CMOS technology

    International Nuclear Information System (INIS)

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature. (topical review)

  11. An integrated CMOS high data rate transceiver for video applications

    Institute of Scientific and Technical Information of China (English)

    Liang Yaping; Che Dazhi; Liang Cheng; Sun Lingling

    2012-01-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology hy using a proprietary protocol,which combines the new IEEE 802.11n features such as multiplein multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment.The RF frequencies cover from 4.9 to 5.9 GHz:the industrial,scientific and medical (ISM) band.Each RF channel bandwidth is 20 MHz.The transceiver utilizes a direct up transmitter and low-IF receiver architecture.A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration.The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  12. Performance of Very Small Robotic Fish Equipped with CMOS Camera

    Directory of Open Access Journals (Sweden)

    Yang Zhao

    2015-10-01

    Full Text Available Underwater robots are often used to investigate marine animals. Ideally, such robots should be in the shape of fish so that they can easily go unnoticed by aquatic animals. In addition, lacking a screw propeller, a robotic fish would be less likely to become entangled in algae and other plants. However, although such robots have been developed, their swimming speed is significantly lower than that of real fish. Since to carry out a survey of actual fish a robotic fish would be required to follow them, it is necessary to improve the performance of the propulsion system. In the present study, a small robotic fish (SAPPA was manufactured and its propulsive performance was evaluated. SAPPA was developed to swim in bodies of freshwater such as rivers, and was equipped with a small CMOS camera with a wide-angle lens in order to photograph live fish. The maximum swimming speed of the robot was determined to be 111 mm/s, and its turning radius was 125 mm. Its power consumption was as low as 1.82 W. During trials, SAPPA succeeded in recognizing a goldfish and capturing an image of it using its CMOS camera.

  13. High-Q CMOS-integrated photonic crystal microcavity devices.

    Science.gov (United States)

    Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  14. Design and Analysis of Hybrid CMOS SRAM Sense Amplifier

    Directory of Open Access Journals (Sweden)

    Karishma Bajaj

    2012-03-01

    Full Text Available Sense amplifiers are one of the very important peripheral components of CMOS memories. In a Hybrid Sense amplifier both current and voltage sensing techniques are used which makes it a better selection than a conventional current or voltage sense amplifiers. The hybrid sense amplifier works in three phases-Offset cancellation (200ps, Access phase (500ps and Evaluation phase. The offset cancellation is done simultaneously with word line decoding, so as to speed up the process. The sensing range of the hybrid sense amplifier is improved from 1.18mV to 92mV. Also hybrid sense amplifier consumes very low energy of about 6.84fj. This sense amplifier is analyzed with a column of 512 SRAM cells at 180nm technology node and compared to CMOS conventional voltage sense amplifier. The circuit consumes an average power of 1.57 µW with a negligible offset of 149.3µV.

  15. BiCMOS-integrated photodiode exploiting drift enhancement

    Science.gov (United States)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  16. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  17. A charge pump for driving CMOS active pixel reset

    Institute of Scientific and Technical Information of China (English)

    XU Jiang-tao; LI Bin-qiao; YAO Su-ying; SUN Zhong-yan

    2009-01-01

    To overcome the limitation of low image signal swing range and long reset time in four transistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open perfor-mance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage tipple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is eliminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 ~ 106 pixeis.

  18. High-stage analog accumulator for TDI CMOS image sensors

    Science.gov (United States)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  19. A Low-Cost CMOS Programmable Temperature Switch

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2008-05-01

    Full Text Available A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  20. NV-CMOS HD camera for day/night imaging

    Science.gov (United States)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  1. Seroprevalence study in Vojvodina (Serbia following 2009 pandemic influenza A(H1N1v

    Directory of Open Access Journals (Sweden)

    Petrović Vladimir

    2012-01-01

    Full Text Available Introduction. The seroprevalence study was performed in Vojvodina during May and June 2010 in order to asses the effects of the 2009 pandemic influenza A(H1N1v epidemic on herd immunity. It was a part of the Serbian Ministry of Health funded nationwide study. Objective. Prevalence of antibodies against 2009 pandemic influenza A(H1N1v was determined in a 1% sample of the population monitored for influenza-like illness and acute respiratory infections in Vojvodina through sentinel surveillance system. Methods. The study sample involved a total of 1004 inhabitants of Vojvodina. The control group consisted of randomly selected and age-adjusted 1054 sera collected in the pre-pandemic period. Sera were tested by the reaction of hemagglutination inhibition using influenza A/California/7/2009 (H1N1 antigen in dilution from 1:8 to 1:256. Antibody titers ≥1:32 and ≥1:8 were considered protective and diagnostic, respectively. Results. The differences between control and study sera in all age groups were significant for both diagnostic ≥1/8 and protective titres ≥1/32 of hemagglutination inhibition antibodies (chi square test, p<0.001. The highest percentage of seropositive subjects was registered in the age group 15-19 years followed by children aged 5-14 years. Both diagnostic and protective titres were about twice higher in the vaccinated as compared to the non-vaccinated group. There were no statistically significant differences in seroprevalence between seven districts of Vojvodina. Conclusion. The 2009 pandemic influenza A(H1N1v epidemic significantly influenced the herd immunity in our population regardless of low immunization coverage with highest immunity levels in adolescents aged 15-19 years and with similar herd immunity levels in all the regions in the province six months after the outbreak.

  2. t-channel factorization description of γγ->V1V2

    International Nuclear Information System (INIS)

    A t-channel factorization model is used to estimate cross sections for the processes γγ->V1V2. Whenever V=rho, the width of the rho has been included in the calculations. The channels γγ->rho0rho0, rho0phi, phiphi, ωω, rho0ω and rho+rho- are calculated for two quasi-real photons. Predictions are also given for the process γsup(*)γ->rho0rho0 for virtual photon mass squared Q22. Our results are consistent with all available experimental data. (orig.)

  3. Mechano-optical wavelength tuning in a photonic crystal microcavity with sub-1 V drive voltage.

    Science.gov (United States)

    Abdulla, Shahina M C; Kauppinen, Lasse J; Krijnen, Gijs J M; de Ridder, René M

    2012-06-01

    A micro-bimorph cantilever with self-aligned nanotips is monolithically integrated with a photonic crystal based device using optical and deep UV lithography techniques. Upon electrostatic actuation, the dielectric nanotips perturb the optical field, providing electromechano-optical modulation of light. Static tuning of the optical transmission spectra by more than 600 pm is measured with a sub-1 V drive voltage, resulting in a modulation as high as 21 dB. The observed strong electromechano-optical effect may find application in power efficient devices for optical communication networks, such as wavelength routing elements.

  4. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1...... circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  5. A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Jiang Chen; Huang Yumei; Hong Zhiliang

    2013-01-01

    A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency.With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

  6. Measured dynamic social contact patterns explain the spread of H1N1v influenza.

    Science.gov (United States)

    Eames, Ken T D; Tilston, Natasha L; Brooks-Pollock, Ellen; Edmunds, W John

    2012-01-01

    Patterns of social mixing are key determinants of epidemic spread. Here we present the results of an internet-based social contact survey completed by a cohort of participants over 9,000 times between July 2009 and March 2010, during the 2009 H1N1v influenza epidemic. We quantify the changes in social contact patterns over time, finding that school children make 40% fewer contacts during holiday periods than during term time. We use these dynamically varying contact patterns to parameterise an age-structured model of influenza spread, capturing well the observed patterns of incidence; the changing contact patterns resulted in a fall of approximately 35% in the reproduction number of influenza during the holidays. This work illustrates the importance of including changing mixing patterns in epidemic models. We conclude that changes in contact patterns explain changes in disease incidence, and that the timing of school terms drove the 2009 H1N1v epidemic in the UK. Changes in social mixing patterns can be usefully measured through simple internet-based surveys. PMID:22412366

  7. A 1 V supercapacitor device with nanostructured graphene oxide/polyaniline composite materials

    Indian Academy of Sciences (India)

    Deepak Kumar; Anjan Banerjee; Satish Patil; Ashok K Shukla

    2015-10-01

    Polyaniline and graphene oxide composite on activated carbon cum reduced graphene oxide-supported supercapacitor electrodes are fabricated and electrochemically characterized in a three-electrode cell assembly. Attractive supercapacitor performance, namely high-power capability and cycling stability for graphene oxide/polyaniline composite, is observed owing to the layered and porous-polymeric-structured electrodes. Based on the materials characterization data in a three-electrode cell assembly, 1 V supercapacitor devices are developed and performance tested. A comparative study has also been conducted for polyaniline and graphene oxide/polyaniline composite-based 1 V supercapacitors for comprehending the synergic effect of graphene oxide and polyaniline. Graphene oxide/polyaniline composite-based capacitor that exhibits about 100 F g−1 specific capacitance with faradaic efficiency in excess of 90% has its energy and power density values of 14 Wh kg−1 and 72 kW kg−1, respectively. Cycle-life data for over 1000 cycles reflect 10% capacitance degradation for graphene oxide/polyaniline composite supercapacitor.

  8. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  9. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  10. Development of high-performances monolithic CMOS detectors for space applications

    OpenAIRE

    Larnaudie, Franck; Vignon, Bruno; Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Martin-Gonthier, Philippe; Corbière, Franck; Basolo, Stephanie

    2002-01-01

    This paper describes the development of a 750x750 pixels CMOS image sensor for star tracker applications. A first demonstrator of such a star tracker called SSM star tracker built around a 512x512 detector has been recently developed and proves the feasibility of such instrument. In order to take fully advantage of the CMOS image sensor step, the 750x750 device called SSM CMOS detector which will take part of the final star tracker, can be considered as a major technical breakthrough that...

  11. An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits

    OpenAIRE

    Ashok Srivastava; Chuang Zhang

    2008-01-01

    A CMOS body-bias generating circuit has been designed for generating adaptive body-biases for MOSFETs in CMOS circuits for low voltage operation. The circuit compares the frequency of an internal ring oscillator with an external reference clock. When the reference clock is “high,” a forward body-bias is generated. When the reference clock is “low,” a reverse body-bias is generated. The forward body bias is limited to no more than 0.4 V to avoid CMOS latchup. The reverse body bias is limited t...

  12. A CMOS current preamplifier and shaper with 50Ω line driver for liquid argon preshower

    International Nuclear Information System (INIS)

    In the field of liquid argon calorimetry for the LHC detector program, a CMOS ''current conveyor'' preamplifier was cold preshower. It is an improved version of the ICON circuit which had been formerly designed by the RD2 collaboration. This paper also presents a CMOS linear output buffer, featuring a dynamic range close to ±2V on a 50Ω load, for a 21 mW power dissipation at 77K. Furthermore a biquadratic 7 MHz bandpass filter was developed, based on a high speed rail to rail CMOS operational amplifier. It is meant to be the filter placed at the output of the ICON preamplifier

  13. A new interpolating method based on the variation of spectra energy using CMOS array

    Institute of Scientific and Technical Information of China (English)

    Tianjin Tang; Xiangqun Cao; Hongqiu Chen; Bin Lin

    2005-01-01

    @@ A new interpolating method to enhance the resolution of gratings using complementary metal-oxide semiconductor (CMOS) according to the variation of some specified spectral light intensities during the motion of scale grating in a periodic separation is proposed. CMOS image sensor (pixel array 648 × 488) was also introduced as receiving device and its stability was verified experimentally. Many factors in the experiment were analyzed theoretically and contrasted with experiment. The advantages of this novel method were featured by CMOS and the specified spectral variation of the energy distribution was discussed.

  14. Developing CMOS Camera and USB Device Drivers in Linux 2.6.32

    Directory of Open Access Journals (Sweden)

    CH. P. N. S. Sujitha

    2013-07-01

    Full Text Available —This paper proposes CMOS camera and USB device drivers implementation on S3C2440 using LINUX 2.6.32. The CMOS camera driver is used for video acquisition applications, which implements image-sensor technology and USB driver is used for data acquisition applications, establishes communication between host computer and a number of peripheral devices. OV9650 CMOS camera is implemented in linux 2.6.32, uses V4L2 protocol for complying. Similarly USB device in LINUX kernel uses struct urb structure to communicate with all USB devices

  15. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    OpenAIRE

    Zujun Wang; Shaoyan Huang; Minbo Liu; Zhigang Xiao; Baoping He; Zhibin Yao; Jiangkun Sheng

    2014-01-01

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN)...

  16. Polarisation analysing complementary metal-oxide semiconductor image sensor in 65-nm standard CMOS technology

    Directory of Open Access Journals (Sweden)

    N. Wakama

    2013-09-01

    Full Text Available In the present study, the authors demonstrate a complementary metal-oxide semiconductor (CMOS image sensor implemented with on-chip polarisers using 65-nm standard CMOS technology. The polariser is composed of metal wire grids made of metal wires fabricated by the CMOS process. An extinction ratio of 18.8 dB was obtained for a single pixel with an on-chip polariser, where the line/space widths have the finest pitch obtainable by 65-nm technology. Electrical crosstalk between pixels is reduced by over 25% using a guard ring structure. Polarisation imaging by the sensor was also performed.

  17. Reset noise reduction through column-level feedback reset in CMOS image sensors

    International Nuclear Information System (INIS)

    A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6 μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination. (semiconductor integrated circuits)

  18. Reset noise reduction through column-level feedback reset in CMOS image sensors*

    Institute of Scientific and Technical Information of China (English)

    Li Binqiao; Xu Jiangtao; Xie Shuang; Sun Zhongyan

    2011-01-01

    A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

  19. SiGe HBT BiCMOS technology for millimeter-wave applications

    Science.gov (United States)

    Joseph, Alvin; Dahlstrom, Mattias; Liu, Qizhi; Orner, Bradley; Liu, Xuefeng; Sheridan, David; Rassel, Robert; Dunn, Jim; Ahlgren, David

    2006-03-01

    We present the advances in Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) and BiCMOS technology capabilities to address the emerging millimetre-wave (mmWave) applications. SiGe HBTs with f MAX performance reaching 350 GHz that are integrated with advanced CMOS and high-frequency passives is envisioned to allow better integration capability for mmWave applications. This capability of SiGe HBT BiCMOS technology is discussed relative to an InP HBT technology.

  20. Mutation analysis of the c-mos proto-oncogene in human ovarian teratomas.

    OpenAIRE

    de Foy, K. A.; Gayther, S A; Colledge, W.H.; Crockett, S; Scott, I V; Evans, M.J.; Ponder, B A

    1998-01-01

    Female transgenic mice lacking a functional c-mos proto-oncogene develop ovarian teratomas, indicating that c-mos may behave as a tumour-suppressor gene for this type of tumour. We have analysed the entire coding region of the c-MOS gene in a series of human ovarian teratomas to determine whether there are any cancer-causing alterations. DNA from twenty teratomas was analysed by single-strand conformational analysis (SSCA) and heteroduplex analysis (HA) to screen for somatic and germline muta...

  1. Effect of ABCA1-V771M polymorphism on plasma lipid levels and its relationship with coronary atherosclerotic heart disease

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Objective To explore the risk association of ABCA1-V771M polymorphism with coronary heart disease(CHD)in Han nationality in Northwest of China.Methods With case-control study,ABCA1-V771M polymorphism was detected in 204 unrelated Han nationality people in Northwest of China,and all the subjects by coronary angiography were grouped into 106 cases and 98 controls.The genotypes and alleles frequency distribution of ABCA1-V771M polymorphisms were analyzed by PCR-RFLP analysis,and the clinical statistics of seru...

  2. State assignment approach to asynchronous CMOS circuit design

    Science.gov (United States)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  3. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

    Science.gov (United States)

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  4. Small-Scale CMOS Pseudo SRAM Module Design

    Institute of Scientific and Technical Information of China (English)

    李昀; 刘振宇; 韩月秋

    2004-01-01

    An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.

  5. CMOS APS detector characterization for quantitative X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Endrizzi, Marco, E-mail: m.endrizzi@ucl.ac.uk [Dipartimento di Fisica, Università di Siena, Via Roma 56, 53100 Siena (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy); Oliva, Piernicola [Dipartimento di Chimica e Farmacia, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Golosio, Bruno [Sezione di Matematica, Fisica e Ingegneria dell' Informazione, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Delogu, Pasquale [Dipartimento di Fisica “E. Fermi”, Università di Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy)

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11–30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  6. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

    Science.gov (United States)

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P Glenn; Maxwell, Karen L

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  7. A photonics design tool for advanced CMOS nodes

    CERN Document Server

    Alloatti, Luca; Stojanovic, Vladimir; Popovic, Milos; Ram, Rajeev Jagga

    2015-01-01

    Recently, we have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigor that is embodied in the 10000 to 50000 design rules that these designs must comply within advanced CMOS manufacturing. Here, we present a photonic design automation (PDA) tool which allows automatic generation of layouts without design-rule violations. Our tool is written in SKILL, the native language of the mainstream electric design automation (EDA) software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. Removal of design-rule violations - based on Manhattan discretization, Boolean and sizing operations - occurs during data preparation from the initial photonic layers to the final mask...

  8. Novel CMOS readout techniques for uncooled pyroelectric IR FPA

    Science.gov (United States)

    Sun, Tai-Ping; Chin, Yuan-Lung; Chung, Wen-Yaw; Hsiung, Shen-Kan; Chou, Jung-Chuan

    1998-09-01

    Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers (superscript 2) pixel size.

  9. New CMOS Compatible Platforms for Integrated Nonlinear Optical Signal Processing

    CERN Document Server

    Moss, D J

    2014-01-01

    Nonlinear photonic chips have succeeded in generating and processing signals all-optically with performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. This paper reviews some of the recent achievements in CMOS-compatible platforms for nonlinear optics, focusing on amorphous silicon and Hydex glass, highlighting their potential future impact as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  10. Voltage-to-frequency converters CMOS design and implementation

    CERN Document Server

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  11. Design of a CMOS multi-mode GNSS receiver VCO

    Institute of Scientific and Technical Information of China (English)

    Long Qiang; Zhuang Yiqi; Yin Yue; Li Zhenrong

    2012-01-01

    A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multimode global navigation satellite system (GNSS) application,which adopts sigma-delta fractional-N technology in the synthesizer,is presented.The structure is selected to optimize the frequency coverage and tuning linearity,based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells,which cover the global positioning system (GPS) and Beidou (BD) bands.The VCO implemented in the 0.18 μm CMOS process can cover the GPS L1,BD B1,B2 and B3 bands with sufficient margin,and exhibits low phase noise by using this tuning curve linearization technique.The equalized Kvco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

  12. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    Directory of Open Access Journals (Sweden)

    Yue Xu

    2011-06-01

    Full Text Available An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

  13. Design Of A 65 Nm Cmos Comparator With Hysteresis

    Directory of Open Access Journals (Sweden)

    Aleksandr Vasjanov

    2014-05-01

    Full Text Available The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC.

  14. Micro-lens maker equation of a CMOS image sensor

    Science.gov (United States)

    Wu, Yang

    2007-09-01

    The demand of a large resolution CMOS image sensor (CIS) in a small package drives the pixel pitch size down to the neighborhood of 2 μm. Double-micro-lens (ML) structure is a promising technology to obtain the high focusing capability required by such a small pixel. In this work, an optical model of a double-ML is derived from the well-known lens maker equation. This model predicts the critical back focal length (BFL) and the effective focal length (EFL) of the double-ML embedded in the Back-End-Of-The-Line (BEOL) stack. Explained by this model, a design guideline is provided to optimize the amount of light collected by the photo diode area for a good quantum efficiency (QE), which is crucial to the sensitivity of the sensor.

  15. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  16. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    Directory of Open Access Journals (Sweden)

    Wei-Song Wang

    2010-03-01

    Full Text Available Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 ºpA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB.

  17. A 20 MHz CMOS reorder buffer for a superscalar microprocessor

    Science.gov (United States)

    Lenell, John; Wallace, Steve; Bagherzadeh, Nader

    1992-01-01

    Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

  18. Fully integrated current-mode CMOS gated baseline restorer circuits

    International Nuclear Information System (INIS)

    Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of ±40 microA for the gated integrator circuits, ±100 microA for the CFD constant fraction comparator circuit, and ± 160 microA for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at sub millivolt levels, and arming comparator threshold is maintained at a 0--0.48 V level under on-board DAC control

  19. Mutagenesis in yam, Discorea rotundata: Clonal evaluation of M1V3 yam plants

    International Nuclear Information System (INIS)

    Ten thousand plants of M1V3 population of the white guinea yam, Dioscorea rotundata Poir, were evaluated. There was no consistent trends in variations in plant height, number of branches, branching heights and number of leaves of the treated tubers. However, plant height were lower in the irradiated than in the control. The coefficients of variations (C.V.) were higher in the irradiated than in the control populations, indicating wider variations in the former population. Based on yield performance, 110 tubers were selected for preliminary yield trials, Considering that diplontic selection may occur in the irradiated micro-tubers, the experiment will also be carried out using nodal cultures in vitro. (author). 2 tabs

  20. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

    Institute of Scientific and Technical Information of China (English)

    Li Chen; Liao Huai-Lin; Huang Ru; Wang Yang-Yuan

    2008-01-01

    In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.

  1. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II SBIR project a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at sub 1 micro-g...

  2. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This Phase I SBIR effort initiates development of a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at...

  3. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    Science.gov (United States)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  4. Development of radiation hard CMOS active pixel sensors for HL-LHC

    Science.gov (United States)

    Pernegger, Heinz

    2016-07-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  5. CMOS color image sensor with overlaid organic photoconductive layers having narrow absorption band

    Science.gov (United States)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi; Komatsu, Takashi; Saito, Takahiro

    2007-02-01

    At EI2006, we proposed the CMOS image sensor, which was overlaid with organic photoconductive layers in order to incorporate in it large light-capturing ability of a color film owing to its multiple-layer structure, and demonstrated the pictures taken by the trial product of the proposed CMOS image sensor overlaid with an organic layer having green sensitivity. In this study, we have tried to get the optimized spectral sensitivity for the proposed CMOS image sensor by means of the simulation to minimize the color difference between the original Macbeth chart and its reproduction with the spectral sensitivity of the sensor as a parameter. As a result, it has been confirmed that the proposed CMOS image sensor with multiple-layer structure possesses high potential capability in terms of imagecapturing efficiency when it is provided with the optimized spectral sensitivity.

  6. Stripe rust resistance and dough quality of new wheat - Dasypyrum villosum translocation lines T1DL•1V#3S and T1DS•1V#3L and the location of HMW-GS genes.

    Science.gov (United States)

    Zhao, W C; Gao, X; Dong, J; Zhao, Z J; Chen, Q G; Chen, L G; Shi, Y G; Li, X Y

    2015-01-01

    The transfer of agronomically useful genes from wild wheat species into cultivated wheat is one of the most effective approaches to improvement of wheat varieties. To evaluate the transfer of genes from Dasypyrum villosum into Triticum aestivum, wheat quality and disease resistance was evaluated in two new translocation lines, T1DL•1V#3S and T1DS•1V#3L. We examined the levels of stripe rust resistance and dough quality in the two lines, and identified and located the stripe rust resistant genes and high molecular weight glutenin subunit (HMW-GS) genes Glu-V1 of D. villosum. Compared to the Chinese Spring (CS) variety, T1DL•1V#3S plants showed moderate resistance to moderate susceptibility to the stripe rust races CYR33 and Su11-4. However, T1DS•1V#3L plants showed high resistance or immunity to these stripe rusts. The genes for resistance to stripe rust were located on 1VL of D. villosum. In comparison to CS, the dough from T1DS•1V#3L had a significantly shorter developing time (1.45 min) and stable time (1.0 min), a higher weakness in gluten strength (208.5 FU), and a lower farinograph quality index (18). T1DL•1V#3S had a significantly longer developing time (4.2 min) and stable time (5.25 min), a lower weakness in gluten strength (53 FU) and a higher farinograph quality index (78.5). We also found that T1DS•1V#3L had reduced gluten strength and dough quality compared to CS, but T1DL•1V#3S had increased gluten strength and dough quality. The results of SDS-PAGE analysis indicated that Glu-V1 of D. villosum was located on short arm 1VS and long arm 1VL. These results prove that the new translocation lines, T1DS•1V#3L and T1DS•1V#3L, have valuable stripe rust resistance and dough quality traits that will be important for improving wheat quality and resistance in future wheat breeding programs.

  7. Structure of HIV-1 gp120 V1/V2 domain with broadly neutralizing antibody PG9

    Energy Technology Data Exchange (ETDEWEB)

    McLellan, Jason S.; Pancera, Marie; Carrico, Chris; Gorman, Jason; Julien, Jean-Philippe; Khayat, Reza; Louder, Robert; Pejchal, Robert; Sastry, Mallika; Dai, Kaifan; O’Dell, Sijy; Patel, Nikita; Shahzad-ul-Hussan, Syed; Yang, Yongping; Zhang, Baoshan; Zhou, Tongqing; Zhu, Jiang; Boyington, Jeffrey C.; Chuang, Gwo-Yu; Diwanji, Devan; Georgiev, Ivelin; Kwon, Young Do; Lee, Doyung; Louder, Mark K.; Moquin, Stephanie; Schmidt, Stephen D.; Yang, Zhi-Yong; Bonsignori, Mattia; Crump, John A.; Kapiga, Saidi H.; Sam, Noel E.; Haynes, Barton F.; Burton, Dennis R.; Koff, Wayne C.; Walker, Laura M.; Phogat, Sanjay; Wyatt, Richard; Orwenyo, Jared; Wang, Lai-Xi; Arthos, James; Bewley, Carole A.; Mascola, John R.; Nabel, Gary J.; Schief, William R.; Ward, Andrew B.; Wilson, Ian A.; Kwong, Peter D. (UWASH); (NIH); (Scripps); (Duke); (IAVI); (Maryland-MED)

    2012-12-13

    Variable regions 1 and 2 (V1/V2) of human immunodeficiency virus-1 (HIV-1) gp120 envelope glycoprotein are critical for viral evasion of antibody neutralization, and are themselves protected by extraordinary sequence diversity and N-linked glycosylation. Human antibodies such as PG9 nonetheless engage V1/V2 and neutralize 80% of HIV-1 isolates. Here we report the structure of V1/V2 in complex with PG9. V1/V2 forms a four-stranded {beta}-sheet domain, in which sequence diversity and glycosylation are largely segregated to strand-connecting loops. PG9 recognition involves electrostatic, sequence-independent and glycan interactions: the latter account for over half the interactive surface but are of sufficiently weak affinity to avoid autoreactivity. The structures of V1/V2-directed antibodies CH04 and PGT145 indicate that they share a common mode of glycan penetration by extended anionic loops. In addition to structurally defining V1/V2, the results thus identify a paradigm of antibody recognition for highly glycosylated antigens, which - with PG9 - involves a site of vulnerability comprising just two glycans and a strand.

  8. Structures of HIV-1-Env V1V2 with broadly neutralizing antibodies reveal commonalities that enable vaccine design

    Science.gov (United States)

    Gorman, Jason; Soto, Cinque; Yang, Max M.; Davenport, Thaddeus M.; Guttman, Miklos; Bailer, Robert T.; Chambers, Michael; Chuang, Gwo-Yu; DeKosky, Brandon J.; Doria-Rose, Nicole A.; Druz, Aliaksandr; Ernandes, Michael J.; Georgiev, Ivelin S.; Jarosinski, Marissa C.; Joyce, M. Gordon; Lemmin, Thomas M.; Leung, Sherman; Louder, Mark K.; McDaniel, Jonathan R.; Narpala, Sandeep; Pancera, Marie; Stuckey, Jonathan; Wu, Xueling; Yang, Yongping; Zhang, Baoshan; Zhou, Tongqing; Mullikin, James C.; Baxa, Ulrich; Georgiou, George; McDermott, Adrian B.; Bonsignori, Mattia; Haynes, Barton F.; Moore, Penny L.; Morris, Lynn; Lee, Kelly K.; Shapiro, Lawrence; Mascola, John R.; Kwong, Peter D.

    2016-01-01

    Broadly neutralizing antibodies (bNAbs) against HIV-1-Env V1V2 arise in multiple donors. However, atomic-level interactions had only been determined with antibodies from a single donor, making commonalities in recognition uncertain. Here we report the co-crystal structure of V1V2 with antibody CH03 from a second donor and model Env interactions of antibody CAP256-VRC26 from a third. These V1V2-directed bNAbs utilized strand-strand interactions between a protruding antibody loop and a V1V2 strand, but differed in their N-glycan recognition. Ontogeny analysis indicated protruding loops to develop early, with glycan interactions maturing over time. Altogether, the multidonor information suggested V1V2-directed bNAbs to form an ‘extended class’, for which we engineered ontogeny-specific antigens: Env trimers with chimeric V1V2s that interacted with inferred ancestor and intermediate antibodies. The ontogeny-based design of vaccine antigens described here may provide a general means for eliciting antibodies of a desired class. PMID:26689967

  9. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    CERN Document Server

    Benoit, M; de Mendizabal, J. Bilbao; Chen, H; Chen, K; Di Bello, F.A; Ferrere, D; Golling, T; Gonzalez-Sevilla, S; Iacobucci, G; Lanni, F; Liu, H; Meng, L; Miucci, A; Muenstermann, D; Nessi, M; Peric, I; Rimoldi, M; Ristic, B; Pinto, M. Vicente Barrero; Vossebeld, J; Weber, M; Wu, W; Xu, L

    2016-01-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  10. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  11. CMOS detectors for space applications: from R&D to operational program with large volume foundry

    OpenAIRE

    Martin-Gonthier, Philippe; Magnan, Pierre; Corbière, Franck; Rolando, Sébastien; Saint-Pé, Olivier; Breart de Boisanger, M.; Larnaudie, Franck

    2010-01-01

    Nowadays, CMOS image sensors are widely considered for space applications. The use of CIS (CMOS Image sensor) processes has significantly enhanced their performances such as dark current, quantum efficiency and conversion gain. However, in order to fulfil specific space mission requirements, dedicated research and development work has to be performed to address specific detector performance issues. This is especially the case for dynamic range improvement through output voltage swing optim...

  12. Monte Carlo Study of the Dosimetry of Small-Photon Beams Using CMOS Active Pixel Sensors

    OpenAIRE

    Jimenez Spang, F.

    2014-01-01

    Stereotactic radiosurgery is an increasingly common treatment modality that uses very small photon fields. This technique imposes high dosimetric standards and complexities that remain unsolved. In this work the dosimetric performance of CMOS active pixel sensors is presented for the measurement of small-photons beams. A novel CMOS active pixel sensor called Vanilla developed for scientific applications was used. The detector is an array of 520 × 520 pixels on a 25 μm pitch which allows up to...

  13. Design of low-power K-band circuits in CMOS technology

    OpenAIRE

    Ali, Mohammed Kamal Abdelrahman

    2015-01-01

    Die Entwicklung von Millimeterwellen-Transceivern auf Basis moderner CMOS-Technologien steht derzeit weltweit im Fokus von Wissenschaft und Forschung. Dabei sind insbesondere Schaltungen für die ISM-Bänder bei 24 GHz bzw. 60 GHz von Interesse. Beim Entwurf von CMOS-Schaltungen zur Erzeugung und Umsetzung von Frequenzen in diesen Frequenzbereichen ergeben sich zahlreiche unterschiedliche Problemstellungen. So ist einerseits die Performance von spannungsgesteuerten Oszillatoren (VCOs) bei Mill...

  14. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    Science.gov (United States)

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  15. A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing

    OpenAIRE

    Wu, Xinyu; Saxena, Vishal; Zhu, Kehan

    2015-01-01

    Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigur...

  16. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    OpenAIRE

    Amine Bermak; Milin Zhang

    2010-01-01

    Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression...

  17. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    OpenAIRE

    Kiyotaka Sasagawa; Jun Ohta; Takashi Tokuda; Toshihiko Noda

    2010-01-01

    In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-...

  18. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    OpenAIRE

    Shoji Kawahito; Shinya Itoh; Satoshi Aoyama; Sungho Suh

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effec...

  19. Analysis and Optimization of Noise Response for Low-Noise CMOS Image Sensors

    OpenAIRE

    Martin-Gonthier, Philippe; Molina, Romain; Cervantes, Paola; Magnan, Pierre

    2012-01-01

    CMOS image sensors are nowadays widely used in imaging applications and particularly in low light flux applications. This is really possible thanks to a reduction of noise obtained, among others, by the use of pinned photodiode associated with a Correlated Double Sampling readout. It reveals new noise sources which become the major contributors. This paper presents noise measurements on low-noise CMOS image sensor. Image sensor noise is analyzed and optimization is done in order to reach an i...

  20. Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors

    OpenAIRE

    Martin-Gonthier, Philippe; Havard, E.; Magnan, Pierre

    2010-01-01

    Interface and near oxide traps in small gate area MOS transistors (gate area ,1 mm2) lead to RTS noise which implies the emergence of noisy pixels in CMOS image sensors. To reduce this noise, two simple and efficient layout techniques of custom transistors have been imagined. These techniques have been successfully implemented in an image sensor test chip fabricated in a 0.35 mm CMOS image sensor process. Experimental results demonstrate a significant reduction of the noisy pixels for the ...

  1. A Study of a Versatile Low Power CMOS Pulse Generator for Ultra Wideband Radios

    OpenAIRE

    Marsden, Kevin Matthew

    2004-01-01

    Ultra-Wideband (UWB) technologies are at the forefront of wireless communications, offering the possibility to provide extremely high data rate wireless solutions. In addition to high data rate applications, UWB technologies also offer an extremely low cost alternative for many low data rate systems. In this thesis, we describe the design of a CMOS pulse generator for impulse based UWB systems. The structure of our pulse generator is based on the topology of a single tap CMOS power amplifi...

  2. Sinusoidal Frequency Doublers Circuit With Low Voltage + 1.5 Volt CMOS Inverter

    OpenAIRE

    Bancha Burapattanasiri

    2009-01-01

    This paper is present sinusoidal frequency doublers circuit with low voltage + 1.5 volt CMOS inverter. Main structure of circuit has three parts that is CMOS inverter circuit, differential amplifier circuit, and square root circuit. This circuit has designed to receive input voltage and give output voltage use few MOS transistor, easy to understand, non complex of circuit, high precision, low error and low power. The Simulation of circuit has MOS transistor functional in active and saturation...

  3. A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes

    Institute of Scientific and Technical Information of China (English)

    CHENG YuHua

    2008-01-01

    This paper overviews design for manufacturing (DFM) for IC design in nano-CMOS technologies. Process/device issues relevant to the manufacturability of ICs in advanced CMOS technologies will be presented first before an exploration on process/device modeling for DFM is done. The discussion also covers a brief in-troduction of DFM-aware of design flow and EDA efforts to better handle the design-manufacturing interface in very large scale IC design environment.

  4. Effects of Fiber-optic Plates on Image Quality of CMOS X-ray Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Seungman; Han, Jong Chul; Kim, Ho Kyung [Pusan National Univ., Busan (Korea, Republic of)

    2014-05-15

    Radiation damage and its effects on image quality of Complementary metal-oxide-semiconductor (CMOS) devices have also been reported by previous studies. In this regard, most CMOS sensor manufacturers usually employ a fiber-optic plate (FOP) bonded to the CMOS photodiode array. In this configuration, the FOP layer absorbs un-attenuated x-ray photons through an overlaid scintillator; otherwise the un-attenuated photons might be absorbed within the CMOS photodiode array directly. Therefore, it is important to select an optimal thickness of an FOP layer for the long-term use of CMOS sensors providing high-quality images. By comparing the image qualities of the CMOS detector measured without and with FOP, the effects of FOP on the imaging system have been investigated for various x-ray spectra. Measurements showed that the FOP degraded the x-ray sensitivity and resolving power, whereas it enhanced noise properties by absorbing un-attenuated x-ray photons. As a result, the use of FOP enhances the DQE performance which mainly governs x-ray image quality. However, for a low exposure imaging, the use of FOP may not be appropriate because it reduces the light photon transmittance by ∼55% which implies that the image quality could be easily affected by additional electronics noise rather than quantum noise. In this regard, the use of FOP may be more appropriate for industrial applications in which irradiation condition is harsh.

  5. CMOS-sensors for energy-resolved X-ray imaging

    International Nuclear Information System (INIS)

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

  6. Effects of Fiber-optic Plates on Image Quality of CMOS X-ray Detectors

    International Nuclear Information System (INIS)

    Radiation damage and its effects on image quality of Complementary metal-oxide-semiconductor (CMOS) devices have also been reported by previous studies. In this regard, most CMOS sensor manufacturers usually employ a fiber-optic plate (FOP) bonded to the CMOS photodiode array. In this configuration, the FOP layer absorbs un-attenuated x-ray photons through an overlaid scintillator; otherwise the un-attenuated photons might be absorbed within the CMOS photodiode array directly. Therefore, it is important to select an optimal thickness of an FOP layer for the long-term use of CMOS sensors providing high-quality images. By comparing the image qualities of the CMOS detector measured without and with FOP, the effects of FOP on the imaging system have been investigated for various x-ray spectra. Measurements showed that the FOP degraded the x-ray sensitivity and resolving power, whereas it enhanced noise properties by absorbing un-attenuated x-ray photons. As a result, the use of FOP enhances the DQE performance which mainly governs x-ray image quality. However, for a low exposure imaging, the use of FOP may not be appropriate because it reduces the light photon transmittance by ∼55% which implies that the image quality could be easily affected by additional electronics noise rather than quantum noise. In this regard, the use of FOP may be more appropriate for industrial applications in which irradiation condition is harsh

  7. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    Energy Technology Data Exchange (ETDEWEB)

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  8. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2012-06-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

  9. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2011-07-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.

  10. Robust Supersolidity in the V1- V2 Extended Bose-Hubbard Model

    Science.gov (United States)

    Greene, Nicole; Pixley, Jedediah

    2016-05-01

    Motivated by ultra-cold atomic gases with long-range interactions in an optical lattice we study the effects of the next-nearest neighbor interaction on the extended Bose-Hubbard model on a square lattice. Using the variational Gutzwiller approach with a four-site unit cell we determine the ground state phase diagrams as a function of the model parameters. We focus on the interplay of each interaction between the nearest neighbor (V1) , the next-nearest neighbor (V2) , and the onsite repulsion (U). We find various super-solid phases that can be described by one of the ordering wave-vectors (π, 0), (0, π) , and (π, π) . In the limits V1, V2 U we find phases reminiscent of the limit V2 = 0 but with a richer super solid structure. For V1

  11. Analysis of EMCCD and sCMOS readout noise models for Shack-Hartmann wavefront sensor accuracy

    CERN Document Server

    Basden, Alastair

    2015-01-01

    In recent years, detectors with sub-electron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: EMCCD and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models for sCMOS readout noise are optimistic, and recommend that a proper treatment of the sCMOS rms readout noise probability distribution should be considered during instrument performance modelling and development.

  12. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    Science.gov (United States)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  13. High resolution, high bandwidth global shutter CMOS area scan sensors

    Science.gov (United States)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  14. Smart CMOS sensor for wideband laser threat detection

    Science.gov (United States)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  15. Charge collection studies in irradiated HV-CMOS particle detectors

    Science.gov (United States)

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  16. Tracking cancer cell proliferation on a CMOS capacitance sensor chip.

    Science.gov (United States)

    Prakash, Somashekar Bangalore; Abshire, Pamela

    2008-05-15

    We report a novel technique for assessing cell proliferation that employs integrated capacitance sensors for monitoring the growth of anchorage-dependent living cells. The sensors measure substrate coupling capacitances of cells cultured on-chip in a standard in vitro environment. The biophysical phenomenon underlying the capacitive behavior of cells is the counterionic polarization around the insulating cell bodies when exposed to weak, low frequency electric fields. The sensors employ charge sharing for mapping sensed capacitance values in the fF range to output voltage signals. The sensor chip has been fabricated in a commercially available 0.5microm, 2-poly 3-metal CMOS technology. We report experimental results demonstrating sensor response to the adhesion of MDA-MB-231 breast cancer cells followed by their proliferation on the chip surface. On-chip capacitance sensing offers a non-invasive, label-free, easy-to-use, miniaturized technique with real-time monitoring capability for tracking cell proliferation in vitro. PMID:18281207

  17. Capacitively Coupled CMOS VCSEL Driver Circuits for Optical Communication

    Science.gov (United States)

    Kozlov, Victor

    This thesis presents the analysis, design and implementation of a common-cathode capacitively-coupled VCSEL driver in 65nm CMOS intended for short-reach optical interconnects. The driver consists of an AC-coupled high-frequency path and a low-frequency path that provides DC signal components. By increasing the low-frequency path bandwidth by 10 times compared to previous AC-coupled drivers allowed the on-chip coupling capacitor to be reduced to 2.1pF, occupying 3 times less area than prior art. The driver introduces capacitively-coupled two-tap emphasis to equalize the VCSEL's optical response. The VCSEL was modulated with an OMA of up to 5.1dBm and an ER of 9dB, measuring an RMS jitter of 5ps at a data rate of 15Gb/s, which represents the highest OMA and ER achieved in high-speed anode-driving LDDs. The driver could be programmed for a low-power mode, outputting 2.3dBm OMA at power consumption of only 30mW, corresponding to an energy efficiency of 2pJ/bit.

  18. A hierarchical approach to test generation for CMOS VLSI circuits

    Science.gov (United States)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  19. Fabrication of Wireless Micro Pressure Sensor Using the CMOS Process

    Directory of Open Access Journals (Sweden)

    Chienliu Chang

    2009-10-01

    Full Text Available In this study, we fabricated a wireless micro FET (field effect transistor pressure sensor based on the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The wireless micro pressure sensor is composed of a FET pressure sensor, an oscillator, an amplifier and an antenna. The oscillator is adopted to generate an ac signal, and the amplifier is used to amplify the sensing signal of the pressure sensor. The antenna is utilized to transmit the output voltage of the pressure sensor to a receiver. The pressure sensor is constructed by 16 sensing cells in parallel. Each sensing cell contains an MOS (metal oxide semiconductor and a suspended membrane, which the gate of the MOS is the suspended membrane. The postprocess employs etchants to etch the sacrificial layers in the pressure sensor for releasing the suspended membranes, and a LPCVD (low pressure chemical vapor deposition parylene is adopted to seal the etch holes in the pressure. Experimental results show that the pressure sensor has a sensitivity of 0.08 mV/kPa in the pressure range of 0–500 kPa and a wireless transmission distance of 10 cm.

  20. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  1. A CMOS pressure sensor tag chip for passive wireless applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  2. A CMOS pressure sensor tag chip for passive wireless applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  3. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  4. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  5. Variation-aware adaptive voltage scaling for digital CMOS circuits

    CERN Document Server

    Wirnshofer, Martin

    2013-01-01

    Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engine...

  6. A CMOS Smart Thermal Sensor for Biomedical Application

    Science.gov (United States)

    Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

    This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18μm CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180° phase difference input to SDM is also a novel design of this work. As a result, in the range of 0°C to 80°C or body temperature (37±5°C), the inaccuracy is less than ±0.1°C or ±0.05°C respectively with one-point calibration after packaging. The average power consumption is 268.4μW with 1.8V supply voltage.

  7. A CMOS Amperometric System for Multi-Neurotransmitter Detection.

    Science.gov (United States)

    Massicotte, Genevieve; Carrara, Sandro; Di Micheli, Giovanni; Sawan, Mohamad

    2016-06-01

    In vivo multi-target and selective concentration monitoring of neurotransmitters can help to unravel the brain chemical complex signaling interplay. This paper presents a dedicated integrated potentiostat transducer circuit and its selective electrode interface. A custom 2-electrode time-based potentiostat circuit was fabricated with 0.13 μm CMOS technology and provides a wide dynamic input current range of 20 pA to 600 nA with 56 μ W, for a minimum sampling frequency of 1.25 kHz. A multi-working electrode chip is functionalized with carbon nanotubes (CNT)-based chemical coatings that offer high sensitivity and selectivity towards electroactive dopamine and non-electroactive glutamate. The prototype was experimentally tested with different concentrations levels of both neurotransmitter types, and results were similar to measurements with a commercially available potentiostat. This paper validates the functionality of the proposed biosensor, and demonstrates its potential for the selective detection of a large number of neurochemicals. PMID:26761882

  8. CMOS indoor light energy harvesting system for wireless sensing applications

    CERN Document Server

    Ferreira Carvalho, Carlos Manuel

    2016-01-01

    This book discusses in detail the CMOS implementation of energy harvesting.  The authors describe an integrated, indoor light energy harvesting system, based on a controller circuit that dynamically and automatically adjusts its operation to meet the actual light circumstances of the environment where the system is placed.  The system is intended to power a sensor node, enabling an autonomous wireless sensor network (WSN). Although designed to cope with indoor light levels, the system is also able to work with higher levels, making it an all-round light energy harvesting system.  The discussion includes experimental data obtained from an integrated manufactured prototype, which in conjunction with a photovoltaic (PV) cell, serves as a proof of concept of the desired energy harvesting system.  ·         Discusses several energy sources which can be used to power energy harvesting systems and includes an overview of PV cell technologies  ·         Includes an introduction to voltage step-...

  9. MEMS Very Low Capacitive Pressure Sensor Based on CMOS Process

    International Nuclear Information System (INIS)

    The CMOS standard process with advantage of simplicity in term of design and fabrication process compatibility has triggered the invention of MEMS very low capacitive pressure sensor, (MEMS-VLCPS). In this paper the development of the whole structure of MEMS-VLCPS that involves the design simulation, fabrication and testing is described. The novelty of this work lies in the design and fabrication process itself. A new technique in fabricating thin sensor membrane of VLCPS using seal-off techniques is also presented. The physical structure of the membrane consists of parallel plate. The top plate acts as the flexible electrode membrane and the bottom plate acts as the counter electrode membrane. Both plates are separated by absolute air gap with fixed end at both sides. As a result, it was found that the etch-opening holes of 0.8 μm and seal-off thickness of 4000 Angstrom gave the optimum sealing surface. The percentage of relative capacitance change is extracted from the reference capacitance measurement. Air gap thickness of 0.3 μm gives the highest percentage of PRCC showing that smaller air gap thickness provides a larger change in capacitance value. (author)

  10. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  11. Novel integrated CMOS pixel structures for vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  12. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Directory of Open Access Journals (Sweden)

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  13. Optimization of ultra-low-power CMOS transistors

    CERN Document Server

    Stockinger, M

    2000-01-01

    chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/mu m. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 mu m and 0.1 mu m devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for its superior drive performance are given. It is compared to already known device structures and practical alternatives are suggested with respect to its manufacturability. In a second optimization study the gate delay times of complete CMOS inverters are minimized. Both the doping profiles of the NMOS and PMOS transistors are optimized at the same time which results again in PCD devices. The inverter speeds are improved by 54 % and 97 % for the 0.25 mu m and 0.1 mu m devices, respectively. Ultra-low-power CMO...

  14. Pandemic A/H1N1v influenza 2009 in hospitalized children: a multicenter Belgian survey

    Directory of Open Access Journals (Sweden)

    Blumental Sophie

    2011-11-01

    Full Text Available Abstract Background During the 2009 influenza A/H1N1v pandemic, children were identified as a specific "at risk" group. We conducted a multicentric study to describe pattern of influenza A/H1N1v infection among hospitalized children in Brussels, Belgium. Methods From July 1, 2009, to January 31, 2010, we collected epidemiological and clinical data of all proven (positive H1N1v PCR and probable (positive influenza A antigen or culture pediatric cases of influenza A/H1N1v infections, hospitalized in four tertiary centers. Results During the epidemic period, an excess of 18% of pediatric outpatients and emergency department visits was registered. 215 children were hospitalized with proven/probable influenza A/H1N1v infection. Median age was 31 months. 47% had ≥ 1 comorbid conditions. Febrile respiratory illness was the most common presentation. 36% presented with initial gastrointestinal symptoms and 10% with neurological manifestations. 34% had pneumonia. Only 24% of the patients received oseltamivir but 57% received antibiotics. 10% of children were admitted to PICU, seven of whom with ARDS. Case fatality-rate was 5/215 (2%, concerning only children suffering from chronic neurological disorders. Children over 2 years of age showed a higher propensity to be admitted to PICU (16% vs 1%, p = 0.002 and a higher mortality rate (4% vs 0%, p = 0.06. Infants less than 3 months old showed a milder course of infection, with few respiratory and neurological complications. Conclusion Although influenza A/H1N1v infections were generally self-limited, pediatric burden of disease was significant. Compared to other countries experiencing different health care systems, our Belgian cohort was younger and received less frequently antiviral therapy; disease course and mortality were however similar.

  15. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    Science.gov (United States)

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 × 63 mm2 silicon area containing 16 million pixels arranged in a 4K × 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 × 2 or 4 × 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 × 1 or 2 × 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 μm standard CMOS process.

  16. Damage analysis of CMOS electro-optical imaging system by a continuous wave laser

    Science.gov (United States)

    Yoon, Sunghee; Jhang, Kyung-Young; Shin, Wan-Soon

    2016-08-01

    EOIS (electro-optical imaging system) is vulnerable to laser beam because EOIS focuses the incident laser beam onto the image sensor via lens module. Accordingly, the laser-induced damage of EOIS is necessary to be identified for the counter-measure against the laser attack. In this study, the damage of CMOS EOIS and image sensor induced by CW (continuous wave) NIR (near infrared) laser was experimentally investigated. When the laser was emitted to CMOS EOIS, a temporary damage was occurred first such as flickering or dazzling and then a permanent damage was followed as the increase of laser irradiance and irradiation time. If the EIOS is composed of the optical equipment made of heatresistant material, laser beam can penetrate the lens module of EOIS without melting the lens and lens guide. Thus, it is necessary to investigate the damage of CMOS image sensor by the CW laser and we performed experimentally investigation of damage on the CMOS image sensor similar with case of CMOS EOIS. And we analyzed the experiment results by using OM (optical microscopy) and check the image quality through tomography. As the increase of laser irradiance and irradiation time, the permanent damage such as discoloration and breakdown were sequentially appeared.

  17. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    Directory of Open Access Journals (Sweden)

    Zujun Wang

    2014-07-01

    Full Text Available The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD, dark signal spike, dark signal non-uniformity (DSNU, noise (VN, saturation output signal voltage (VS, and dynamic range (DR versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  18. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    International Nuclear Information System (INIS)

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN), saturation output signal voltage (VS), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike

  19. An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Ashish Raghuwanshi

    2013-09-01

    Full Text Available One of the key issues in CMOS circuit design is the large amount of power being dissipated in the circuits. Energy recovering circuitry based on adiabatic principles is a relatively new technique used to implement low power dissipating circuits. By recycling the charge at capacitive nodes in the circuit, adiabatic logic families can achieve very low power dissipation. In this paper we had design and simulate the Inverter, Two-Input Nand gate, Two-Input Nor gate, Two-Input Xor gate, 2:1 Multiplexer on the basis of CMOS Logic and Adiabatic Switching logic using 180nm CMOS technology in Cadence design environment. Two adiabatic families are used in this work, Oneis the Positive Feedback Adiabatic Logic (PFAL and the other is the Efficient Charge Recovery Logic (ECRL Finally, the analysis of the average dynamic power dissipation with respect to the frequency and the load capacitance was done to show the amount of power dissipated by the CMOS, PFAL and ECRL family. The results shows that power saving of adiabatic circuit can reach more than 90% as compare to conventional static CMOS logic

  20. CMOS图像传感器及其应用%CMOS Image Sensor and Its Application

    Institute of Scientific and Technical Information of China (English)

    谈新权; 何永泰

    2001-01-01

    CMOS图像传感器是近年来市场上出现的一种新的摄像器件。文中对CMOS图像传感器与CCD图像传感器作了比较。分析了CMOS像传感器的工作原理及其优越的性能。提供了CMOS像传感器的应用实例。CMOS成像器在红外成像领域具有广阔的应用前景。%CMOS image sensor is a new solid-state pickup element.This article compares the performance of a CMOS image sensor with CCD image sensor.The operation principle and significant performance advantages of CMOS image sensor are analysed.An application example of CMOS image sensor is given in the article.CMOS image sensor has the prospects of application in the infrared imaging.

  1. Electronic dosimetry and neutron metrology by CMOS active pixel sensor

    International Nuclear Information System (INIS)

    This work aims at demonstrating the possibility to use active pixel sensors as operational neutron dosemeters. To do so, the sensor that has been used has to be γ-transparent and to be able to detect neutrons on a wide energy range with a high detection efficiency. The response of the device, made of the CMOS sensor MIMOSA-5 and a converter in front of the sensor (polyethylene for fast neutron detection and 10B for thermal neutron detection), has been compared with Monte Carlo simulations carried out with MCNPX and GEANT4. These codes have been before-hand validated to check they can be used properly for our application. Experiments to characterize the sensor have been performed at IPHC and at IRSN/LMDN (Cadarache). The results of the sensor irradiation to photon sources and mixed field (241AmBe source) show the γ-transparency of the sensor by applying an appropriate threshold on the deposited energy (around 100 keV). The associated detection efficiency is satisfactory with a value of 10-3, in good agreement with MCNPX and GEANT4. Other features of the device have been tested with the same source, like the angular response. The last part of this work deals with the detection of thermal neutrons (eV-neutrons). Assays have been done in Cadarache (IRSN) with a 252Cf source moderated with heavy water (with and without cadmium shell). Results asserted a very high detection efficiency (up to 6*10-3 for a pure 10B converter) in good agreement with GEANT4. (author)

  2. sCMOS detector for imaging VNIR spectrometry

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  3. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    Science.gov (United States)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  4. Silicides and germanides for nano-CMOS applications

    Energy Technology Data Exchange (ETDEWEB)

    Kittl, J.A. [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)], E-mail: kittlj@imec.be; Opsomer, K.; Torregiani, C.; Demeurisse, C.; Mertens, S.; Brunco, D.P.; Van Dal, M.J.H.; Lauwers, A. [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)

    2008-12-05

    An overview of silicides and germanides for nano-CMOS applications is presented. The historical evolution describing the migration from the use of Ti silicide to Co silicide to Ni silicide as contacting material is first discussed. These changes in silicide material were mainly motivated by the inability to form the target low resistivity silicide phase in small structures due to low nucleation density. This issue was found first for the low resistivity C54 TiSi{sub 2} at linewidths below 200 nm and later for the low resistivity CoSi{sub 2}, at linewidths below 40 nm. A detailed description of scalability and thermal stability issues for NiSi is then presented. No nucleation issues were found in small structures for NiSi, which grows by diffusion or interface limited kinetics with Ni as main moving species. However, silicidation can be excessive in small structures due to Ni diffusion from surrounding areas, resulting in thicker films than targeted in small devices. This can be controlled by using a silicidation process with two rapid thermal processing steps, the first one to control the amount of Ni reacted and the second one to convert the silicide to the target low resistivity monosilicide phase. One of the main issues for applications of NiSi is its low thermal stability: thin NiSi films agglomerate at relatively low temperatures. The process window and thermal stability of Ni and Pt-based films reacted with Si, Si:Ge and Si:C substrates is reviewed. Addition of Ge is shown to degrade thermal stability while addition of C or Pt improves it. Contact resistivity considerations and implementation of dual band-edge silicides are discussed, as well as promising results for the extension of Ni-based silicides to future nodes. Finally a brief overview of germanides is presented discussing NiGe and PdGe as main candidates.

  5. Designing of RF Single Balanced Mixer with a 65 nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

    Directory of Open Access Journals (Sweden)

    Raja Mahmou

    2012-01-01

    Full Text Available The present work consists of designing a Single Balanced Mixer (SBM with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

  6. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    Energy Technology Data Exchange (ETDEWEB)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p/sup +/n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience.

  7. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p+n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  8. Noise Eliminating Technologies in CMOS Image Sensors%CMOS图像传感器的消噪技术

    Institute of Scientific and Technical Information of China (English)

    梁红玉; 朱宇明; 徐宏; 白培康

    2000-01-01

    Aim To introduce the noise eliminating technologies in CMOS image sensors. Methods The advantages and disadvantages of CMOS image sensors and CCD image sensors are compared. The methods of the noise eliminating technologies of CMOS image sensors are analyzed. The actuality and trend of development are introduced. Results At present these technologies can eliminate efficiently noises and improve signal noise rate. Conclusion The development trend of the noise eliminating technologies of CMOS image sensors is foreseen. Key words: % 目的 介绍 CMOS 图像传感器的消噪技术. 方法 比较了 CMOS 图像传感器与 CCD 图像传感器的优缺点, 分析了 CMOS 图像传感器消噪技术的方法, 介绍了其研制现状及发展趋势. 结果 目前采用的消噪技术有效地降低了噪声, 提高了信噪比. 结论 预见了 CMOS 图像传感器消噪技术的发展趋势.

  9. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process. PMID:27337723

  10. Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE

    Directory of Open Access Journals (Sweden)

    Mugdha Sathe

    2014-07-01

    Full Text Available According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.

  11. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    Directory of Open Access Journals (Sweden)

    Martin D. Dawson

    2009-11-01

    Full Text Available We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM. This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented.

  12. 2D and 3D CMOS MAPS with high performance pixel-level signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Traversi, Gianluca, E-mail: gianluca.traversi@unibg.i [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Gaioni, Luigi; Manghisoni, Massimo [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Ratti, Lodovico [University of Pavia and INFN Pavia (Italy); Re, Valerio [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy)

    2011-02-01

    Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

  13. TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

    CERN Document Server

    Buckland, Matthew Daniel

    2016-01-01

    The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

  14. A novel monolithic ultraviolet image sensor based on a standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Guike; Feng Peng; Wu Nanjian

    2011-01-01

    We present a monolithic ultraviolet (UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists ofa CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16 × 16 image sensor prototype chip is implemented in a 0.18 μm standard CMOS logic process.The pixel and image sensor were measured.Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

  15. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Directory of Open Access Journals (Sweden)

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  16. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    Directory of Open Access Journals (Sweden)

    S. M. Rezaul Hasan

    2002-01-01

    Full Text Available This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

  17. An approach to the optical interconnect made in standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Yu Changliang; Mao Luhong; Xiao Xindong; Xie Sheng; Zhang Shilin

    2009-01-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide,metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  18. Implementation of large area CMOS image sensor module using the precision align inspection

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo [Radiation Imaging Technology Center, JBTP, Iksan (Korea, Republic of); Lee, Kyung Yong; Kim, Jin Soo [Nano Sol-Tech INC., Iksan (Korea, Republic of); Kim, Myung Soo; Cho, Gyu Seong [Dept. of Nuclear and Quantum Engineering, KAIST, Daejeon (Korea, Republic of)

    2014-12-15

    This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

  19. High efficiency grating couplers based on shared process with CMOS MOSFETs

    Institute of Scientific and Technical Information of China (English)

    Qiu Chao; Sheng Zhen; Li Le; Albert Pang; Wu Ai-Min; Wang Xi; Zou Shi-Chang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers.In this work,a high-efficiency and complementary metal-oxide-semiconductor (CMOS) process compatible grating coupler is proposed.The poly-Si layer used as a gate in the CMOS metal-oxide-semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler,which greatly enhances its coupling efficiency.With optimal structure parameters,a coupling efficiency can reach as high as ~ 70% at a wavelength of 1550 nm as indicated by simulation.From the angle of fabrication,all masks and etching steps are shared between MOSFETs and grating couplers,-thereby making the high performance grating couplers easily integrated with CMOS circuits.Fabrication errors such as alignment shift are also simulated,showing that the device is quite tolerant in fabrication.

  20. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    Science.gov (United States)

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  1. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Energy Technology Data Exchange (ETDEWEB)

    Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  2. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  3. Full-Wave Rectifier Circuit Responding in Linear Wide Range by Two Stage CMOS

    Directory of Open Access Journals (Sweden)

    Sanchaiya Pasomkusolsil

    2009-10-01

    Full Text Available This article is present full-wave rectifier circuit responding in linear wide range by two stage CMOS by 0.5 mm CMOS technology, + 1.5 V low voltage, operation input receiver and output current mode, it responded operational at high frequency. The components of structure circuit are two stage CMOS circuit and current mirror circuit. The performances of the proposed circuit are investigated through PSpice. They show that the proposed circuit can function as maximum input current ranges 300 mAp-p, responding at maximum frequency ranges 10 MHz, high precision, low power, non precision zero-crossing output signal, and uses a little of transistors. Furthermore, the circuit is able to generate square signal, it is operating at voltage mode but without modification or elaboration to structure of circuit.

  4. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Institute of Scientific and Technical Information of China (English)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  5. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  6. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    Science.gov (United States)

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-01

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process. PMID:25782697

  7. Investigation of III-V semiconductor heterostructures for post-Si-CMOS applications

    Science.gov (United States)

    Bhatnagar, Kunal

    Silicon complementary metal-oxide-semiconductor (CMOS) technology in the past few decades has been driven by aggressive device scaling to increase performance, reduce cost and lower power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. As we move towards advanced technology nodes, materials innovation and physical architecture are becoming the primary enabler for performance enhancement in CMOS technology rather than scaling. One class of materials that can potentially result in improved electrical performance are III-V semiconductors, which are ideal candidates for replacing the channel in Si CMOS owing to their high electron mobilities and capabilities for band-engineering. This work is aimed towards the growth and characterization of III-V semiconductor heterostructures and their application in post-Si-CMOS devices. The two main components of this study include the integration of III-V compound semiconductors on silicon for tunnel-junction Esaki diodes, and the investigation of carrier transport properties in low-power III-V n-channel FETs under uniaxial strain for advanced III-V CMOS solutions. The integration of III-V compound semiconductors with Si can combine the cost advantage and maturity of the Si technology with the superior performance of III-V materials. We have demonstrated high quality epitaxial growth of GaAs and GaSb on Si (001) wafers through the use of various buffer layers including AlSb and crystalline SrTiO3. These GaSb/Si virtual substrates were used for the fabrication and characterization of InAs/GaSb broken-gap Esaki-tunnel diodes as a possible solution for heterojunction Tunnel-FETs. In addition, the carrier transport properties of InAs channels were evaluated under uniaxial strain for the potential use of strain solutions in III-V CMOS.

  8. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  9. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  10. Design and experimental demonstration of low-power CMOS magnetic cell manipulation platform using charge recycling technique

    Science.gov (United States)

    Niitsu, Kiichi; Yoshida, Kohei; Nakazato, Kazuo

    2016-03-01

    We present the world’s first charge-recycling-based low-power technique of complementary metal-oxide-semiconductor (CMOS) magnetic cell manipulation. CMOS magnetic cell manipulation associated with magnetic beads is a promissing tool for on-chip biomedical-analysis applications such as drug screening because CMOS can integrate control electronics and electro-chemical sensors. However, the conventional CMOS cell manipulation requires considerable power consumption. In this work, by concatenating multiple unit circuits and recycling electric charge among them, power consumption is reduced by a factor of the number of the concatenated unit circuits (1/N). For verifying the effectiveness, test chip was fabricated in a 0.6-µm CMOS. The chip successfully manipulates magnetic microbeads with achieving 49% power reduction (from 51 to 26.2 mW). Even considering the additional serial resistance of the concatenated inductors, nearly theoretical power reduction effect can be confirmed.

  11. Measurements on HV-CMOS active sensors after irradiation to HL-LHC fluences

    Science.gov (United States)

    Ristic, B.

    2015-04-01

    During the long shutdown (LS) 3 beginning 2022 the LHC will be upgraded for higher luminosities pushing the limits especially for the inner tracking detectors of the LHC experiments. In order to cope with the increased particle rate and radiation levels the ATLAS Inner Detector will be completely replaced by a purely silicon based one. Novel sensors based on HV-CMOS processes prove to be good candidates in terms of spatial resolution and radiation hardness. In this paper measurements conducted on prototypes built in the AMS H18 HV-CMOS process and irradiated to fluences of up to 2·1016 neq cm-2 are presented.

  12. Use of CMOS imagers to measure high fluxes of charged particles

    Science.gov (United States)

    Servoli, L.; Tucceri, P.

    2016-03-01

    The measurement of high flux charged particle beams, specifically at medical accelerators and with small fields, poses several challenges. In this work we propose a single particle counting method based on CMOS imagers optimized for visible light collection, exploiting their very high spatial segmentation (> 3 106 pixels/cm2) and almost full efficiency detection capability. An algorithm to measure the charged particle flux with a precision of ~ 1% for fluxes up to 40 MHz/cm2 has been developed, using a non-linear calibration algorithm, and several CMOS imagers with different characteristics have been compared to find their limits on flux measurement.

  13. Compact all-CMOS spatiotemporal compressive sensing video camera with pixel-wise coded exposure.

    Science.gov (United States)

    Zhang, Jie; Xiong, Tao; Tran, Trac; Chin, Sang; Etienne-Cummings, Ralph

    2016-04-18

    We present a low power all-CMOS implementation of temporal compressive sensing with pixel-wise coded exposure. This image sensor can increase video pixel resolution and frame rate simultaneously while reducing data readout speed. Compared to previous architectures, this system modulates pixel exposure at the individual photo-diode electronically without external optical components. Thus, the system provides reduction in size and power compare to previous optics based implementations. The prototype image sensor (127 × 90 pixels) can reconstruct 100 fps videos from coded images sampled at 5 fps. With 20× reduction in readout speed, our CMOS image sensor only consumes 14μW to provide 100 fps videos.

  14. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    OpenAIRE

    Valente, V.; Demosthenous, A.

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) ...

  15. Analytical Frequency-Dependent Model for Transmission Lines on RF-CMOS Lossy Substrates

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    Transmission lines (T-Lines) are widely used in millimeter wave applications on silicon-based complementary metal-oxide semiconductor (CMOS) technology. Accurate modeling of T-lines to capture the related electrical effects has, therefore, become increasingly important. This paper describes a method to model the capacitance and conductance of T-Lines on CMOS multilayer, lossy substrates based on conformal mapping, and region subdivision. Tests show that the line parameters (per unit length) obtained by the method are frequency dependent and very accurate. The method is also suitable for parallel multiconductor interconnect modeling for high frequency circuits.

  16. Characterization of an x-ray hybrid CMOS detector with low interpixel capacitive crosstalk

    OpenAIRE

    Griffith, Christopher V.; Bongiorno, Stephen D.; Burrows, David N.; Falcone, Abraham D.; Prieskorn, Zachary R.

    2012-01-01

    We present the results of x-ray measurements on a hybrid CMOS detector that uses a H2RG ROIC and a unique bonding structure. The silicon absorber array has a 36{\\mu}m pixel size, and the readout array has a pitch of 18{\\mu}m; but only one readout circuit line is bonded to each 36x36{\\mu}m absorber pixel. This unique bonding structure gives the readout an effective pitch of 36{\\mu}m. We find the increased pitch between readout bonds significantly reduces the interpixel capacitance of the CMOS ...

  17. Characterization of an x-ray hybrid CMOS detector with low interpixel capacitive crosstalk

    CERN Document Server

    Griffith, Christopher V; Burrows, David N; Falcone, Abraham D; Prieskorn, Zachary R

    2012-01-01

    We present the results of x-ray measurements on a hybrid CMOS detector that uses a H2RG ROIC and a unique bonding structure. The silicon absorber array has a 36{\\mu}m pixel size, and the readout array has a pitch of 18{\\mu}m; but only one readout circuit line is bonded to each 36x36{\\mu}m absorber pixel. This unique bonding structure gives the readout an effective pitch of 36{\\mu}m. We find the increased pitch between readout bonds significantly reduces the interpixel capacitance of the CMOS detector reported by Bongiorno et al. 2010 and Kenter et al. 2005.

  18. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  19. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  20. Highly Unidirectional Uniform Optical Grating Couplers, Fabricated in Standard 45nm SOI-CMOS Foundry Process

    CERN Document Server

    Urošević, Stevan Lj

    2014-01-01

    This paper defines new structures of highly unidirectional uniform optical grating couplers which are all within constraints of the standard 45nm SOI-CMOS foundry process. Analysis in terms of unidirectivity and coupling efficiency is done. Maximum achieved unidirectivity (power radiation in one direction) is 98%. Unidirectional uniform gratings are fabricated in the standard 45nm SOI-CMOS foundry process. These gratings are measured and compared, using the new method of comparison, with typical bidirectional uniform gratings fabricated in the same process, in terms of coupling efficiency (in this case unidirectivity) with the standard singlemode fiber. For both types of gratings spectrum is given, measured with optical spectrum analyzer.