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Implementation of Accelerated Beam-Specific Matched-Filter-Based Optical Alignment  

Energy Technology Data Exchange (ETDEWEB)

Accurate automated alignment of laser beams in the National Ignition Facility (NIF) is essential for achieving extreme temperature and pressure required for inertial confinement fusion. The alignment achieved by the integrated control systems relies on algorithms processing video images to determine the position of the laser beam images in real-time. Alignment images that exhibit wide variations in beam quality require a matched-filter algorithm for position detection. One challenge in designing a matched-filter based algorithm is to construct a filter template that is resilient to variations in imaging conditions while guaranteeing accurate position determination. A second challenge is to process the image as fast as possible. This paper describes the development of a new analytical template that captures key recurring features present in the beam image to accurately estimate the beam position under good image quality conditions. Depending on the features present in a particular beam, ...

2009-01-29

2

Internal interface for RFC muon trigger electronics at CMS experiment  

CERN Document Server

The paper describes design and practical realization of an internal communication layer referred to as the Internal Interface (II). The system was realized for the RFC Muon Trigger of the CMS experiment. Fully automatic implementation of the communication layer is realized in the FPGA chips and in the control software. The methodology of implementation was presented in the description form of the interface structure from the sides of hardware and software. The examples of the communication layer realizations were given for the RFC Muon Trigger.

2004-01-01

3

Fast Implementation of Matched Filter Based Automatic Alignment Image Processing  

Energy Technology Data Exchange (ETDEWEB)

Video images of laser beams imprinted with distinguishable features are used for alignment of 192 laser beams at the National Ignition Facility (NIF). Algorithms designed to determine the position of these beams enable the control system to perform the task of alignment. Centroiding is a common approach used for determining the position of beams. However, real world beam images suffer from intensity fluctuation or other distortions which make such an approach susceptible to higher position measurement variability. Matched filtering used for identifying the beam position results in greater stability of position measurement compared to that obtained using the centroiding technique. However, this gain is achieved at the expense of extra processing time required for each beam image. In this work we explore the possibility of using a field programmable logic array (FPGA) to speed up these computations. The results indicate a performance improvement of 20 using the ...

2008-04-02

4

A Novel VLSI Architecture of Fixed-complexity Sphere Decoder  

CERN Document Server

Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13{\\mu}m CMOS technology. The proposed solution is much more economical compared with the existing ...

2010-01-01

5

Circuit design of PMT readout module for detector prototype of Daya Bay reactor neutrino experiment  

International Nuclear Information System (INIS)

This paper describes the design of PMT readout module for detector prototype of Daya Bay Reactor Neutrino Experiment. According to the design requirements of the readout module, the basic structure of the readout module is discussed. This paper also discusses how to realize the charge measurement and time measurement and data processing using a high performance FPGA. The DAQ system including three readout modules and one trigger module are well commissioned and doing data taking now. (authors)

2006-10-21

6

The Gigabit Link Interface Board (GLIB), a flexible system for the evaluation and use of GBT-based optical links  

International Nuclear Information System (INIS)

The Gigabit Link Interface Board (GLIB) is an evaluation platform and an easy entry point for users of high speed optical links in high energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory to control, triggering and data acquisition from remote modules in beam or irradiation tests. The GLIB is an FPGA-based Advanced Mezzanine Card (AMC) conceived to serve a small and simple system residing either inside a Micro Telecommunications Computing Architecture (?TCA) crate, or on a bench with a link to a PC. This paper presents the architecture of the GLIB, its features as well as examples of its use in different setups.

2010-11-01

7

Implementation of an OFDM underwater acoustic communication system on an underwater vehicle with multiprocessor structure  

British Library Electronic Table of Contents (United Kingdom)

Orthogonal frequency division multiplexing (OFDM) can fully use the frequency band and transmit data at high speeds. The ADSP-TS101 is a high performance digital signal processor (DSP) with good properties that include parallel processing and a high speed. Aimed at the real-time processing requirement of the OFDM algorithm, an underwater acoustic communication system with real-time processing capability is carried out. The system is mainly composed of multiple ADSP-TS101s, a multi-channel synchronous sample module and a field programmable gate array (FPGA) chip. The multiprocessor structure is made up of a cluster/data flow associated multiprocessing parallel processing structure as the operation kernel, and a multi-channel synchronous sample module is designed to realize no phase warp amo...

2007-01-01

8

Hardware standardization for embedded systems  

International Nuclear Information System (INIS)

Reactor Control Division (RCnD) has been one of the main designers of safety and safety related systems for power reactors. These systems have been built using in-house developed hardware. Since the present set of hardware was designed long ago, a need was felt to design a new family of hardware boards. A Working Group on Electronics Hardware Standardization (WG-EHS) was formed with an objective to develop a family of boards, which is general purpose enough to meet the requirements of the system designers/end users. RCnD undertook the responsibility of design, fabrication and testing of boards for embedded systems. VME and a proprietary I/O bus were selected as the two system buses. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented on FPGA/CPLD using VHDL. This paper outlines the various boards that have been developed with a brief description. (author)

2010-02-01

9

ETHERNET BASED EMBEDDED SYSTEM FOR FEL DIAGNOSTICS AND CONTROLS  

Energy Technology Data Exchange (ETDEWEB)

An Ethernet based embedded system has been developed to upgrade the Beam Viewer and Beam Position Monitor (BPM) systems within the free-electron laser (FEL) project at Jefferson Lab. The embedded microcontroller was mounted on the front-end I/O cards with software packages such as Experimental Physics and Industrial Control System (EPICS) and Real Time Executive for Multiprocessor System (RTEMS) running as an Input/Output Controller (IOC). By cross compiling with the EPICS, the RTEMS kernel, IOC device supports, and databases all of these can be downloaded into the microcontroller. The first version of the BPM electronics based on the embedded controller was built and is currently running in our FEL system. The new version of BPM that will use a Single Board IOC (SBIOC), which integrates with an Field Programming Gate Array (FPGA) and a ColdFire embedded microcontroller, is presently under development. The new system has the features of a low cost IOC, an open ...

2006-10-24