Dynamic Efficiency Measurements for Irradiated ATLAS Pixel Single Chip Modules

CERN Document Server

Pfaff, Mike; Grosse-Knetter, Jorn

2011-01-01

The ATLAS pixel detector is the innermost subdetector of the ATLAS experiment. Due to this, the pixel detector has to be particularly radiation hard. In this diploma thesis effects on the sensor and the electronics which are caused by irradiation are examined. It is shown how the behaviour changes between an unirradiated sample and a irradiated sample, which was treated with the same radiation dose that is expected at the end of the lifetime of ATLAS. For this study a laser system, which is used for dynamic efficiency measurements was constructed. Furthermore, the behaviour of the noise during the detection of a particle was evaluated studied.

Initial Measurements on Pixel Detector Modules for the ATLAS Upgrades

CERN Document Server

Gallrapp, C; The ATLAS collaboration

2011-01-01

Delicate conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel Detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming Pixel Detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation for silicon planar and 3D pixel sensors, which give a first impression on the charge collection properties of the different sensor technologies, are presented.

Upgrade of ATLAS ITk Pixel Detector

CERN Document Server

Huegging, Fabian; The ATLAS collaboration

2017-01-01

The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current inner detector will be replaced with an entirely-silicon inner tracker (ITk) which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation levels are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors and low mass global and local support structures. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the ITk ATLAS Pixel detector developments as well as different layout options will be reviewed.

Operational Experience with the ATLAS Pixel Detector at LHC

CERN Document Server

Keil, M

2013-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus crucial for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via front-end chips bump-bonded to 1744 n-on-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, detector performance and measurements of radiation damage. The detector performance is excellent: more than 95% of the pixels are operational, noise occupancy and hit efficiency exceed the des...

Initial Measurements On Pixel Detector Modules For The ATLAS Upgrades

CERN Document Server

Gallrapp, C; The ATLAS collaboration

2011-01-01

Sophisticated conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming pixel detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation, which give a first impression on the charge collection properties of the different sensor technologies are presented.

ATLAS ITk Pixel detector

CERN Document Server

Gemme, Claudia; The ATLAS collaboration

2016-01-01

The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

FE-I4 pixel chip characterization with USBpix3 test system

Energy Technology Data Exchange (ETDEWEB)

Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

2015-07-01

The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

Studies for the detector control system of the ATLAS pixel at the HL-LHC

International Nuclear Information System (INIS)

Püllen, L; Becker, K; Boek, J; Kersten, S; Kind, P; Mättig, P; Zeitnitz, C

2012-01-01

In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

Vertex measurement at a hadron collider. The ATLAS pixel detector

International Nuclear Information System (INIS)

Grosse-Knetter, J.

2008-03-01

The ATLAS Pixel Detector is the innermost layer of the ATLAS tracking system and will contribute significantly to the ATLAS track and vertex reconstruction. The detector consists of identical sensor-chip-hybrid modules, arranged in three barrels in the centre and three disks on either side for the forward region. The position of the Pixel Detector near the interaction point requires excellent radiation hardness, fast read-out, mechanical and thermal robustness, good long-term stability, all combined with a low material budget. The new design concepts used to meet the challenging requirements are discussed with their realisation in the Pixel Detector, followed by a description of a refined and extensive set of measurements to assess the detector performance during and after its construction. (orig.)

SEU tolerant memory design for the ATLAS pixel readout chip

International Nuclear Information System (INIS)

Menouni, M; Barbero, M; Breugnon, P; Fougeron, D; Gensolen, F; Arutinov, D; Backhaus, M; Gonella, L; Hemperek, T; Karagounis, M; Beccherle, R; Darbo, G; Caminada, L; Dube, S; Fleury, J; Garcia-Sciveres, M; Gnani, D; Jensen, F; Gromov, V; Kluit, R

2013-01-01

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

2004-01-01

A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

Operational Experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Keil, M; The ATLAS collaboration

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including calibration procedures, timing optimization and detector performance. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit efficiency e...

Operational Experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Keil, M; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

Operational experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Hirschbuehl, D; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.7% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

Operational experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Lapoire, C; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

Operational Experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Lapoire, C; The ATLAS collaboration

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as B-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification.

Operational Experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Keil, M

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, timing optimization and detector performance. The detector performance is excellent: approximately 97% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

Operational experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Ince, T; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.8% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

Operational experience with the ATLAS Pixel detector at the LHC

CERN Document Server

Deluca, C; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5\\% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, ...

Operational Experience with the ATLAS Pixel Detector at the LHC

CERN Document Server

Lange, C; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump- bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, a...

Operational experience with the ATLAS Pixel detector at the LHC

CERN Document Server

Deluca, C; The ATLAS collaboration

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

The FE-I4 Pixel Readout Chip and the IBL Module

Energy Technology Data Exchange (ETDEWEB)

Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

2012-05-01

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

The Phase-2 ATLAS ITk Pixel Upgrade

CERN Document Server

Macchiolo, Anna; The ATLAS collaboration

2018-01-01

The new ATLAS ITk pixel system will be installed during the LHC Phase-II shutdown, to better take advantage of the increased luminosity of the HL-LHC. The detector will consist of 5 layers of stave-like support structures in the most central region and ring-shaped supports in the endcap regions, covering up to |η| < 4. While the outer 3 layers of the Pixel Detector are designed to operate for the full HL-LHC data taking period, the innermost 2 layers of the detector will be replaced around half of the lifetime. The ITk pixel detector will be instrumented with new sensors and readout electronics to provide improved tracking performance and radiation hardness compared to the current detector. Sensors will be read out by new ASICs based on the chip developed by the RD53 Collaboration. The pixel off-detector readout electronics will be implemented in the framework of the general ATLAS trigger and DAQ system with a readout speed of up to 5 Gb/s per data link for the innermost layers. Results of extensive tests...

Calibration Analysis Software for the ATLAS Pixel Detector

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

2016-01-01

The calibration of the ATLAS Pixel detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied together to chips with different characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

CERN Document Server

Macchiolo, A; Beimforde, M; Moser, H G; Nisius, R; Richter, R H

2009-01-01

We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.

Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

CERN Document Server

Marcotulli, Andrea

2016-01-01

New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

Module and Electronics Developments for the ATLAS ITK Pixel System

CERN Document Server

Rummler, Andr{e}; The ATLAS collaboration

2016-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

Module and Electronics Developments for the ATLAS ITK Pixel System

CERN Document Server

Nellist, Clara; The ATLAS collaboration

2016-01-01

ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off de...

Module and electronics developments for the ATLAS ITK pixel system

CERN Document Server

Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

2017-01-01

ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in 2017. A new on-detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on-going R&D within the ATLAS ITK project towards the new pixel modules and the off-detector electronics. Planar and 3D sensors are being re-designed with cell sizes of 50x50 or 25x100 μm2, compatible with the RD53 chip. A sensor thickness equal or less th...

Development of 3D-DDTC pixel detectors for the ATLAS upgrade

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Boscardin, Maurizio; Darbo, Giovanni; Gemme, Claudia; La Rosa, Alessandro; Pernegger, Heinz; Piemonte, Claudio; Povoli, Marco; Ronchin, Sabina; Zoboli, Andrea; Zorzi, Nicola

2011-01-01

We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

Development of 3D-DDTC pixel detectors for the ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Boscardin, Maurizio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Darbo, Giovanni; Gemme, Claudia [INFN, Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); La Rosa, Alessandro; Pernegger, Heinz [CERN-PH, CH-1211 Geneve 23 (Switzerland); Piemonte, Claudio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Povoli, Marco [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Ronchin, Sabina [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Zoboli, Andrea [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Zorzi, Nicola [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy)

2011-04-21

We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

Development of 3D-DDTC pixel detectors for the ATLAS upgrade

CERN Document Server

Betta, G -F Dalla; Darbo, G; Gemme, C; La Rosa, A; Pernegger, H; Piemonte, C; Povoli, M; Ronchin, S; Zoboli, A; Zorzi, N

2011-01-01

We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are here discussed.

High-voltage pixel sensors for ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Perić, I., E-mail: ivan.peric@ziti.uni-heidelberg.de [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Kreidl, C.; Fischer, P. [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M. [CPPM, Marseille (France); Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B. [CERN, Geneve (Switzerland); Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A. [University of Geneve (Switzerland); and others

2014-11-21

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

Status of the ATLAS Pixel Detector and its performance after three years of operation

CERN Document Server

Favareto, A; The ATLAS collaboration

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is very important for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, and a good alignment allows high quality track resolution

Status of the ATLAS Pixel Detector and its performance after three years of operation

CERN Document Server

Favareto, A; The ATLAS collaboration

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is very important for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The detector performance is excellent: ~96% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, and a good alignment allows high quality track resolution.

MCC:the Module Controller Chip for the ATLAS Pixel Detector

Czech Academy of Sciences Publication Activity Database

Beccherle, R.; Darbo, G.; Gagliardi, G.; Šícho, Petr

2002-01-01

Roč. 492, 1-2 (2002), s. 117-133 ISSN 0168-9002 R&D Projects: GA MPO RP-4210/69 Institutional research plan: CEZ:AV0Z1010920 Keywords : ASIC * radiation hardness * silicon pixel detectors * ATLAS * LHC Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.167, year: 2002

Quality control on planar n-in-n pixel sensors — Recent progress of ATLAS planar pixel sensors

International Nuclear Information System (INIS)

Klingenberg, R.

2013-01-01

To extend the physics reach of the Large Hadron Collider (LHC), upgrades to the accelerator are planned which will increase the peak luminosity by a factor 5–10. To cope with the increased occupancy and radiation damage, the ATLAS experiment plans to introduce an all-silicon inner tracker with the high luminosity upgrade (HL-LHC). To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Upgrade Planar Pixel Sensor (PPS) R and D Project was established. Main areas of research are the performance of planar pixel sensors at highest fluences, the exploration of possibilities for cost reduction to enable the instrumentation of large areas, the achievement of slim or active edges to provide low geometric inefficiencies without the need for shingling of modules and the investigation of the operation of highly irradiated sensors at low thresholds to increase the efficiency. The Insertable b-layer (IBL) is the first upgrade project within the ATLAS experiment and will employ a new detector layer consisting of silicon pixel sensors, which were improved and prototyped in the framework of the planar pixel sensor R and D project. A special focus of this paper is the status of the development and testing of planar n-in-n pixel sensors including the quality control of the on-going series production and postprocessing of sensor wafers. A high yield of produced planar sensor wafers and FE-I4 double chip sensors after first steps of post-processing including under bump metallization and dicing is observed. -- Highlights: ► Prototypes of irradiated planar n-in-n sensors have been successfully tested under laboratory conditions. ► A quality assurance programme on the series production of planar sensors for the IBL has started. ► A high yield of double chip sensors during the series production is observed which are compatible to the specifications to this detector component.

Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

Energy Technology Data Exchange (ETDEWEB)

Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

2016-07-01

The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

International Nuclear Information System (INIS)

Püllen, Lukas; Boek, Jennifer; Kersten, Susanne; Kind, Peter; Mättig, Peter; Zeitnitz, Christian

2013-01-01

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerator's instantaneous luminosity by a factor of 5 and the integrated luminosity by a factor of 10. In the context of this upgrade, the inner detector (including the pixel detector) of the ATLAS experiment will be replaced. This new pixel detector requires a specific control system which complies with strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4×4 DCS chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub-micron technology. We present results from reliability measurements under irradiation from new prototypes of components for the DCS network.

Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

International Nuclear Information System (INIS)

Boek, J; Kersten, S; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

2013-01-01

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

International Nuclear Information System (INIS)

Backhaus, Malte

2014-01-01

The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the socalled Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosity increase in the shutdown of 2022 and 2023. The final chapter of this thesis introduces a new module concept that uses an industrial high voltage CMOS technology as sensor layer, which is capacitively coupled to the FE-I4 readout chip.

Performance of thin pixel sensors irradiated up to a fluence of 1016neqcm-2 and development of a new interconnection technology for the upgrade of the ATLAS pixel system

International Nuclear Information System (INIS)

Macchiolo, A.; Andricek, L.; Beimforde, M.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Weigell, P.

2011-01-01

A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R and D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and 150μm has been produced using a thinning technique developed at the Max-Planck-Institut Halbleiterlabor (HLL). Charge Collection Efficiency measurements have been performed, yielding a higher CCE than expected from the present radiation damage models. The interconnection of thin n-in-p pixels to the FE-I3 ATLAS electronics is under way, exploiting the Solid Liquid Interdiffusion (SLID) technique developed by the Fraunhofer Institut EMFT. In addition, preliminary studies aimed at Inter-Chip-Vias (ICV) etching into the FE-I3 electronics are reported. ICVs will be used to route the signals vertically through the read-out chip, to newly created pads on the backside. This should serve as a proof of principle for future four-side tileable pixel assemblies, avoiding the cantilever presently needed in the chip for the wire bonding.

Radiation induced effects in the \\\\ATLAS Insertable B-Layer readout chip

CERN Document Server

The ATLAS collaboration

2017-01-01

The ATLAS Insertable B-Layer is the innermost pixel barrel layer of the ATLAS detector installed in 2014. During the first year of $pp$ collisions at $\\sqrt{s} = 13~{\\rm TeV}$ in 2015, an unusual increase was observed in the low voltage currents of the readout chips. This increase was found to be due to radiation damage to the chips. The dependence of the current on the total ionising dose and temperature has been studied using X-ray and proton beam sources, and will be presented in this note together with its possible parametrisation and operation guidelines for the detector.

Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Wittig, Tobias

2013-05-08

One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

Status and future of the ATLAS Pixel Detector at the LHC

International Nuclear Information System (INIS)

Rozanov, Alexandre

2013-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of disks in each forward end-cap. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-on-n silicon substrates. Intensive calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. The record breaking instantaneous luminosities of 7.7×10 33 cm −2 s −1 recently surpassed at the LHC generated a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulated, the first effects of radiation damage became observable in the silicon sensors as an increase in the silicon leakage current and the change of the voltage required to fully deplete the sensor. A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014) together with the replacement of pixel services. A letter of intent was submitted for a completely new Pixel Detector after 2023, capable to take data with extremely high leveled luminosities of 5×10 34 cm −2 s −1 at the high luminosity LHC. -- Highlights: •The ATLAS Pixel Detector provides hermetic coverage with three layers with 80 million pixels. •Calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. •First effects of radiation damage became observable in the silicon sensors. •A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014). •Replacement of pixel services in 2013–2014. •A letter of intent was submitted for new Pixel Detector after 2023 for high luminosity LHC

Performance of irradiated thin n-in-p planar pixel sensors for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Savić, N.; Beyer, J.; Hiti, B.; Kramberger, G.; La Rosa, A.; Macchiolo, A.; Mandić, I.; Nisius, R.; Petek, M.

2017-12-01

The ATLAS collaboration will replace its tracking detector with new all silicon pixel and strip systems. This will allow to cope with the higher radiation and occupancy levels expected after the 5-fold increase in the luminosity of the LHC accelerator complex (HL-LHC). In the new tracking detector (ITk) pixel modules with increased granularity will implement to maintain the occupancy with a higher track density. In addition, both sensors and read-out chips composing the hybrid modules will be produced employing more radiation hard technologies with respect to the present pixel detector. Due to their outstanding performance in terms of radiation hardness, thin n-in-p sensors are promising candidates to instrument a section of the new pixel system. Recently produced and developed sensors of new designs will be presented. To test the sensors before interconnection to chips, a punch-through biasing structure was implemented. Its design was optimized to decrease the possible tracking efficiency losses observed. After irradiation, they were caused by the punch-through biasing structure. A sensor compatible with the ATLAS FE-I4 chip with a pixel size of 50×250 μm2, subdivided into smaller pixel implants of 30×30 μm2 size was designed to investigate the performance of the 50×50 μm2 pixel cells foreseen for the HL-LHC. Results on sensor performance of 50×250 and 50×50 μm2 pixel cells in terms of efficiency, charge collection and electric field properties are obtained with beam tests and the Transient Current Technique.

Module and electronics developments for the ATLAS ITK pixel system

CERN Document Server

Nellist, Clara; The ATLAS collaboration

2016-01-01

Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

Realisation of serial powering of ATLAS pixel modules

CERN Document Server

Stockmanns, Tobias; Fischer, P; Hügging, Fabian Georg; Peric, Ivan; Runólfsson, Ogmundur; Wermes, Norbert

2004-01-01

Modern hybrid pixel detectors as they will be used for the next generation of high energy collider experiments like LHC avail deep sub micron technology for the readout electronics. To operate chips in this technology low supply voltages of 2.0 V to 2.5 V and high currents to achieve the desired performance are needed. Due to the long and low mass supply cables this high current leads to a significant voltage drop so that voltage fluctuations at the chip result, when the supply current changes. Therefore the parallel connection of the readout electronics with the power supplies imposes severe constraints on a detector with respect to voltage fluctuations and cable mass. To bypass this problem a new concept of serially connecting modules in a supply chain was developed. The basic idea of the concept, the potential risk and ways to minimize these risks are presented. In addition, studies of the implementation of this technology as an alternative for a possible upgrade of the ATLAS pixel detector are shown. In p...

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

Science.gov (United States)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Study of run time errors of the ATLAS Pixel Detector in the 2012 data taking period

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00339072

2013-05-16

The high resolution silicon Pixel detector is critical in event vertex reconstruction and in particle track reconstruction in the ATLAS detector. During the pixel data taking operation, some modules (Silicon Pixel sensor +Front End Chip+ Module Control Chip (MCC)) go to an auto-disable state, where the Modules don’t send the data for storage. Modules become operational again after reconfiguration. The source of the problem is not fully understood. One possible source of the problem is traced to the occurrence of single event upset (SEU) in the MCC. Such a module goes to either a Timeout or Busy state. This report is the study of different types and rates of errors occurring in the Pixel data taking operation. Also, the study includes the error rate dependency on Pixel detector geometry.

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation

CERN Document Server

Andreazza, A; The ATLAS collaboration

2012-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit ...

First MCM-D modules for the b-physics layer of the ATLAS Pixel Detector

CERN Document Server

Basken, O; Ehrmann, O; Gerlach, P; Grah, C; Gregor, I M; Linder, C; Meuser, S; Richardson, J; Topper, M; Wolf, J

2000-01-01

The innermost layer (b-physics layer) of the ATLAS Pixel Detector will consist of modules based on MCM-D technology. Such a module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out ICs, each serving 24* 160 pixel unit cells, a module controller chip (MCC), an optical transceiver and the local signal interconnection and power distribution busses. We show a prototype of such a module with additional test pads on both sides. The outer dimensions of the final module will be 21.4 mm*67.8 mm. The extremely high wiring density, which is necessary to interconnect the read-out chips, was achieved using a thin film copper/photo-BCB process on the pixel array. The bumping of the read out chips was done using electroplating PbSn. All dice are then attached by flip-chip assembly to the sensor diodes and the local busses. The focus of this paper is the description of the first results of such MCM-D-type modules. (11 refs).

Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC

International Nuclear Information System (INIS)

Kersten, S.; Püllen, L.; Zeitnitz, C.

2016-01-01

In terms of the phase-2 upgrade of the ATLAS detector, the entire inner tracker (ITk) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system is being developed with emphasis on the supervision of serially powered modules. Previous chips had been designed to test the radiation hardness of the technology and the implementation of the modified I2C as well as the implementation of the logic of the CAN protocol. This included tests with triple redundant registers. The described chip is focusing on the implementation in a serial powering scheme. It was designed for laboratory tests, aiming for the proof of principle. The concept of the DCS for ATLAS pixel after the phase-2 upgrade is presented as well as the status of development including tests with the prototype ASIC

The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

Energy Technology Data Exchange (ETDEWEB)

Backhaus, M., E-mail: malte.backhaus@cern.ch

2016-09-21

During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO{sub 2} based cooling system. This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

Radiationhard components for the control system of a future ATLAS pixel detector

International Nuclear Information System (INIS)

Becker, K; Boek, J; Kersten, S; Kind, P; Maettig, P; Puellen, L; Zeitnitz, C

2011-01-01

The upgrade of the ATLAS experiment for the High Luminosity LHC (HL-LHC) will include a new pixel detector. A completely new detector control system (DCS) for this pixel detector will be required in order to cope with the substantial increase in radiation at the HL-LHC. The DCS has to have a very high reliability and all components installed within the detector volume have to be radiationhard. This will ensure a safe operation of the pixel detector and the experiment. A further design constraint is the minimization of the used material and cables in order to limit the impact on the tracking performance to a minimum. To meet these requirements we propose a DCS network which consists of a DCS chip and a DCS controller. In the following we present the development of the first prototypes for the DCS chip and the DCS controller with a special focus on the communication interface, radiation hardness and robustness against single event upsets.

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

International Nuclear Information System (INIS)

Riegel, C.; Backhaus, M.; Hoorne, J.W. Van; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 10 15 n/cm 2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Performance of thin pixel sensors irradiated up to a fluence of 10{sup 16}n{sub eq}cm{sup -2} and development of a new interconnection technology for the upgrade of the ATLAS pixel system

Energy Technology Data Exchange (ETDEWEB)

Macchiolo, A., E-mail: Anna.Macchiolo@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Andricek, L. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 Muenchen (Germany); Beimforde, M. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Moser, H.-G. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 Muenchen (Germany); Nisius, R. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Richter, R.H. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 Muenchen (Germany); Weigell, P. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805 Muenchen (Germany)

2011-09-11

A new pixel module concept is presented, where thin sensors and a novel vertical integration technique are combined. This R and D activity is carried out in view of the ATLAS pixel detector upgrades. A first set of n-in-p pixel sensors with active thicknesses of 75 and 150{mu}m has been produced using a thinning technique developed at the Max-Planck-Institut Halbleiterlabor (HLL). Charge Collection Efficiency measurements have been performed, yielding a higher CCE than expected from the present radiation damage models. The interconnection of thin n-in-p pixels to the FE-I3 ATLAS electronics is under way, exploiting the Solid Liquid Interdiffusion (SLID) technique developed by the Fraunhofer Institut EMFT. In addition, preliminary studies aimed at Inter-Chip-Vias (ICV) etching into the FE-I3 electronics are reported. ICVs will be used to route the signals vertically through the read-out chip, to newly created pads on the backside. This should serve as a proof of principle for future four-side tileable pixel assemblies, avoiding the cantilever presently needed in the chip for the wire bonding.

ATLAS pixel IBL modules construction experience and developments for future upgrade

Energy Technology Data Exchange (ETDEWEB)

Gaudiello, A.

2015-10-01

The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, are used. Sensors are connected with the new generation 130 nm IBM CMOS FE-I4 read-out chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

CERN Document Server

Macchiolo, Anna; Savic, Natascha; Terzo, Stefano

2016-09-21

Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region...

The ATLAS Planar Pixel Sensor R and D project

International Nuclear Information System (INIS)

Beimforde, M.

2011-01-01

Within the R and D project on Planar Pixel Sensor Technology for the ATLAS inner detector upgrade, the use of planar pixel sensors for highest fluences as well as large area silicon detectors is investigated. The main research goals are optimizing the signal size after irradiations, reducing the inactive sensor edges, adjusting the readout electronics to the radiation induced decrease of the signal sizes, and reducing the production costs. Planar n-in-p sensors have been irradiated with neutrons and protons up to fluences of 2x10 16 n eq /cm 2 and 1x10 16 n eq /cm 2 , respectively, to study the collected charge as a function of the irradiation dose received. Furthermore comparisons of irradiated standard 300μm and thin 140μm sensors will be presented showing an increase of signal sizes after irradiation in thin sensors. Tuning studies of the present ATLAS front end electronics show possibilities to decrease the discriminator threshold of the present FE-I3 read out chips to less than 1500 electrons. In the present pixel detector upgrade scenarios a flat stave design for the innermost layers requires reduced inactive areas at the sensor edges to ensure low geometric inefficiencies. Investigations towards achieving slim edges presented here show possibilities to reduce the width of the inactive area to less than 500μm. Furthermore, a brief overview of present simulation activities within the Planar Pixel R and D project is given.

Operational Experience with the ATLAS Pixel Detector

CERN Document Server

Djama, Fares; The ATLAS collaboration

2017-01-01

Run 2 of the LHC collider sets new challenges to track and vertex reconstruction because of its higher energy, pileup and luminosity. The ATLAS tracking performance relies critically on the Pixel Detector. Therefore, in view of Run 2, the ATLAS collaboration has constructed the first 4-layer pixel detector in Particle Physics by installing a new pixel layer, called Insertable B-Layer (IBL). Operational experience and performance of the 4-layer Pixel Detector during Run 2 are presented.

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

Commissioning of the ATLAS pixel detector

International Nuclear Information System (INIS)

Golling, Tobias

2008-01-01

The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and summer 2008, and is ready for the imminent LHC turn-on. The highlights of the past and future commissioning activities of the ATLAS pixel system are presented

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

International Nuclear Information System (INIS)

Conti, E.; Marconi, S.; Christiansen, J.; Placidi, P.; Hemperek, T.

2016-01-01

The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified

Rework of flip chip bonded radiation pixel detectors

International Nuclear Information System (INIS)

Vaehaenen, S.; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S.

2008-01-01

In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process

Rework of flip chip bonded radiation pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Vaehaenen, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)], E-mail: sami.vahanen@vtt.fi; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)

2008-06-11

In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process.

A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

Energy Technology Data Exchange (ETDEWEB)

Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P, E-mail: Michael.Beimforde@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805, Muenchen (Germany)

2010-12-15

The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 {mu}m and 150 {mu}m has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10{sup 16}n{sub eq}cm{sup -2} have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

International Nuclear Information System (INIS)

Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P

2010-01-01

The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10 16 n eq cm -2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

International Nuclear Information System (INIS)

Savic, N.; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

2017-01-01

The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm"2). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm"2 pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

Energy Technology Data Exchange (ETDEWEB)

Savic, N., E-mail: natascha.savic@mpp.mpg.de; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

2017-02-11

The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm{sup 2}). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm{sup 2} pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

CERN Document Server

Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

2012-01-01

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

ATLAS SemiConductor Tracker and Pixel Detector: Status and Performance

CERN Document Server

Reeves, K; The ATLAS collaboration

2012-01-01

The Semi-Conductor Tracker (SCT) and the Pixel Detector are the key precision tracking devices in the Inner Detector of the ATLAS experiment at CERN LHC. The SCT is a silicon strip detector and is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. The Pixel Detector consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In the talk the current status of the SCT and Pixel Detector will be reviewed. We will report on the operation of the detectors including an overview of the issues we encountered and the observation of significant increases in leakage currents (as expected) from bulk ...

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

CERN Document Server

Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

2009-01-01

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

ATLAS rewards two pixel detector suppliers

CERN Multimedia

2007-01-01

Peter Jenni, ATLAS spokesperson, presented the ATLAS supplier award to Herbert Reichl, IZM director, and to Simonetta Di Gioia, from the SELEX company.Two of ATLAS’ suppliers were awarded prizes at a ceremony on Wednesday 13 June attended by representatives of the experiment’s management and of CERN. The prizes went to the Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM) in Berlin and the company SELEX Sistemi Integrati in Rome for the manufacture of modules for the ATLAS pixel detector. SELEX supplied 1500 of the modules for the tracker, while IZM produced a further 1300. The modules, each made up of 46080 channels, form the active part of the ATLAS pixel detector. IZM and SELEX received the awards for the excellent quality of their work: the average number of faulty channels per module was less than 2.10-3. They also stayed within budget and on schedule. The difficulty they faced was designing modules based on electronic components and sensor...

Operational Experience with the ATLAS Pixel Detector

CERN Document Server

Djama, Fares; The ATLAS collaboration

2017-01-01

Run-2 of the LHC is providing new challenges to track and vertex reconstruction imposed by the higher collision energy, pileup and luminosity that are being delivered. The ATLAS tracking performance relies critically on the Pixel Detector, therefore, in view of Run-2 of LHC, the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and an additional optical link per module was added to overcome in some layers the readout bandwidth limitation when LHC will exceed the nominal peak luminosity by almost a factor of 3. The key features and challenges met during the IBL project will be presented, as well as its operational experience and Pixel Detector performance in LHC.

SLHC upgrade plans for the ATLAS pixel detector

International Nuclear Information System (INIS)

Sicho, Petr

2009-01-01

The ATLAS pixel detector is an 80 million channels silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. An upgrade of the ATLAS pixel detector is presently being considered, enabling to cope with higher luminosity at Super Large Hadron Collider (SLHC). The increased luminosity leads to extremely high radiation doses in the innermost region of the ATLAS tracker. Options considered for a new detector are discussed, as well as some important R and D activities, such as investigations towards novel detector geometries and novel processes.

submitter Development of the readout for the IBL upgrade project of the ATLAS Pixel Detector

CERN Document Server

Krieger, Nina

The LHC luminosity is upgraded in several phases until 2022. The resulting higher occupancy degrades the detector performance of the current Pixel Detector. To provide a good performance during the LHC luminosity upgrade, a fourth pixel layer is inserted into the existing ATLAS Pixel Detector. A new FE-I4 readout chip and a new data acquisition chain are required to cope with the higher track rate and the resulting increased bandwidth. Among others, this includes a new readout board: the IBL ROD. One component of this board is the DSP which creates commands for the FE-I4 chip and has to be upgraded as well. In this thesis, the first tests of the IBL ROD prototype are presented. A correct communication of the DSP to its external memory is verified. Moreover, the implementations for an IBL DSP code are described and tested. This includes the first configuration of the FE-I4 with an IBL ROD. In addition, a working communication with the Histogrammer SDRAM and the Input FIFO on the IBL ROD are demonstrated.

Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

International Nuclear Information System (INIS)

Terzo, S; Macchiolo, A; Nisius, R; Paschen, B

2014-01-01

Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 μm, produced at CiS, and 100-200 μm thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The performance of the different sensor thicknesses and edge designs are compared before and after irradiation up to a fluence of 1.4 × 10 16 n eq /cm 2

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

CERN Document Server

Gabrielli, Alessandro; The ATLAS collaboration; Balbi, Gabriele; Bindi, Marcello; Chen, Shaw-pin; Falchieri, Davide; Flick, Tobias; Hauck, Scott Alan; Hsu, Shih-Chieh; Kretz, Moritz; Kugel, Andreas; Lama, Luca; Travaglini, Riccardo; Wensing, Marius; ATLAS Pixel Collaboration

2015-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data pat...

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

CERN Document Server

Balbi, G; The ATLAS collaboration; Gabrielli, A; Lama, L; Travaglini, R; Backhaus, M; Bindi, M; Chen, S-P; Flick, T; Kretz, M; Kugel, A; Wensing, M

2014-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development was three-fold: keeping as much of the PixelROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path im...

RD Collaboration Proposal: Development of pixel readout integrated circuits for extreme rate and radiation

CERN Document Server

Chistiansen, J (CERN)

2013-01-01

This proposal describes a new RD collaboration to develop the next genrration of hybrid pixel readout chips for use in ATLAS and CMS PHase 2 upgrades. extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. Challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm2 ), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. This collaboration is specifically focused on design of hybrid pixel readout chips, and not on more general chip design or on other aspects of hybrid pixel technology. Participants include 7 institutes on ATLAS and 7 on CMS, plus 2 on both experiments.

Radiation damage monitoring in the ATLAS pixel detector

International Nuclear Information System (INIS)

Seidel, Sally

2013-01-01

We describe the implementation of radiation damage monitoring using measurement of leakage current in the ATLAS silicon pixel sensors. The dependence of the leakage current upon the integrated luminosity is presented. The measurement of the radiation damage corresponding to an integrated luminosity 5.6 fb −1 is presented along with a comparison to a model. -- Highlights: ► Radiation damage monitoring via silicon leakage current is implemented in the ATLAS (LHC) pixel detector. ► Leakage currents measured are consistent with the Hamburg/Dortmund model. ► This information can be used to validate the ATLAS simulation model.

Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

CERN Document Server

Ristic, Branislav

2016-09-21

Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

ATLAS Pixel Detector Upgrade

CERN Document Server

Flick, T; The ATLAS collaboration

2009-01-01

The first upgrade for higher luminosity at LHC for the ATLAS pixel detector is the insertion of a forth layer, the IBL. The talk gives an overview about what the IBL is and how it will be set up, as well as to give a status of the research and develoment work.

ATLAS Pixel Group - Photo Gallery from Irradiation

CERN Multimedia

2001-01-01

Photos 1,2,3,4,5,6,7 - Photos taken before irradiation of Pixel Test Analog Chip and Pmbars (April 2000) Photos 8,9,10,11 - Irradiation of VDC chips (May 2000) Photos 12, 13 - Irradiation of Passive Components (June 2000) Photos 14,15, 16 - Irradiation of Marebo Chip (November 1999)

ATLAS ITk and new pixel sensors technologies

CERN Document Server

Gaudiello, A

2016-01-01

During the 2023–2024 shutdown, the Large Hadron Collider (LHC) will be upgraded to reach an instantaneous luminosity up to 7×10$^{34}$ cm$^{−2}$s$^{−1}$. This upgrade of the accelerator is called High-Luminosity LHC (HL-LHC). The ATLAS detector will be changed to meet the challenges of HL-LHC: an average of 200 pile-up events in every bunch crossing, and an integrated luminosity of 3000 fb $^{−1}$ over ten years. The HL-LHC luminosity conditions are too extreme for the current silicon (pixel and strip) detectors and straw tube transition radiation tracker (TRT) of the current ATLAS tracking system. Therefore the ATLAS inner tracker is being completely rebuilt for data-taking and the new system is called Inner Tracker (ITk). During this upgrade the TRT will be removed in favor of an all-new all-silicon tracker composed only by strip and pixel detectors. An overview of new layouts in study will be reported and the new pixel sensor technologies in development will be explained.

Design and Performance of the CMS Pixel Detector Readout Chip

CERN Document Server

Kästli, H C; Erdmann, W; Hörmann, C; Horisberger, R P; Kotlinski, D; Meier, B; Hoermann, Ch.

2006-01-01

The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor

CERN Document Server

Stockmanns, Tobias

2004-01-01

Abstract: The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 µm technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules mo...

Individualized Pixel Synthesis and Characterization of Combinatorial Materials Chips

Directory of Open Access Journals (Sweden)

Xiao-Dong Xiang

2015-06-01

Full Text Available Conventionally, an experimentally determined phase diagram requires studies of phase formation at a range of temperatures for each composition, which takes years of effort from multiple research groups. Combinatorial materials chip technology, featuring high-throughput synthesis and characterization, is able to determine the phase diagram of an entire composition spread of a binary or ternary system at a single temperature on one materials library, which, though significantly increasing efficiency, still requires many libraries processed at a series of temperatures in order to complete a phase diagram. In this paper, we propose a “one-chip method” to construct a complete phase diagram by individually synthesizing each pixel step by step with a progressive pulse of energy to heat at different temperatures while monitoring the phase evolution on the pixel in situ in real time. Repeating this process pixel by pixel throughout the whole chip allows the entire binary or ternary phase diagram to be mapped on one chip in a single experiment. The feasibility of this methodology is demonstrated in a study of a Ge-Sb-Te ternary alloy system, on which the amorphous-crystalline phase boundary is determined.

Development of pixel readout integrated circuits for extreme rate and radiation

CERN Multimedia

Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Pacher, L; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Marconi, S; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

Science.gov (United States)

Macchiolo, A.; Nisius, R.; Savic, N.; Terzo, S.

2016-09-01

Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14 ×1015 neq /cm2 . The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.

Characterization and Performance of Silicon n-in-p Pixel Detectors for the ATLAS Upgrades

CERN Document Server

Weigell, Philipp; Gallrapp, Christian; La Rosa, Alessandro; Macchiolo, Anna; Nisius, Richard; Pernegger, Heinz; Richter, Rainer

2011-01-01

The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities (super LHC) the development of new structures and materials which can cope with the resulting particle fluences is needed. N-in-p silicon devices are a promising candidate for tracking detectors to achieve these goals, since they are radiation hard, cost efficient and are not type inverted after irradiation. A n-in-p pixel production based on a MPP/HLL design and performed by CiS (Erfurt, Germany) on 300 \\mu m thick Float-Zone material is characterised and the electrical properties of sensors and single chip modules (SCM) are presented, including noise, charge collection efficiencies, and measurements with MIPs as well as an 241Am source. The SCMs are built with sensors connected to the current the ATLAS read-out chip FE-I3. The characterisation has been performed with the ATL...

Performance of n-in-p pixel detectors irradiated at fluences up to $5x10^{15} n_{eq}/cm^{2}$ for the future ATLAS upgrades

CERN Document Server

INSPIRE-00219560; La Rosa, A.; Nisius, R.; Pernegger, H.; Richter, R.H.; Weigell, P.

We present the results of the characterization of novel n-in-p planar pixel detectors, designed for the future upgrades of the ATLAS pixel system. N-in-p silicon devices are a promising candidate to replace the n-in-n sensors thanks to their radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. The n-in-p modules presented here are composed of pixel sensors produced by CiS connected by bump-bonding to the ATLAS readout chip FE-I3. The characterization of these devices has been performed with the ATLAS pixel read-out systems, TurboDAQ and USBPIX, before and after irradiation with 25 MeV protons and neutrons up to a fluence of 5x10**15 neq /cm2. The charge collection measurements carried out with radioactive sources have proven the feasibility of employing this kind of detectors up to these particle fluences. The collected charge has been measured to be for any fluence in excess of twice the value of the FE-I3 threshold, tuned to 3200 e. The first result...

Monitoring radiation damage in the ATLAS pixel detector

CERN Document Server

Schorlemmer, André Lukas; Quadt, Arnulf; Große-Knetter, Jörn; Rembser, Christoph; Di Girolamo, Beniamino

2014-11-05

Radiation hardness is one of the most important features of the ATLAS pixel detector in order to ensure a good performance and a long lifetime. Monitoring of radiation damage is crucial in order to assess and predict the expected performance of the detector. Key values for the assessment of radiation damage in silicon, such as the depletion voltage and depletion depth in the sensors, are measured on a regular basis during operations. This thesis summarises the monitoring program that is conducted in order to assess the impact of radiation damage and compares it to model predictions. In addition, the physics performance of the ATLAS detector highly depends on the amount of disabled modules in the ATLAS pixel detector. A worrying amount of module failures was observed during run I. Thus it was decided to recover repairable modules during the long shutdown (LS1) by extracting the pixel detector. The impact of the module repairs and module failures on the detector performance is analysed in this thesis.

Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

International Nuclear Information System (INIS)

Mathes, Markus

2008-12-01

Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10 16 particles per cm 2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 μm 2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm 2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm 2 ). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

Development of pixel readout integrated circuits for extreme rate and radiation

CERN Document Server

Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

2013-01-01

Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

Vertically integrated pixel readout chip for high energy physics

International Nuclear Information System (INIS)

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Khalid, Farah; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

2011-01-01

We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 (micro)m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 (micro)m 2 pixels, laid out in an array of 48 x 48 pixels.

Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

Energy Technology Data Exchange (ETDEWEB)

Mathes, Markus

2008-12-15

Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

Digital column readout architectures for hybrid pixel detector readout chips

International Nuclear Information System (INIS)

Poikela, T; Plosila, J; Westerlund, T; Buytaert, J; Campbell, M; Gaspari, M De; Llopart, X; Wyllie, K; Gromov, V; Kluit, R; Beuzekom, M van; Zappon, F; Zivkovic, V; Brezina, C; Desch, K; Fu, Y; Kruth, A

2014-01-01

In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures

Readout Architecture for Hybrid Pixel Readout Chips

CERN Document Server

AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

Energy Technology Data Exchange (ETDEWEB)

Puellen, Lukas

2015-02-10

In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

International Nuclear Information System (INIS)

Puellen, Lukas

2015-01-01

In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

The Phase-2 ATLAS ITk Pixel Upgrade

CERN Document Server

Rossi, Leonardo Paolo; The ATLAS collaboration

2018-01-01

The upgrade of the ATLAS experiment for the operation at the High Luminosity Large Hadron Collider requires a new and more performant inner tracker, the ITk. The innermost part of this tracker will be built using silicon pixel detectors. This paper describes the ITk pixel project, which, after few years of design and test e ort, is now defined in detail.

Iterative local Chi2 alignment algorithm for the ATLAS Pixel detector

CERN Document Server

Göttfert, Tobias

The existing local chi2 alignment approach for the ATLAS SCT detector was extended to the alignment of the ATLAS Pixel detector. This approach is linear, aligns modules separately, and uses distance of closest approach residuals and iterations. The derivation and underlying concepts of the approach are presented. To show the feasibility of the approach for Pixel modules, a simplified, stand-alone track simulation, together with the alignment algorithm, was developed with the ROOT analysis software package. The Pixel alignment software was integrated into Athena, the ATLAS software framework. First results and the achievable accuracy for this approach with a simulated dataset are presented.

Planar slim-edge pixel sensors for the ATLAS upgrades

International Nuclear Information System (INIS)

Altenheiner, S; Goessling, C; Jentzsch, J; Klingenberg, R; Lapsien, T; Rummler, A; Troska, G; Wittig, T; Muenstermann, D

2012-01-01

The ATLAS detector at CERN is a general-purpose experiment at the Large Hadron Collider (LHC). The ATLAS Pixel Detector is the innermost tracking detector of ATLAS and requires a sufficient level of hermeticity to achieve superb track reconstruction performance. The current planar n-type pixel sensors feature a pixel matrix of n + -implantations which is (on the opposite p-side) surrounded by so-called guard rings to reduce the high voltage stepwise towards the cutting edge and an additional safety margin. Because of the inactive region around the active area, the sensor modules have been shingled on top of each other's edge which limits the thermal performance and adds complexity in the present detector. The first upgrade phase of the ATLAS pixel detector will consist of the insertable b-layer (IBL), an additional b-layer which will be inserted into the present detector in 2013. Several changes in the sensor design with respect to the existing detector had to be applied to comply with the IBL's specifications and are described in detail. A key issue for the ATLAS upgrades is a flat arrangement of the sensors. To maintain the required level of hermeticity in the detector, the inactive sensor edges have to be reduced to minimize the dead space between the adjacent detector modules. Unirradiated and irradiated sensors with the IBL design have been operated in test beams to study the efficiency performance in the sensor edge region and it was found that the inactive edge width could be reduced from 1100 μm to less than 250 μm.

Development and Characterization of Diamond and 3D-Silicon Pixel Detectors with ATLAS-Pixel Readout Electronics

CERN Document Server

Mathes, Markus

2008-01-01

Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10^16 particles per cm^2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 × 50 um^2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm^2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 × 6 cm^2). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection ...

3D silicon pixel detectors for the ATLAS Forward Physics experiment

International Nuclear Information System (INIS)

Lange, J.; Cavallaro, E.; Grinstein, S.; Paz, I. López

2015-01-01

The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2–3 mm). This implies the need of slim edges of about 100–200 μm width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 μm width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 10 15 n eq /cm 2 with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al masks. The efficiency in the irradiated region is found to be similar to the one in the non-irradiated region and exceeds 97% in case of favourable chip-parameter settings. Only in a narrow transition area at the edge of the hole in the Al mask, a significantly lower efficiency is seen. A follow-up study of this effect using arrays of small pad diodes for position-resolved dosimetry via the leakage current is carried out

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

International Nuclear Information System (INIS)

Gabrielli, A.; Balbi, G.; Falchieri, D.; Lama, L.; Travaglini, R.; Backhaus, M.; Bindi, M.; Chen, S.P.; Hauck, S.; Hsu, S.C.; Flick, T.; Wensing, M.; Kretz, M.; Kugel, A.

2015-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

OpenAIRE

Riegel, C; Backhaus, M; Hoorne, J W Van; Kugathasan, T; Musa, L; Pernegger, H; Riedler, P; Schaefer, D; Snoeys, W; Wagner, W

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS techn...

Results from the Commissioning of the ATLAS Pixel Detector

CERN Document Server

Strandberg, S

2009-01-01

The ATLAS pixel detector is a high resolution, silicon based, tracking detector with its innermost layer located only 5 cm away from the ATLAS interaction point. It is designed to provide good hit resolution and low noise, both important qualities for pattern recognition and for finding secondary vertices originating from decays of long-lived particles. The pixel detector has 80 million readout channels and is built up of three barrel layers and six disks, three on each side of the barrel. The detector was installed in the center of ATLAS in June 2007 and is currently being calibrated and commissioned. Details from the installation, commissioning and calibration are presented together with the current status.

Results from the commissioning of the ATLAS Pixel Detector

CERN Document Server

Masetti, L

2008-01-01

The Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It is an 80 million channel silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. After connection of cooling and services and verification of their operation, the ATLAS Pixel Detector is now in the final stage of its commissioning phase. Calibration of optical connections, verification of the analog performance and special DAQ runs for noise studies have been performed and the first tracks in combined operation with the other subdetectors of the ATLAS Inner Detector were observed. The results from calibration tests on the whole detector and from cosmic muon data are presented.

Serial powering optimization for CMS and ATLAS pixel detectors within RD53 collaboration for HL-LHC: system level simulations and testing

CERN Document Server

Orfanelli, Stella; Hamer, Matthias; Hinterkeuser, F; Karagounis, M; Pradas Luengo, Alvaro; Marconi, Sara; Ruini, Daniele

2017-01-01

Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. Two 2.0 A Shunt-LDO regulators are integrated in a prototype pixel chip implemented in 65-nm CMOS technology and used to provide constant supply voltages to its power domains from a constant input current. Performance results from testing prototype Shunt-LDO regulators are shown, including their behaviour after x-ray irradiation. The system level simulation studies, which had been performed with a detailed regulator design in a serially powered topology, have been validated.

The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00407702

2016-01-01

The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

Operational Experience with the ATLAS Pixel Detector

CERN Document Server

Lantzsch, Kerstin; The ATLAS collaboration

2016-01-01

Run 2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). In addition the Pixel detector was refurbished with new service quarter panels to recover about 3% of defective modules lost during run 1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning, operation and performance of the 4-layer Pixel Detector will be presented.

Optical data links for the ATLAS SCT and Pixel Detector

International Nuclear Information System (INIS)

Gregor, I.M.; Weidberg, A.R.; Lee, S.C.; Chu, M.L.; Teng, P.K.

2001-01-01

ATLAS (The ATLAS Technical Proposal, CERN/LHCC 94-33) is one of the large electronic particle detectors at LHC (The LHC Conceptual Design, Report- The Yellow Book, CERN/AC/95-05(LHC)) which will become operational in 2005. It is planned to use radiation tolerant optical links for the data transfer from the SemiConductor Tracker (SCT) (ATLAS Inner Detector Technical Proposal, CERN/LHCC 97-16 and CERN/LHCC 97-17). and Pixel Detector (ATLAS Pixel Detector Technical Proposal, CERN/LHCC 98-13) systems to the acquisition electronics over a distance up to 140m. The overall architecture and the performance of these optical data links are described. One of the three candidate designs for an on-detector Opto-Package is presented

Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

Energy Technology Data Exchange (ETDEWEB)

Peric, I.

2004-08-01

Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

The ATLAS Pixel Detector operation and performance

CERN Document Server

Andreazza, A; The ATLAS collaboration

2010-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately $80 imes 10^6$~electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region. The complete Pixel Detector has been taking part in cosmic-ray data-taking since 2008. Since November 2009 it has been operated with LHC colliding beams at $sqrt{s}=900$~GeV, 2.36~TeV and 7 TeV. The detector operated with an active fraction of 97.2% at a threshold of 3500~$e$, showing a noise occupancy rate better than $10^{-9}$~hit/pixel/BC and a track association efficiency of 99%. The Lorentz angle for electrons in silicon is measured to be $ heta_mathrm{L}=12.11^circ pm 0.09^circ$ and its temperature dependence has been verified. The pulse height information from the time-over-threshold technique allows to improve the point resolution using charge sharing and to perform parti...

Transfer Function and Fluorescence Measurements on New CMOS Pixel Sensor for ATLAS

CERN Document Server

Kaemingk, Michael

2017-01-01

A new generation of pixel sensors is being designed for the phase II upgrade of the ATLAS Inner Tracker (ITk). These pixel sensors are being tested to ensure that they meet the demands of the ATLAS detector. As a summer student, I was involved in some of the measurements taken for this purpose.

Operational Experience and Performance with the ATLAS Pixel detector

CERN Document Server

Martin, Christopher Blake; The ATLAS collaboration

2018-01-01

The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of $1.3\\times10^{34}\\text{cm}^{{-2}}\\text{s}^{{-1}}$ recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarized, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

Operational Experience and Performance with the ATLAS Pixel detector

CERN Document Server

Martin, Christopher Blake; The ATLAS collaboration

2018-01-01

The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 1.3 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

Science.gov (United States)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

Development of the MCM-D technique for pixel detector modules

CERN Document Server

Grah, Christian

2005-01-01

This thesis treats a copper--polymer based thin film technology, the MCM-D technique and its application when building hybrid pixel detector modules. The ATLAS experiment at the LHC will be equipped with a pixel detector system. The basic mechanical units of the pixel detector are multi chip modules. The main components of these modules are: 16 electronic chips, a controller chip and a large sensor tile, featuring more than 46000 sensor cells. MCM-D is a superior technique to build the necessary signal bus system and the power distribution system directly on the active sensor tile. In collaboration with the Fraunhofer Institute for Reliability and Microintegration, IZM, the thin film process is reviewed and enhanced. The multi layer system was designed and optimized for the interconnection system as well as for the 46000 pixel contacts. Laboratory measurements on prototypes prove that complex routing schemes for geometrically optimized single chips are suitable and have negligible influence on the front--end ...

Test Beam Results of Geometry Optimized Hybrid Pixel Detectors

CERN Document Server

Becks, K H; Grah, C; Mättig, P; Rohe, T

2006-01-01

The Multi-Chip-Module-Deposited (MCM-D) technique has been used to build hybrid pixel detector assemblies. This paper summarises the results of an analysis of data obtained in a test beam campaign at CERN. Here, single chip hybrids made of ATLAS pixel prototype read-out electronics and special sensor tiles were used. They were prepared by the Fraunhofer Institut fuer Zuverlaessigkeit und Mikrointegration, IZM, Berlin, Germany. The sensors feature an optimized sensor geometry called equal sized bricked. This design enhances the spatial resolution for double hits in the long direction of the sensor cells.

ATLAS IBL Stave QA - In and Around SR1

CERN Document Server

Carney, Rebecca

2013-01-01

During the Phase-I upgrade the ATLAS Inner tracker will have a whole new layer of pixels inserted between the existing B-layer and a new, smaller, beam pipe. Briefly, there are 14 assemblies of 32 single and double-chip hybrid silicon pixel chips arranged side-by-side on light-weight, thermally conductive carbon-fibre coated carbon foam supports called staves. When the staves arrive at CERN, fully assembled, they undergo a QA procedure, which checks the power characteristics of sensors and read-out chips, and assess the quality of individual pixels.

Readout chip for the CMS pixel detector upgrade

Energy Technology Data Exchange (ETDEWEB)

Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

2014-11-21

For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

A self-adjusting delay circuit for pixel read-out chips

International Nuclear Information System (INIS)

Raith, B.

1997-01-01

A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

International Nuclear Information System (INIS)

Havranek, Miroslav

2014-09-01

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Havranek, Miroslav

2014-09-15

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Pixel-Cluster Counting Luminosity Measurement in ATLAS

CERN Document Server

McCormack, William Patrick; The ATLAS collaboration

2016-01-01

A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measurements of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster-counting method are ...

Pixel-Cluster Counting Luminosity Measurement In ATLAS

CERN Document Server

AUTHOR|(SzGeCERN)782710; The ATLAS collaboration

2017-01-01

A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measure- ments of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster- counting method a...

Recent achievements of the ATLAS upgrade Planar Pixel Sensors R and D Project

International Nuclear Information System (INIS)

George, M

2014-01-01

After the foreseen upgrade of the LHC towards the HL-LHC, coming along with higher beam energies and increased peak luminosities, the experiments have to upgrade their detector systems to cope with the expected higher occupancies and radiation damages. In case of the ATLAS experiment a new Inner Tracker will be installed in this context. The ATLAS Planar Pixel Sensor R and D Project (PPS) is investigating the possibilities to cope with these new requirements, using planar pixel silicon sensors, working in a collaboration of 17 institutions and more than 80 scientists. Since the new Inner Tracker is supposed to have an active area on the order of 8 m 2 on the one side and has to withstand extreme irradiation on the other side, the PPS community is working on several approaches to reduce production costs, while increasing the radiation tolerance of the sensors. Another challenge is to produce sensors in such large quantities. During the production of the Insertable b-Layer (IBL) modules, the PPS community has proven to be able to produce a large scale production of planar silicon sensors with a high yield. For cost reduction reasons, it is desirable to produce larger sensors. There the PPS community is working on so called quad- and hex-modules, which have a size of four, respectively six FE-I4 readout chips. To cope with smaller radii and strict material budget requirements for the new pixel layers, developments towards sensors with small inactive areas are in the focus of research. Different production techniques, which even allow the production of sensors with active edges, have been investigated and the designs were qualified using lab and testbeam measurements. The short distance between the new innermost pixel layers and the interaction point, combined with the increase in luminosity, requires designs which are more radiation tolerant. Since charge collection on the one hand decreases with irradiation and on the other hand is not uniform within the pixel cells

Studies for an upgrade of ALICE Inner Tracking System: Pixel chip characterization

Directory of Open Access Journals (Sweden)

Park Jonghan

2017-01-01

Full Text Available Inner Tracking System (ITS of ALICE is used for vertex determination and tracking. Future heavy-ion program at the LHC aims to run with high luminosity. To address this challenge, upgrade program of ITS is underway, which aims at better position resolution (factor of 3, high detection efficiency (>99%, high-rate readout capabilities (100 kHz for Pb-Pb and moderate radiation hardness (> 700 krad. The new ITS will be composed with 7 layers of silicon pixel chip based on Monolithic Active Pixel Sensor (MAPS technology. The characterization test of various version of prototype chips at different phases of development has been performed. This contribution will provide the main characterization results obtained from the measurements performed at laboratories and using test beam for finalizing the pixel chip specification.

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

CERN Document Server

Llopart Cudie, Xavier; Campbell, M

2007-01-01

Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

CERN Document Server

Nachman, Benjamin Philip; The ATLAS collaboration

2017-01-01

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of $10^{15}$ 1 MeV $n_\\mathrm{eq}/\\mathrm{cm}^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This talk presents a digitization model that includes radiation damage effects to the ATLAS Pixel sensors for the first time. After a thorough description of the setup, predictions for basic Pixel cluster properties are presented alongside first validation studies with Run 2 collision data.

Neural network based cluster creation in the ATLAS silicon pixel detector

CERN Document Server

Selbach, K E; The ATLAS collaboration

2012-01-01

The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS pixel detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

Neural network based cluster creation in the ATLAS silicon Pixel Detector

CERN Document Server

Andreazza, A; The ATLAS collaboration

2013-01-01

The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

Online calibrations and performance of the ATLAS Pixel Detector

CERN Document Server

Keil, M; The ATLAS collaboration

2010-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

A prototype pixel readout chip for asynchronous detection applications

International Nuclear Information System (INIS)

Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

1991-01-01

A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

Development of active edge pixel sensors and four-side buttable modules using vertical integration technologies

Energy Technology Data Exchange (ETDEWEB)

Macchiolo, A., E-mail: Anna.Macchiolo@mpp.mpg.de [Max-Planck-Institut for Physics, Föhringer Ring 6, D-80805 Munich (Germany); Andricek, L. [Semiconductor Laboratory of the Max-Planck-Society, Otto Hahn Ring 6, D-81739 Munich (Germany); Moser, H.-G.; Nisius, R. [Max-Planck-Institut for Physics, Föhringer Ring 6, D-80805 Munich (Germany); Richter, R.H. [Semiconductor Laboratory of the Max-Planck-Society, Otto Hahn Ring 6, D-81739 Munich (Germany); Terzo, S.; Weigell, P. [Max-Planck-Institut for Physics, Föhringer Ring 6, D-80805 Munich (Germany)

2014-11-21

We present an R and D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 μm thick, produced at VTT (Finland) with an active edge technology, which considerably reduces the dead area at the periphery of the device. The sensors are interconnected with solder bump-bonding to the ATLAS FE-I3 and FE-I4 read-out chips, and characterised with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements will be discussed for devices before and after irradiation up to a fluence of 5×10{sub 15}n{sub eq}/cm{sup 2}. We will also report on the R and D activity to obtain Inter Chip Vias (ICVs) on the ATLAS read-out chip in collaboration with the Fraunhofer Institute EMFT. This step is meant to prove the feasibility of the signal transport to the newly created readout pads on the backside of the chips allowing for four side buttable devices without the presently used cantilever for wire bonding. The read-out chips with ICVs will be interconnected to thin pixel sensors, 75 μm and 150 μm thick, with the Solid Liquid Interdiffusion (SLID) technology, which is an alternative to the standard solder bump-bonding.

ATLAS Pixel IBL: Stave Quality Assurance

CERN Document Server

The ATLAS collaboration

2014-01-01

For Run 2 of the LHC a fourth innermost Pixel Detector layer on a smaller radius beam pipe has been installed in the ATLAS Detector to add redundancy against radiation damage of the current Pixel Detector and to ensure a high quality tracking and b-tagging performance of the Inner Detector over the coming years until the High Luminosity Upgrade. State of the art components have been produced and assembled onto support structures known as staves over the last two years. In total, 20 staves have been built and qualified in a designated Quality Assurance setup at CERN of which 14 have been integrated onto the beam pipe. Results from the testing are presented.

Results from the Commissioning of the ATLAS Pixel Detector

CERN Document Server

Ibragimov, I

2008-01-01

The ATLAS pixel detector is the innermost tracking detector of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. It has a total active area of 1.7 m2 of silicon read out by approximately 80 million electronic channels, which will detect particle tracks and decay vertices with a very high precision. After more than 10 years of development and construction it is the first time ever the whole detector has been operated together. The paper will illustrate the detector performance and give first results from the combined ATLAS cosmics runs.

3D silicon pixel detectors for the High-Luminosity LHC

CERN Document Server

Lange, J.

2016-01-01

3D silicon pixel detectors have been investigated as radiation-hard candidates for the innermost layers of the HL-LHC upgrade of the ATLAS pixel detector. 3D detectors are already in use today in the ATLAS IBL and AFP experiments. These are based on 50x250 um2 large pixels connected to the FE-I4 readout chip. Detectors of this generation were irradiated to HL-LHC fluences and demonstrated excellent radiation hardness with operational voltages as low as 180 V and power dissipation of 12--15 mW/cm2 at a fluence of about 1e16 neq/cm2, measured at -25 degree C. Moreover, to cope with the higher occupancies expected at the HL-LHC, a first run of a new generation of 3D detectors designed for the HL-LHC was produced at CNM with small pixel sizes of 50x50 and 25x100 um2, matched to the FE-I4 chip. They demonstrated a good performance in the laboratory and in beam tests with hit efficiencies of about 97% at already 1--2V before irradiation.

Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

Energy Technology Data Exchange (ETDEWEB)

Peschke, Richard

2017-03-15

As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

International Nuclear Information System (INIS)

Peschke, Richard

2017-03-01

As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

Effets de rayonnement sur les detecteurs au silicium a pixels du detecteur ATLAS

CERN Document Server

Lebel, Celine

2007-01-01

Two detection systems are using pixel silicon detectors in the ATLAS detector: the Pixel, which is the subdetector closest to the interaction point, and the MPX network. The activation of the materials present in the Pixel produced by radiation has been measured in two experiments which we performed at CERF (CERN) and NPI-ASCR (Czech Republic). These experimental studies of activation are com- pared with GEANT4 simulations. The results of these comparisons show that the simulation can predict the activities with a precision of an order of magnitude. They also show that GEANT4 fails to produce certain radioisotopes seen in the experimental activation studies. The contribution to background and the resid- ual doses due to the desintegration of the radioisotopes produced by fast neutrons (category in which falls the expected average neutron energy of 1 MeV in ATLAS) are extrapolated to ATLAS conditions. It is found that this background in the AT- LAS Pixel subdetector will be negligible and that the doses are we...

Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

Energy Technology Data Exchange (ETDEWEB)

Beimforde, Michael

2010-07-19

edge demonstrate that the active sensor area fraction can be increased to fulfill the requirements for the detector upgrades. A subset of sensors, irradiated up to the fluence expected at the sLHC demonstrated that thin sensors show a higher charge collection efficiency than expected from current radiation damage models. First thin diodes equipped with the SLID metallization and first test structures that were connected with SLID indicate that this novel interconnection as part of the ICV-SLID technology could be a suitable replacement for the present bump-bonding technology. Finally, a new calibration algorithm for the ATLAS pixel readout chips is presented which is used to lower the discriminator threshold from 4000 electrons to 2000 electrons, to account for the reduction of the signal size due to radiation damage and the reduced sensor thickness. (orig.)

Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

International Nuclear Information System (INIS)

Beimforde, Michael

2010-01-01

sensor area fraction can be increased to fulfill the requirements for the detector upgrades. A subset of sensors, irradiated up to the fluence expected at the sLHC demonstrated that thin sensors show a higher charge collection efficiency than expected from current radiation damage models. First thin diodes equipped with the SLID metallization and first test structures that were connected with SLID indicate that this novel interconnection as part of the ICV-SLID technology could be a suitable replacement for the present bump-bonding technology. Finally, a new calibration algorithm for the ATLAS pixel readout chips is presented which is used to lower the discriminator threshold from 4000 electrons to 2000 electrons, to account for the reduction of the signal size due to radiation damage and the reduced sensor thickness. (orig.)

Module and electronics developments for the ATLAS ITK pixel system

CERN Document Server

Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

2017-01-01

The ATLAS experiment is preparing for an extensive modification of its detectors in the course of the planned HL-LHC accelerator upgrade around 2025. The ATLAS upgrade includes the replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will be a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in 2017. In this paper an overview of the ongoing R\\&D activities on modules and electronics for the ATLAS ITk is given including the main developments and achievements in silicon planar and 3D sensor technologies, readout and power challenges.

arXiv Planar n-in-n quad module prototypes for the ATLAS ITk upgrade at HL-LHC

CERN Document Server

Gisen, A.; Burmeister, I.; Gößling, C.; Klingenberg, R.; Kröninger, K.; Lönker, J.; Weers, M.; Wizemann, F.

2017-12-15

In order to meet the requirements of the High Luminosity LHC (HL-LHC), it will be necessary to replace the current tracker of the ATLAS experiment. Therefore, a new all-silicon tracking detector is being developed, the so-called Inner Tracker (ITk). The use of quad chip modules is intended in its pixel region. These modules consist of a silicon sensor that forms a unit along with four read-out chips. The current ATLAS pixel detector consists of planar n-in-n silicon pixel sensors. Similar sensors and four FE-I4 read-out chips were assembled to first prototypes of planar n-in-n quad modules. The main focus of the investigation of these modules was the region between the read-out chips, especially the central area between all four read-out chips. There are special pixel cells placed on the sensor which cover the gap between the read-out chips. This contribution focuses on the characterization of a non-irradiated device, including important sensor characteristics, charge collection determined with radioactive so...

Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

International Nuclear Information System (INIS)

Macchiolo, A.; Beyer, J.; Rosa, A. La; Nisius, R.; Savic, N.

2017-01-01

The ATLAS experiment will undergo around the year 2025 a replacement of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) with a new 5-layer pixel system. Thin planar pixel sensors are promising candidates to instrument the innermost region of the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. The sensors of 50-150 μm thickness, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests. In particular active edge sensors have been investigated. The performance of two different versions of edge designs are compared: the first with a bias ring, and the second one where only a floating guard ring has been implemented. The hit efficiency at the edge has also been studied after irradiation at a fluence of 10 15  n eq /cm 2 . Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 μm 2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angles with respect to the short pixel direction. Results on the hit efficiency in this configuration are discussed for different sensor thicknesses.

Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

Energy Technology Data Exchange (ETDEWEB)

Viel, Simon, E-mail: sviel@lbl.gov [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Banerjee, Swagato [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Pranko, Aliaksandr [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Rieger, Julia [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); II Physikalisches Institut, Georg-August-Universität, Göttingen (Germany); Wolf, Julian [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Wu, Sau Lan; Yang, Hongtao [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States)

2016-09-21

In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN. - Highlights: • Extended inner pixel barrel layers are proposed for the ATLAS ITk upgrade. • Test beam results at small track incidence angles validate this ATLAS ITk design. • Long pixel clusters are reconstructed with high efficiency at low threshold values. • Excellent angular resolution is achieved using pixel cluster length information.

Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

International Nuclear Information System (INIS)

Viel, Simon; Banerjee, Swagato; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian; Wu, Sau Lan; Yang, Hongtao

2016-01-01

In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN. - Highlights: • Extended inner pixel barrel layers are proposed for the ATLAS ITk upgrade. • Test beam results at small track incidence angles validate this ATLAS ITk design. • Long pixel clusters are reconstructed with high efficiency at low threshold values. • Excellent angular resolution is achieved using pixel cluster length information.

Probing and irradiation tests of ALICE pixel chip wafers and sensors

CERN Document Server

Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

2004-01-01

In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

International Nuclear Information System (INIS)

Rubinskiy, Igor

2013-01-01

The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–2014). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase in the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector. An overview of the sensor technologies' qualification with particular emphasis on irradiation and beam tests is presented. -- Highlights: ► The ATLAS inner tracker will be extended with a so called Insertable B-Layer (IBL). ► The IBL modules are required to withstand irradiation up to 5×10 15 n eq /cm 2 . ► Two types of silicon pixel detector technologies (Planar and 3D) were tested in beam. ► The irradiated sensor efficiency exceeds 97% both with and without magnetic field. ► The leakage current, power dissipation, module active area ratio requirements are met.

Planar n-in-n quad module prototypes for the ATLAS ITk upgrade at HL-LHC

Science.gov (United States)

Gisen, A.; Altenheiner, S.; Burmeister, I.; Gößling, C.; Klingenberg, R.; Kröninger, K.; Lönker, J.; Weers, M.; Wizemann, F.

2017-12-01

In order to meet the requirements of the High Luminosity LHC (HL-LHC), it will be necessary to replace the current tracker of the ATLAS experiment. Therefore, a new all-silicon tracking detector is being developed, the so-called Inner Tracker (ITk). The use of quad chip modules is intended in its pixel region. These modules consist of a silicon sensor that forms a unit along with four read-out chips. The current ATLAS pixel detector consists of planar n-in-n silicon pixel sensors. Similar sensors and four FE-I4 read-out chips were assembled to first prototypes of planar n-in-n quad modules. The main focus of the investigation of these modules was the region between the read-out chips, especially the central area between all four read-out chips. There are special pixel cells placed on the sensor which cover the gap between the read-out chips. This contribution focuses on the characterization of a non-irradiated device, including important sensor characteristics, charge collection determined with radioactive sources as well as hit efficiency measurements, performed in the laboratory and at testbeams. In addition, first laboratory results of an irradiated device are presented.

Fabrication of ATLAS pixel detector prototypes at IRST

International Nuclear Information System (INIS)

Boscardin, M.; Betta, G.-F. Dalla; Gregori, P.; Zen, M.; Zorzi, N.

2001-01-01

We report on the development of a fabrication technology for n-on-n silicon pixel detectors oriented to the ATLAS experiment at LHC. The main processing issues and some selected results from the electrical characterization of detector prototypes and related test structures are presented and discussed

Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

CERN Document Server

Ducourthial, Audrey; The ATLAS collaboration

2017-01-01

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15} n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside...

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Risti{c}, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Modeling radiation damage to pixel sensors in the ATLAS detector

CERN Document Server

Ducourthial, Audrey; The ATLAS collaboration

2017-01-01

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15}n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside ...

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Gaudiello, Andrea; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

CERN Document Server

Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

2014-01-01

In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

Science.gov (United States)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

Development of the MCM-D technique for pixel detector modules

International Nuclear Information System (INIS)

Grah, C.

2005-03-01

This thesis treats a copper--polymer based thin film technology, the MCM-D technique and its application when building hybrid pixel detector modules. The ATLAS experiment at the LHC will be equipped with a pixel detector system. The basic mechanical units of the pixel detector are multi chip modules. The main components of these modules are: 16 electronic chips, a controller chip and a large sensor tile, featuring more than 46000 sensor cells. MCM-D is a superior technique to build the necessary signal bus system and the power distribution system directly on the active sensor tile. In collaboration with the Fraunhofer Institute for Reliability and Microintegration, IZM, the thin film process is reviewed and enhanced. The multi layer system was designed and optimized for the interconnection system as well as for the 46000 pixel contacts. Laboratory measurements on prototypes prove that complex routing schemes for geometrically optimized single chips are suitable and have negligible influence on the front--end chips performance. A full scale MCM-D module has been built and it is shown that the technology is suitable to build pixel detector modules. Further tests include the investigation of the impact of hadronic irradiation on the thin film layers. Single chip assemblies have been operated in a test beam environment and the feasibility of the optimization of the sensors could be shown. A review on the potential as well as the perspective for the MCM-D technique in future experiments is given

Online Calibration and Performance of the ATLAS Pixel Detector

CERN Document Server

Keil, M

2011-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

CERN Document Server

Giugliarelli, Gilberto; The ATLAS collaboration

2018-01-01

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS experiment. They constitute the part of ATLAS closest to the interaction point and for this reason they will be exposed – over their lifetime – to a significant amount of radiation: prior to the HL-LHC, the innermost layers will receive a fluence of 10^15 neq/cm2 and their HL–LHC upgrades will have to cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

Survey of the ATLAS Pixel Detector Components

International Nuclear Information System (INIS)

Andreazza, A.; Kostyukhim, V.; Madaras, R.

2008-01-01

This document provides a description of the survey performed on different components of the ATLAS Pixel Detector at different stages of its assembly. During the production of the ATLAS pixel detector great care was put in the geometrical survey of the location of the sensitive area of modules. This had a double purpose: (1) to provide a check of the quality of the assembly procedure and assure tolerances in the geometrical assembly were met; and (2) to provide an initial point for the alignment (the so called 'as-built detector'), better than the ideal geometry. Since direct access to the sensitive area becomes more and more difficult with the progress of the assembly, the survey needed to be performed at different stages: after module loading on the local supports (sectors and staves) and after assembly of the local supports in disks or halfshells. Different techniques were used, including both optical 2D and 3D surveys and mechanical survey. This document summarizes the survey procedures, the analysis done on the collected data and how survey data are stored in case they will need to be accessed in the future

Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅10 15 $n_{eq}$ /cm 2

CERN Document Server

Weigell, P; Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H

2011-01-01

A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to 2⋅10 15 \\,\

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Operational experience of ATLAS SCT and Pixel Detector

CERN Document Server

Kocian, Martin; The ATLAS collaboration

2017-01-01

The ATLAS Inner Detector based on silicon sensors is consisting of a strip detector (SCT) and a pixel detector. It is the crucial component for vertexing and tracking in the ATLAS experiment. With the excellent performance of the LHC well beyond the original specification the silicon tracking detectors are facing substantial challenges in terms of data acquisition, radiation damage to the sensors, and SEUs in the readout ASICs. The approaches on how the detector systems cope with the demands of high luminosity operation while maintaining excellent performance through hardware upgrades, software and firmware algorithms, and operational settings, are presented.

Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2$\\cdot 10^{15}$\\,n$_{\\mathrm{eq}}$/cm$^2$

CERN Document Server

INSPIRE-00237859; Beimforde, M.; Macchiolo, A.; Moser, H.G.; Nisius, R.; Richter, R.H.

2011-01-01

A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to $2\\cdot10^{15}$\\,\

Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

Energy Technology Data Exchange (ETDEWEB)

Germic, Leonard; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Havranek, Miroslav [University of Bonn, Bonn (Germany); Institute of Physics of the Academy of Sciences, Prague (Czech Republic)

2015-07-01

The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges coming from the higher hit rate will have to be solved by designing faster and more complex circuits, while at the same time keeping in mind very high radiation hardness requirements. Therefore matching the specification set by the high luminosity upgrade requires a large R and D effort. Our group is participating in such a joint development * namely the RD53 collaboration * which goal is to design a new pixel chip using an advanced 65 nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology will be shown together with a comparison with older technologies (130 nm, 250 nm). Most of the talk is allocated to presenting some of the circuits designed by our group, along with their performance measurement results.

Silicon sensor technologies for ATLAS IBL upgrade

CERN Document Server

Grenier, P; The ATLAS collaboration

2011-01-01

New pixel sensors are currently under development for ATLAS Upgrades. The first upgrade stage will consist in the construction of a new pixel layer that will be installed in the detector during the 2013 LHC shutdown. The new layer (Insertable-B-Layer, IBL) will be inserted between the inner most layer of the current pixel detector and the beam pipe at a radius of 3.2cm. The expected high radiation levels require the use of radiation hard technology for both the front-end chip and the sensor. Two different pixel sensor technologies are envisaged for the IBL. The sensor choice will occur in July 2011. One option is developed by the ATLAS Planar Pixel Sensor (PPS) Collaboration and is based on classical n-in-n planar silicon sensors which have been used for the ATLAS Pixel detector. For the IBL, two changes were required: The thickness was reduced from 250 um to 200 um to improve the radiation hardness. In addition, so-called "slim edges" were designed to reduce the inactive edge of the sensors from 1100 um to o...

Radiation Damage Monitoring in the ATLAS Pixel Detector

CERN Document Server

Seidel, S

2013-01-01

We describe the implementation of radiation damage monitoring using measurement of leakage current in the ATLAS silicon pixel sensors. The dependence of the leakage current upon the integrated luminosity is presented. The measurement of the radiation damage corresponding to integrated luminosity 5.6 fb$^{-1}$ is presented along with a comparison to the theoretical model.

Recent achievements of the ATLAS upgrade Planar Pixel Sensors R and D project

International Nuclear Information System (INIS)

Casse, G

2014-01-01

The ATLAS upgrade Planar Pixel Sensors (PPS) project aims to prove the suitability of silicon detectors processed with planar technology to equip all layers of the pixel vertex detector proposed for the upgrade of the ATLAS experiment for the future High Luminosity LHC at CERN (HL-LHC). The detectors need to be radiation tolerant to the extreme fluences expected to be received during the experimental lifetime, with optimised geometry for full coverage and high granularity and affordable in term of cost, due to the relatively large area of the upgraded ATLAS detector system. Here several solutions for the detector geometry and results with radiation hard technologies (n-in-n, n-in-p) are discussed

Preliminary Results of 3D-DDTC Pixel Detectors for the ATLAS Upgrade

Energy Technology Data Exchange (ETDEWEB)

La Rosa, Alessandro; /CERN; Boscardin, M.; /Fond. Bruno Kessler, Povo; Dalla Betta, G.-F.; /Trento U. /INFN, Trento; Darbo, G.; Gemme, C.; /INFN, Genoa; Pernegger, H.; /CERN; Piemonte, C.; /Fond. Bruno Kessler, Povo; Povoli, M.; /Trento U. /INFN, Trento; Ronchin, S.; /Fond. Bruno Kessler, Povo; Zoboli, A.; /Trento U. /INFN, Trento; Zorzi, N.; /Fond. Bruno Kessler, Povo; Bolle, E.; /Oslo U.; Borri, M.; /INFN, Turin /Turin U.; Da Via, C.; /Manchester U.; Dong, S.; /SLAC; Fazio, S.; /Calabria U.; Grenier, P.; /SLAC; Grinstein, S.; /Barcelona, IFAE; Gjersdal, H.; /Oslo U.; Hansson, P.; /SLAC; Huegging, F.; /Bonn U. /SLAC /INFN, Turin /Turin U. /Oslo U. /Bergen U. /Oslo U. /Prague, Tech. U. /Bonn U. /SUNY, Stony Brook /Bonn U. /SLAC

2012-04-04

3D Silicon sensors fabricated at FBK-irst with the Double-side Double Type Column (DDTC) approach and columnar electrodes only partially etched through p-type substrates were tested in laboratory and in a 1.35 Tesla magnetic field with a 180 GeV pion beam at CERN SPS. The substrate thickness of the sensors is about 200 {mu}m, and different column depths are available, with overlaps between junction columns (etched from the front side) and ohmic columns (etched from the back side) in the range from 110 {mu}m to 150 {mu}m. The devices under test were bump bonded to the ATLAS Pixel readout chip (FEI3) at SELEX SI (Rome, Italy). We report leakage current and noise measurements, results of functional tests with Am{sup 241} {gamma}-ray sources, charge collection tests with Sr90 {beta}-source and an overview of preliminary results from the CERN beam test.

Modeling radiation damage to pixel sensors in the ATLAS detector

Science.gov (United States)

Ducourthial, A.

2018-03-01

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC) . As the closest detector component to the interaction point, these detectors will be subject to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC) [1], the innermost layers will receive a fluence in excess of 1015 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is essential in order to make accurate predictions for current and future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects on the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside early studies with LHC Run 2 proton-proton collision data.

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

Science.gov (United States)

Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

2006-12-01

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

Evaluation of testing strategies for the radiation tolerant ATLAS n **+-in-n pixel sensor

CERN Document Server

Klaiber Lodewigs, Jonas M

2003-01-01

The development of particle tracker systems for high fluence environments in new high-energy physics experiments raises new challenges for the development, manufacturing and reliable testing of radiation tolerant components. The ATLAS pixel detector for use at the LHC, CERN, is designed to cover an active sensor area of 1.8 m**2 with 1.1 multiplied by 10 **8 read-out channels usable for a particle fluence up to 10 **1**5 cm**-**2 (1 MeV neutron equivalent) and an ionization dose up to 500 kGy of mainly charged hadron radiation. To cope with such a harsh environment the ATLAS Pixel Collaboration has developed a radiation hard n **+-in-n silicon pixel cell design with a standard cell size of 50 multiplied by 400 mum**2. Using this design on an oxygenated silicon substrate, sensor production has started in 2001. This contribution describes results gained during the development of testing procedures of the ATLAS pixel sensor and evaluates quality assurance procedures regarding their relevance for detector operati...

Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

Energy Technology Data Exchange (ETDEWEB)

Andricek, L. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany); Beimforde, M., E-mail: mibei@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Macchiolo, A. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Moser, H.-G. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany); Nisius, R. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Richter, R.H. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany)

2011-04-21

A new pixel module concept is presented utilizing thin sensors and a novel vertical integration technique for the ATLAS pixel detector in view of the foreseen LHC luminosity upgrades. A first set of pixel sensors with active thicknesses of 75 and 150{mu}m has been produced from wafers of standard thickness using a thinning process developed at the Max-Planck-Institut Halbleiterlabor (HLL) and the Max-Planck-Institut fuer Physik (MPP). Pre-irradiation characterizations of these sensors show a very good device yield and high break down voltage. First proton irradiations up to a fluence of 10{sup 15} n{sub eq} cm{sup -2} have been carried out and their impact on the electrical properties of thin sensors has been studied. The novel ICV-SLID vertical integration technology will allow for routing signals vertically to the back side of the readout chips. With this, four-side buttable detector devices with an increased active area fraction are made possible. A first production of SLID test structures was performed and showed a high connection efficiency for different pad sizes and a mild sensitivity to disturbances of the surface planarity.

Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

International Nuclear Information System (INIS)

Andricek, L.; Beimforde, M.; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.

2011-01-01

A new pixel module concept is presented utilizing thin sensors and a novel vertical integration technique for the ATLAS pixel detector in view of the foreseen LHC luminosity upgrades. A first set of pixel sensors with active thicknesses of 75 and 150μm has been produced from wafers of standard thickness using a thinning process developed at the Max-Planck-Institut Halbleiterlabor (HLL) and the Max-Planck-Institut fuer Physik (MPP). Pre-irradiation characterizations of these sensors show a very good device yield and high break down voltage. First proton irradiations up to a fluence of 10 15 n eq cm -2 have been carried out and their impact on the electrical properties of thin sensors has been studied. The novel ICV-SLID vertical integration technology will allow for routing signals vertically to the back side of the readout chips. With this, four-side buttable detector devices with an increased active area fraction are made possible. A first production of SLID test structures was performed and showed a high connection efficiency for different pad sizes and a mild sensitivity to disturbances of the surface planarity.

Development of Pixel Front-End Electronics using Advanced Deep Submicron CMOS Technologies

CERN Document Server

Havránek, Miroslav; Dingfelder, Jochen

The content of this thesis is oriented on the R&D; of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore’s laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key pa...

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

Energy Technology Data Exchange (ETDEWEB)

Gonella, Laura

2013-10-15

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study.

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

International Nuclear Information System (INIS)

Gonella, Laura

2013-10-01

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study.

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

CERN Document Server

Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

2014-01-01

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

Radiation Damage Modeling for 3D Pixel Sensors in the ATLAS Detector

CERN Document Server

Wallangen, Veronica; The ATLAS collaboration

2017-01-01

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

Science.gov (United States)

Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

2008-02-01

We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

Single Event Upsets in the ATLAS IBL Front End ASICs

CERN Document Server

Rozanov, Alexandre; The ATLAS collaboration

2018-01-01

During operation at instantaneous luminosities of up to 2.1 1034 cm2 s−1 frontend chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, amongst other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques are presented.

Robustness of the ATLAS pixel clustering neural network algorithm

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

2016-01-01

Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. In the ATLAS track reconstruction algorithm, an artificial neural network is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The robustness of the neural network algorithm is presented, probing its sensitivity to uncertainties in the detector conditions. The robustness is studied by evaluating the stability of the algorithm's performance under a range of variations in the inputs to the neural networks. Within reasonable variation magnitudes, the neural networks prove to be robust to most variation types.

ATLAS Pixel Detector Design For HL-LHC

CERN Document Server

Smart, Ben; The ATLAS collaboration

2016-01-01

The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline. High-eta particles will therefore hit these sensors at shallow angles, leaving elongated charge clusters. The length of such a charge cluster can be used to estimate the angle of the passing particle. This information can then be used in track reconstruction to improve tracking efficiency and reduce fake rates. Inclined designs ...

Tests of UFXC32k chip with CdTe pixel detector

Science.gov (United States)

Maj, P.; Taguchi, T.; Nakaye, Y.

2018-02-01

The paper presents the performance of the UFXC32K—a hybrid pixel detector readout chip working with CdTe detectors. The UFXC32K has a pixel pitch of 75 μm and can cope with both input signal polarities. This functionality allows operating with widely used silicon sensors collecting holes and CdTe sensors collecting electrons. This article describes the chip focusing on solving the issues connected to high-Z sensor material, namely high leakage currents, slow charge collection time and thick material resulting in increased charge-sharring effects. The measurements were conducted with higher X-ray energies including 17.4 keV from molybdenum. Conclusions drawn inside the paper show the UFXC32K's usability for CdTe sensors in high X-ray energy applications.

The ATLAS Insertable B-Layer Detector (IBL)

CERN Document Server

Huegging, F; The ATLAS collaboration

2010-01-01

The upgrade for the ATLAS detector will undergo different phases towards SLHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during a longer shutdown of the LHC machine, the so-called Phase I Upgrade. The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of about 3.2 cm. The IBL requires the development of several new technologies to cope with the increase of radiation and pixel occupancy as well as to improve the physics performance of the existing pixel detector. In order to achieve these goals the pixel size is reduced and the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system. Main component of the module development for the IBL is the new ATLAS pixel readout chip, FE-I4, designed in 130 nm technology which features an array of 80 by 336 pixels with a pixel size of 50x250 µ...

Characterisation of novel thin n-in-p planar pixel modules for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Beyer, J.-C.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Savic, N.; Taibah, R.

2018-01-01

In view of the high luminosity phase of the LHC (HL-LHC) to start operation around 2026, a major upgrade of the tracker system for the ATLAS experiment is in preparation. The expected neutron equivalent fluence of up to 2.4×1016 1 MeV neq./cm2 at the innermost layer of the pixel detector poses the most severe challenge. Thanks to their low material budget and high charge collection efficiency after irradiation, modules made of thin planar pixel sensors are promising candidates to instrument these layers. To optimise the sensor layout for the decreased pixel cell size of 50×50 μm2, TCAD device simulations are being performed to investigate the charge collection efficiency before and after irradiation. In addition, sensors of 100-150 μm thickness, interconnected to FE-I4 read-out chips featuring the previous generation pixel cell size of 50×250 μm2, are characterised with testbeams at the CERN-SPS and DESY facilities. The performance of sensors with various designs, irradiated up to a fluence of 1×1016 neq./cm2, is compared in terms of charge collection and hit efficiency. A replacement of the two innermost pixel layers is foreseen during the lifetime of HL-LHC . The replacement will require several months of intervention, during which the remaining detector modules cannot be cooled. They are kept at room temperature, thus inducing an annealing. The performance of irradiated modules will be investigated with testbeam campaigns and the method of accelerated annealing at higher temperatures.

Thin hybrid pixel assembly fabrication development with backside compensation layer

Energy Technology Data Exchange (ETDEWEB)

Bates, R., E-mail: richard.bates@glasgow.ac.uk [Experimental Particle Physics Group, SUPA School of Physics and Astronomy, The University of Glasgow, Glasgow G12 8QQ (United Kingdom); Buttar, C.; McMullen, T.; Cunningham, L.; Ashby, J.; Doherty, F. [Experimental Particle Physics Group, SUPA School of Physics and Astronomy, The University of Glasgow, Glasgow G12 8QQ (United Kingdom); Pares, G.; Vignoud, L.; Kholti, B. [CEA Leti, MINATEC, 17 rue des Martyrs, F38054, Grenoble (France); Vahanen, S. [Advacam Oy, Tietotie 3, 02150 Espoo (Finland)

2017-02-11

The ATLAS and CMS experiments will both replace their entire tracking systems for operation at the HL-LHC in 2026. This will include a significantly larger pixel systems, for example, for ATLAS approximately 15 m{sup 2}. To keep the tracker material budget low it is crucial to minimize the mass of the pixel modules via thinning both the sensor and readout chip to about 150 μm each. The bump yield of thin module assemblies using solder based bump bonding can be problematic due to wafer bowing during solder reflow at high temperature. A new bump-bonding process using backside compensation on the readout chip to address the issue of low yield will be presented. The objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the backside of the wafer. A SiN and Al:Si stack has been chosen for the backside layer. The bow reducing effect of applying a backside compensation layer will be demonstrated using the FE-I4 wafer. The world's first results from assemblies produced from readout wafers thinned to 100 μm with a stress compensation layer are presented with bond yields close to 100% measured using the FE-I4 readout chip.

Fabrication of a high-density MCM-D for a pixel detector system using a BCB/Cu technology

CERN Document Server

Topper, M; Engelmann, G; Fehlberg, S; Gerlach, P; Wolf, J; Ehrmann, O; Becks, K H; Reichl, H

1999-01-01

The MCM-D which is described here is a prototype for a pixel detector system for the planned Large Hadron Collider (LHC) at CERN, Geneva. The project is within the ATLAS experiment. The module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 readout chips, each serving 24*160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and power distribution buses. The extremely high wiring density which is necessary to interconnect the readout chips was achieved using a thin film copper/photo-BCB process above the pixel array. The bumping of the readout chips was done by PbSn electroplating. All dice are then attached by flip-chip assembly to the sensor diodes and the local buses. The focus of this paper is a detailed description of the technologies for the fabrication of this advanced MCM-D. (10 refs).

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

Energy Technology Data Exchange (ETDEWEB)

Aglieri Rinella, Gianluca, E-mail: gianluca.aglieri.rinella@cern.ch

2017-02-11

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10{sup −5} and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm{sup 2} for the application in the Inner Barrel Layers and below 20 mW/cm{sup 2} for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported. - Highlights: • The ALPIDE chip, an innovative CMOS pixel particle detector is described. • It achieves excellent detection performance figures and very low power consumption. • The characterization of prototypes confirms the achievement of the specifications.

A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

CERN Document Server

Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P; 10.1088/1748-0221/5/12/C12025

2010-01-01

The presented R&D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut für Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 1016neqcm−2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the ...

Development of a serial powering scheme and a versatile characterization system for the ATLAS pixel detector upgrade

Energy Technology Data Exchange (ETDEWEB)

Filimonov, Viacheslav

2017-08-15

In order to increase the probability of new discoveries the LHC will be upgraded to the HL-LHC. The upgrade of the ATLAS detector is an essential part of this program. The entire ATLAS tracking system will be replaced by an all-silicon detector called Inner Tracker (ITk) which should be able to withstand the increased luminosity of 5 x 10{sup 34} cm{sup -2}s{sup -1}. The work presented in this thesis is focused on the ATLAS ITk pixel detector upgrade. Advanced silicon pixel detectors will be an essential part of the ITk pixel detector where they will be used for tracking and vertexing. Characterization of the pixel detectors is one of the required tasks for a successful ATLAS tracker upgrade. Therefore, the work presented in this thesis includes the development of a versatile and modular test system for advanced silicon pixel detectors for the HL-LHC. The performance of the system is verified. Single and quad FE-I4 modules functionalities are characterized with the developed system. The reduction of the material budget of the ATLAS ITk pixel detector is essential for a successful operation at high luminosity. Therefore, a low mass, efficient power distribution scheme to power detector modules (serial powering scheme) is investigated as well in the framework of this thesis. A serially powered pixel detector prototype is built with all the components that are needed for current distribution, data transmission, sensor biasing, bypassing and redundancy in order to prove the feasibility of implementing the serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules are made with the help of the developed readout system.

Development of a serial powering scheme and a versatile characterization system for the ATLAS pixel detector upgrade

International Nuclear Information System (INIS)

Filimonov, Viacheslav

2017-08-01

In order to increase the probability of new discoveries the LHC will be upgraded to the HL-LHC. The upgrade of the ATLAS detector is an essential part of this program. The entire ATLAS tracking system will be replaced by an all-silicon detector called Inner Tracker (ITk) which should be able to withstand the increased luminosity of 5 x 10 34 cm -2 s -1 . The work presented in this thesis is focused on the ATLAS ITk pixel detector upgrade. Advanced silicon pixel detectors will be an essential part of the ITk pixel detector where they will be used for tracking and vertexing. Characterization of the pixel detectors is one of the required tasks for a successful ATLAS tracker upgrade. Therefore, the work presented in this thesis includes the development of a versatile and modular test system for advanced silicon pixel detectors for the HL-LHC. The performance of the system is verified. Single and quad FE-I4 modules functionalities are characterized with the developed system. The reduction of the material budget of the ATLAS ITk pixel detector is essential for a successful operation at high luminosity. Therefore, a low mass, efficient power distribution scheme to power detector modules (serial powering scheme) is investigated as well in the framework of this thesis. A serially powered pixel detector prototype is built with all the components that are needed for current distribution, data transmission, sensor biasing, bypassing and redundancy in order to prove the feasibility of implementing the serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules are made with the help of the developed readout system.

Single Event Upsets in the ATLAS IBL Front End ASICs

CERN Document Server

Rozanov, Alexander; The ATLAS collaboration

2018-01-01

During operation at instantaneous luminosities of up to 2.1 10^{34} cm^{-2} s^{-1} the front end chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, among other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques will be presented.

Operational Experience and Performance with the ATLAS Pixel detector

CERN Document Server

Yang, Hongtao; The ATLAS collaboration

2018-01-01

In this presentation, I will discuss the operation of ATLAS Pixel Detector during Run 2 proton-proton data-taking at √s=13 TeV in 2017. The topics to be covered include 1) the bandwidth issue and how it is mitigated through readout upgrade and threshold adjustment; 2) the auto-corrective actions; 3) monitoring of radiation effects.

Development of a counting pixel detector for 'Digitales Roentgen'

International Nuclear Information System (INIS)

Lindner, M.

2001-08-01

The development of a single photon counting X-ray imaging detector for medical applications using hybrid pixel detectors is reported. The electronics development from the first prototype derived from detector development for particle physics experiments (ATLAS) to the imaging chip MPEC (multi picture element counters) for medical applications is described. This chip consists of 32 x 32 pixels of 200 μm x 200 μm size, each containing the complete read out electronics, i.e. an amplifier, two discriminators with adjustable thresholds and two 18-bit linear feedback shift-counters allowing energy windowing for contrast increase. Results on electronics performance are shown as well as measurements with several semiconductor materials (Si, GaAs, CdTe). Important aspects like detection efficiency, sensor homogeneity, linearity and spatial resolution are discussed. (orig.)

Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

CERN Document Server

Rossini, Lorenzo; The ATLAS collaboration

2018-01-01

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High- Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time and considers both planar and 3D sensor designs. In addition to thoroughly describing the setup, we compare predictions for basic...

Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

CERN Document Server

Giugliarelli, Gilberto; The ATLAS collaboration

2017-01-01

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

CERN Document Server

Wallangen, Veronica; The ATLAS collaboration

2017-01-01

Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10$^{15}$ n$_\\mathrm{eq}$/cm$^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This work presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS detector.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Directory of Open Access Journals (Sweden)

Nanjian Wu

2009-07-01

Full Text Available A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Development of Micromegas-like gaseous detectors using a pixel readout chip as collecting anode

International Nuclear Information System (INIS)

Chefdeville, M.

2009-01-01

This thesis reports on the fabrication and test of a new gaseous detector with a very large number of readout channels. This detector is intended for measuring the tracks of charged particles with an unprecedented sensitivity to single electrons of almost 100 %. It combines a metal grid for signal amplification called the Micromegas with a pixel readout chip as signal collecting anode and is dubbed GridPix. GridPix is a potential candidate for a sub-detector at a future electron linear collider (ILC) foreseen to work in parallel with the LHC around 2020--2030. The tracking capability of GridPix is best exploited if the Micromegas is integrated on the pixel chip. This integrated grid is called InGrid and is precisely fabricated by wafer post-processing. The various steps of the fabrication process and the measurements of its gain, energy resolution and ion back-flow property are reported in this document. Studies of the response of the complete detector formed by an InGrid and a TimePix pixel chip to X-rays and cosmic particles are also presented. In particular, the efficiency for detecting single electrons and the point resolution in the pixel plane are measured. Implications for a GridPix detector at ILC are discussed. (author)

The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

International Nuclear Information System (INIS)

Marconi, S; Christiansen, J; Conti, E; Placidi, P; Hemperek, T

2014-01-01

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared

The hardware of the ATLAS Pixel Detector Control System

International Nuclear Information System (INIS)

Henss, T; Andreani, A; Boek, J; Boyd, G; Citterio, M; Einsweiler, K; Kersten, S; Kind, P; Lantzsch, K; Latorre, S; Maettig, P; Meroni, C; Sabatini, F; Schultes, J

2007-01-01

The innermost part of the ATLAS (A Toroidal LHC ApparatuS) experiment, which is currently under construction at the LHC (Large Hadron Collider), will be a silicon pixel detector comprised of 1744 individual detector modules. To operate these modules, the readout electronics, and other detector components, a complex power supply and control system is necessary. The specific powering and control requirements, as well as the custom made components of our power supply and control systems, are described. These include remotely programmable regulator stations, the power supply system for the optical transceivers, several monitoring units, and the Interlock System. In total, this comprises the Pixel Detector Control System (DCS)

Serial powering of pixel modules

CERN Document Server

Stockmanns, Tobias; Hügging, Fabian Georg; Peric, I; Runólfsson, O; Wermes, Norbert

2003-01-01

Modern pixel detectors for the next generation of high-energy collider experiments like LHC use readout electronics in deep sub- micron technology. Chips in this technology need a low supply voltage of 2-2.5 V alongside high current consumption to achieve the desired performance. The high supply current leads to significant voltage drops in the long and low mass supply cables so that voltage fluctuations at the chips are induced, when the supply current changes. This problem scales with the number of modules when connected in parallel to the power supplies. An alternative powering scheme connects several modules in series resulting in a higher supply voltage but a lower current consumption of the chain and therefore a much lower voltage drop in the cables. In addition the amount of cables needed to supply the detector is vastly reduced. The concept and features of serial powering are presented and studies of the implementation of this technology as an alternative for the ATLAS pixel detector are shown. In par...

Dead-time free pixel readout architecture for ATLAS front-end IC

CERN Document Server

Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

1999-01-01

A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at the HL-LHC

International Nuclear Information System (INIS)

Macchiolo, A.; Andricek, L.; Ellenburg, M.; Moser, H.G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

2013-01-01

This R and D activity is focused on the development of new modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The performance after irradiation of n-in-p pixel sensors of different active thicknesses is studied, together with an investigation of a novel interconnection technique offered by the Fraunhofer Institute EMFT in Munich, the Solid–Liquid-InterDiffusion (SLID), which is an alternative to the standard solder bump-bonding. The pixel modules are based on thin n-in-p sensors, with an active thickness of 75μm or 150μm, produced at the MPI Semiconductor Laboratory (MPI HLL) and on 100μm thick sensors with active edges, fabricated at VTT, Finland. Hit efficiencies are derived from beam test data for thin devices irradiated up to a fluence of 4×10 15 n eq /cm 2 . For the active edge devices, the charge collection properties of the edge pixels before irradiation are discussed in detail, with respect to the inner ones, using measurements with radioactive sources. Beyond the active edge sensors, an additional ingredient needed to design four side buttable modules is the possibility of moving the wire bonding area from the chip surface facing the sensor to the backside, avoiding the implementation of the cantilever extruding beyond the sensor area. The feasibility of this process is under investigation with the FE-I3 SLID modules, where Inter Chip Vias are etched, employing an EMFT technology, with a cross section of 3μm×10μm, at the positions of the original wire bonding pads

Thin n-in-p pixel sensors and the SLID-ICV vertical integration technology for the ATLAS upgrade at the HL-LHC

Energy Technology Data Exchange (ETDEWEB)

Macchiolo, A., E-mail: Anna.Macchiolo@mpp.mpg.de [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Andricek, L. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 München (Germany); Ellenburg, M. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Moser, H.G. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 München (Germany); Nisius, R. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Richter, R.H. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany); Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 München (Germany); Terzo, S.; Weigell, P. [Max-Planck-Institut für Physik, Föhringer Ring 6, D-80805 München (Germany)

2013-12-11

This R and D activity is focused on the development of new modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The performance after irradiation of n-in-p pixel sensors of different active thicknesses is studied, together with an investigation of a novel interconnection technique offered by the Fraunhofer Institute EMFT in Munich, the Solid–Liquid-InterDiffusion (SLID), which is an alternative to the standard solder bump-bonding. The pixel modules are based on thin n-in-p sensors, with an active thickness of 75μm or 150μm, produced at the MPI Semiconductor Laboratory (MPI HLL) and on 100μm thick sensors with active edges, fabricated at VTT, Finland. Hit efficiencies are derived from beam test data for thin devices irradiated up to a fluence of 4×10{sup 15}n{sub eq}/cm{sup 2}. For the active edge devices, the charge collection properties of the edge pixels before irradiation are discussed in detail, with respect to the inner ones, using measurements with radioactive sources. Beyond the active edge sensors, an additional ingredient needed to design four side buttable modules is the possibility of moving the wire bonding area from the chip surface facing the sensor to the backside, avoiding the implementation of the cantilever extruding beyond the sensor area. The feasibility of this process is under investigation with the FE-I3 SLID modules, where Inter Chip Vias are etched, employing an EMFT technology, with a cross section of 3μm×10μm, at the positions of the original wire bonding pads.

Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

CERN Document Server

Rossini, Lorenzo; The ATLAS collaboration

2018-01-01

Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of 10^15 neq/cm^2 and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current and future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time and considers both planar and 3D sensor designs. In addition to thoroughly describing the setup, we compare predictions for b...

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

CERN Document Server

Aglieri Rinella, Gianluca

2017-01-01

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm2 for the application in the Inner Barrel Layers and below 20 mW/cm2 for the Outer Barrel Layers, ...

Upgrade of the BOC for the ATLAS Pixel Insertable B-Layer

CERN Document Server

Dopke, J; Heima, T; Kugel, A; Mattig, P; Schroer, N; Zeitnitz, C

2009-01-01

The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

Operational Experience of the ATLAS SemiConductor Tracker and Pixel Detector

CERN Document Server

Robinson, Dave; The ATLAS collaboration

2016-01-01

The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

The Upgraded Pixel Detector of the ATLAS Experiment for Run-2

CERN Document Server

Ferrere, Didier; The ATLAS collaboration

2016-01-01

Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

Production and characterization of SLID interconnected n-in-p pixel modules with 75 micron thin silicon sensors

CERN Document Server

Andricek, L; Macchiolo, A; Moser, H.G; Nisius, R; Richter, R.H; Terzo, S; Weigell, P

2014-01-01

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. T...

Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

CERN Document Server

Andricek, L; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

2014-01-01

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tunability, charge collection, cluster sizes and hit efficiencies. Targeting at ...

Development of thin pixel sensors and a novel interconnection technology for the SLHC

International Nuclear Information System (INIS)

Macchiolo, A.; Andricek, L.; Beimforde, M.; Dubbert, J.; Ghodbane, N.; Kortner, O.; Kroha, H.; Moser, H.G.; Nisius, R.; Richter, R.H.

2008-01-01

We present an R and D activity aiming to develop a new detector concept in the framework of the ATLAS pixel detector upgrade in view of the Super-LHC. The new devices combine 75-150 μm thick pixels sensors with a vertical integration technology. A new production of thin pixel sensors on n- and p-type material is under way at the MPI Semiconductor Laboratory. These devices will be connected to the ATLAS read-out electronics with the new Solid-Liquid InterDiffusion technique as an alternative to the bump-bonding process. We also plan for the signals to be extracted from the back of the electronics wafer through Inter-Chip-Vias. The compatibility of the Solid-Liquid InterDiffusion process with the silicon sensor functionality has already been demonstrated by measurements on two wafers hosting diodes with an active thickness of 50 μm

Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

International Nuclear Information System (INIS)

Libov, Vladyslav

2013-08-01

A measurement of charm and beauty production in Deep Inelastic Scattering at HERA is presented. The analysis is based on the data sample collected by the ZEUS detector in the period from 2003 to 2007 corresponding to an integrated luminosity of 354 pb -1 . The kinematic region of the measurement is given by 5 2 2 and 0.02 2 is the photon virtuality and y is the inelasticity. A lifetime technique is used to tag the production of charm and beauty quarks. Secondary vertices due to decays of charm and beauty hadrons are reconstructed, in association with jets. The jet kinematics is defined by E jet T >4.2(5) GeV for charm (beauty) and -1.6 jet jet T and η jet are the transverse energy and pseudorapidity of the jet, respectively. The significance of the decay length and the invariant mass of charged tracks associated with the secondary vertex are used as discriminating variables to distinguish between signal and background. Differential cross sections of jet production in charm and beauty events as a function of Q 2 , y, E jet T and η jet are measured. Results are compared to Next-to-Leading Order (NLO) predictions from Quantum Chromodynamics (QCD) in the fixed flavour number scheme. Good agreement between data and theory is observed. Contributions of the charm and beauty production to the inclusive proton structure function, F cbar c 2 and F b anti b 2 , are determined by extrapolating the double differential cross sections using NLO QCD predictions. Contributions to the test beam program for the Insertable B-Layer upgrade project of the ATLAS pixel detector are discussed. The test beam data analysis software package EUTelescope was extended, which allowed an efficient analysis of ATLAS pixel sensors. The USBPix DAQ system was integrated into the EUDET telescope allowing test beam measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS Inner Detector

OpenAIRE

Poley, Luise; Bloch, Ingo; Edwards, Sam; Friedrich, Conrad; Gregor, Ingrid-Maria; Jones, Tim; Lacker, Heiko; Pyatt, Simon; Rehnisch, Laura; Sperlich, Dennis; Wilson, John

2015-01-01

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive between readout chips and circuit board is a silver epoxy gl...

Design studies on sensors for the ATLAS Pixel Detector

CERN Document Server

Hügging, F G

2002-01-01

For the ATLAS Pixel Detector, prototype sensors have been successfully developed. For the sensors design, attention was given to survivability of the harsh LHC radiation environment leading to the need to operate them at several hundreds of volts, while maintaining a good charge collection efficiency, small cell size and minimal multiple scattering. For a cost effective mass production, a bias grid is implemented to test the sensors before assembly under full bias. (6 refs).

arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

CERN Document Server

Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

2018-02-02

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

ATLAS Phase-II upgrade pixel data transmission development

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00111400; The ATLAS collaboration

2017-01-01

The current tracking system of the ATLAS experiment will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics indicates that the planned trigger rate of 1 MHz will require readout speeds up to 5.12 Gb/s per data link. The high-radiation environment precludes optical data transmission, so the first part of the data transmission has to be implemented electrically, over a 6-m distance between the pixel modules and the optical transceivers. Several high-speed electrical data transmission solutions involving small-gauge wire cables or flexible circuits have been prototyped and characterized. A combination of carefully-selected physical layers and aggressive signal conditioning are required to achieve the proposed specifications.

First results of a Double-SOI pixel chip for X-ray imaging

Energy Technology Data Exchange (ETDEWEB)

Lu, Yunpeng, E-mail: yplu@ihep.ac.cn [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Ouyang, Qun [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Arai, Yasuo [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801 (Japan); Liu, Yi; Wu, Zhigang; Zhou, Yang [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China)

2016-09-21

Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I–V curve. An s-curve fitting resulted in a sigma of 153 e{sup −} among which equivalent noise charge (ENC) contributed 113 e{sup −}. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

Serial powering of pixel modules

International Nuclear Information System (INIS)

Stockmanns, Tobias; Fischer, Peter; Huegging, Fabian; Peric, Ivan; Runolfsson, O.; Wermes, Norbert

2003-01-01

Modern pixel detectors for the next generation of high-energy collider experiments like LHC use readout electronics in deep sub-micron technology. Chips in this technology need a low supply voltage of 2-2.5 V alongside high current consumption to achieve the desired performance. The high supply current leads to significant voltage drops in the long and low mass supply cables so that voltage fluctuations at the chips are induced, when the supply current changes. This problem scales with the number of modules when connected in parallel to the power supplies. An alternative powering scheme connects several modules in series resulting in a higher supply voltage but a lower current consumption of the chain and therefore a much lower voltage drop in the cables. In addition the amount of cables needed to supply the detector is vastly reduced. The concept and features of serial powering are presented and studies of the implementation of this technology as an alternative for the ATLAS pixel detector are shown. In particular, it is shown that the potential risk of powering in series can be addressed and eliminated

The Phase II ATLAS ITk Pixel Upgrade

CERN Document Server

Terzo, Stefano; The ATLAS collaboration

2017-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the "ITk" (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and and ring-shaped supports in the endcap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m$^2$ , depending on the final layout choice, which is expected to take place in early 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel-endcap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as $|\\eta| < 4$. Supporting structures will be ...

The Phase-2 ATLAS ITk Pixel Upgrade

CERN Document Server

Flick, Tobias; The ATLAS collaboration

2016-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

The Phase-II ATLAS ITk Pixel Upgrade

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00349918; The ATLAS collaboration

2017-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase~2 shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 $\\mathrm{m^2}$ of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| $<4$. Supporting structures will be based on low mass, highly stabl...

Pixel detector modules using MCM-D technology

CERN Document Server

Grah, C

2001-01-01

For the upcoming ATLAS-experiment at CERN it is planned to build a large area pixel detector, providing more than 100*10/sup 6/ sensor cells. For the innermost layer, the B-physics layer, it is planned to use MCM-D technology to perform the signal interconnections and power distribution on the modules. Focus of this paper is to give an introduction to this technology and present measurements on single chip MCM-D assemblies and a full scale MCM-D module prototype. (10 refs).

Study of FPGA and GPU based pixel calibration for ATLAS IBL

CERN Document Server

Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

2010-01-01

The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

Performance of active edge pixel sensors

Science.gov (United States)

Bomben, M.; Ducourthial, A.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Calderini, G.; D'Eramo, L.; Giacomini, G.; Marchiori, G.; Zorzi, N.; Rummler, A.; Weingarten, J.

2017-05-01

To cope with the High Luminosity LHC harsh conditions, the ATLAS inner tracker has to be upgraded to meet requirements in terms of radiation hardness, pile up and geometrical acceptance. The active edge technology allows to reduce the insensitive area at the border of the sensor thanks to an ion etched trench which avoids the crystal damage produced by the standard mechanical dicing process. Thin planar n-on-p pixel sensors with active edge have been designed and produced by LPNHE and FBK foundry. Two detector module prototypes, consisting of pixel sensors connected to FE-I4B readout chips, have been tested with beams at CERN and DESY. In this paper the performance of these modules are reported. In particular the lateral extension of the detection volume, beyond the pixel region, is investigated and the results show high hit efficiency also at the detector edge, even in presence of guard rings.

Characterization of proton irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

CERN Document Server

La Rosa, A; Cobal, M; Betta, G -F Dalla; Da Via, C; Darbo, G; Gallrapp, C; Gemme, C; Huegging, F; Janssen, J; Micelli, A; Pernegger, H; Povoli, M; Wermes, N; Zorzi, N

2012-01-01

In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 x 10**15 neq/cm2, while requiring bias voltages in the order of 100 V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

Towards a new generation of pixel detector readout chips

CERN Document Server

Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

2016-01-01

The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

Angular resolution of the gaseous micro-pixel detector Gossip

Science.gov (United States)

Bilevych, Y.; Blanco Carballo, V.; van Dijk, M.; Fransen, M.; van der Graaf, H.; Hartjes, F.; Hessey, N.; Koppert, W.; Nauta, S.; Rogers, M.; Romaniouk, A.; Veenhof, R.

2011-06-01

Gossip is a gaseous micro-pixel detector with a very thin drift gap intended for a high rate environment like at the pixel layers of ATLAS at the sLHC. The detector outputs not only the crossing point of a traversing MIP, but also the angle of the track, thus greatly simplifying track reconstruction. In this paper we describe a testbeam experiment to examine the angular resolution of the reconstructed track segments in Gossip. We used here the low diffusion gas mixture DME/CO 2 50/50. An angular resolution of 20 mrad for perpendicular tracks could be obtained from a 1.5 mm thin drift volume. However, for the prototype detector used at the testbeam experiment, the resolution of slanting tracks was worsened by poor time resolution of the pixel chip used.

Angular resolution of the gaseous micro-pixel detector Gossip

Energy Technology Data Exchange (ETDEWEB)

Bilevych, Y.; Blanco Carballo, V.; Dijk, M. van; Fransen, M.; Graaf, H. van der; Hartjes, F.; Hessey, N.; Koppert, W.; Nauta, S. [Nikhef, P.O. Box 41882, 1009 DB Amsterdam (Netherlands); Rogers, M. [Radboud University, P.O. Box 9102, 6500HC Nijmegen (Netherlands); Romaniouk, A.; Veenhof, R. [CERN, CH-1211, Geneve 23 (Switzerland)

2011-06-15

Gossip is a gaseous micro-pixel detector with a very thin drift gap intended for a high rate environment like at the pixel layers of ATLAS at the sLHC. The detector outputs not only the crossing point of a traversing MIP, but also the angle of the track, thus greatly simplifying track reconstruction. In this paper we describe a testbeam experiment to examine the angular resolution of the reconstructed track segments in Gossip. We used here the low diffusion gas mixture DME/CO{sub 2} 50/50. An angular resolution of 20 mrad for perpendicular tracks could be obtained from a 1.5 mm thin drift volume. However, for the prototype detector used at the testbeam experiment, the resolution of slanting tracks was worsened by poor time resolution of the pixel chip used.

Angular resolution of the gaseous micro-pixel detector Gossip

International Nuclear Information System (INIS)

Bilevych, Y.; Blanco Carballo, V.; Dijk, M. van; Fransen, M.; Graaf, H. van der; Hartjes, F.; Hessey, N.; Koppert, W.; Nauta, S.; Rogers, M.; Romaniouk, A.; Veenhof, R.

2011-01-01

Gossip is a gaseous micro-pixel detector with a very thin drift gap intended for a high rate environment like at the pixel layers of ATLAS at the sLHC. The detector outputs not only the crossing point of a traversing MIP, but also the angle of the track, thus greatly simplifying track reconstruction. In this paper we describe a testbeam experiment to examine the angular resolution of the reconstructed track segments in Gossip. We used here the low diffusion gas mixture DME/CO 2 50/50. An angular resolution of 20 mrad for perpendicular tracks could be obtained from a 1.5 mm thin drift volume. However, for the prototype detector used at the testbeam experiment, the resolution of slanting tracks was worsened by poor time resolution of the pixel chip used.

Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

Energy Technology Data Exchange (ETDEWEB)

Gallrapp, Christian

2015-07-01

The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

International Nuclear Information System (INIS)

Gallrapp, Christian

2015-01-01

The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

Development of active edge pixel sensors and four-side buttable modules using vertical integration technologies

CERN Document Server

INSPIRE-00219560; Moser, H.-G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

2014-01-01

We present an R&D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 $\\mu$m thick, produced at VTT (Finland) with an active edge technology, which considerably reduces the dead area at the periphery of the device. The sensors are interconnected with solder bump-bonding to the ATLAS FE-I3 and FE-I4 read-out chips, and characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements will be discussed for devices before and after irradiation up to a fluence of $5\\times 10^{15}$ \

Monitoring the Radiation Damage of the ATLAS Pixel Detector

CERN Document Server

Cooke, M; The ATLAS collaboration

2012-01-01

The Pixel Detector is the innermost charged particle tracking component employed by the ATLAS experiment at the CERN Large Hadron Collider (LHC). The instantaneous luminosity delivered by the LHC, now routinely in excess of 5x10^{33} cm^{-2} s^{-1}, results in a rapidly increasing accumulated radiation dose to the detector. Methods based on the sensor depletion properties and leakage current are used to monitor the evolution of the radiation damage, and results from the 2011 run are presented.

Monitoring the radiation damage of the ATLAS pixel detector

International Nuclear Information System (INIS)

Cooke, M.

2013-01-01

The pixel detector is the innermost charged particle tracking component employed by the ATLAS experiment at the CERN Large Hadron Collider (LHC). The instantaneous luminosity delivered by the LHC, now routinely in excess of 5×10 33 cm −2 s −1 , results in a rapidly increasing accumulated radiation dose to the detector. Methods based on the sensor depletion properties and leakage current are used to monitor the evolution of the radiation damage, and results from the 2011 run are presented

The phase-II ATLAS pixel tracker upgrade: layout and mechanics.

CERN Document Server

Sharma, Abhishek; The ATLAS collaboration

2016-01-01

The ATLAS experiment will upgrade its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The upgraded tracker will consist of silicon-strip modules surrounding a pixel detector, and will likely cover an extended eta range, perhaps as far as |eta|<4.0. A number of layout and supporting-structure options are being considered for the pixel detector, with the final choice expected to be made in early 2017. The proposed supporting structures are based on lightweight, highly-thermally-conductive carbon-based materials and are cooled by evaporative carbon dioxide. The various layouts will be described and a description of the supporting structures will be presented, along with results from testing of prototypes.

Laser Soldering and Thermal Cycling Tests of Monolithic Silicon Pixel Chips

CERN Document Server

Strand, Frode Sneve

2015-01-01

An ALPIDE-1 monolithic silicon pixel sensor prototype has been laser soldered to a flex printed circuit using a novel interconnection technique using lasers. This technique is to be optimised to ensure stable, good quality connections between the sensor chips and the FPCs. To test the long-term stability of the connections, as well as study the effects on hit thresholds and noise in the sensor, it was thermally cycled in a climate chamber 1200 times. The soldered connections showed good qualities like even melting and good adhesion on pad/flex surfaces, and the chip remained in working condition for 1080 cycles. After this, a few connections failed, having cracks in the soldering tin, rendering the chip unusable. Threshold and noise characteristics seemed stable, except for the noise levels of sector 2 in the chip, for 1000 cycles in a temperature interval of "10^{\\circ}" and "50^{\\circ}" C. Still, further testing with wider temperature ranges and more cycles is needed to test the limitations of the chi...

Characterization of proton irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

Energy Technology Data Exchange (ETDEWEB)

La Rosa, A., E-mail: alessandro.larosa@cern.ch [CERN, Geneva 23, CH-1211 (Switzerland); Boscardin, M. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Cobal, M. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Dalla Betta, G.-F. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Da Via, C. [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom); Darbo, G. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Gallrapp, C. [CERN, Geneva 23, CH-1211 (Switzerland); Gemme, C. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Huegging, F.; Janssen, J. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Micelli, A. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Pernegger, H. [CERN, Geneva 23, CH-1211 (Switzerland); Povoli, M. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Wermes, N. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Zorzi, N. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

2012-07-21

In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non-optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 Multiplication-Sign 10{sup 15}n{sub eq}cm{sup -2}, while requiring bias voltages in the order of 100 V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Libov, Vladyslav

2013-08-15

measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS Inner Detector

CERN Document Server

INSPIRE-00407830; Bloch, Ingo; Edwards, Sam; Friedrich, Conrad; Gregor, Ingrid M.; Jones, T; Lacker, Heiko; Pyatt, Simon; Rehnisch, Laura; Sperlich, Dennis; Wilson, John

2016-05-24

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). This glue has several disadvantages, which motivated the search for an alternative. This paper presents a study concerning the use of six ultra-violet (UV) cure glues and a glue pad for use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, the thermal conduction and shear strength, thermal cycling, radiation hardness, corrosion resistance and shear strength tests. These investigatio...

Robustness of the ATLAS pixel clustering neural network algorithm

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

2016-01-01

Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. The algorithms depend heavily on accurate estimation of the position of particles as they traverse the inner detector elements. An artificial neural network algorithm is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The method recovers otherwise lost tracks in dense environments where particles are separated by distances comparable to the size of the detector read-out elements. Such environments are highly relevant for LHC run 2, e.g. in searches for heavy resonances. Within the scope of run 2 track reconstruction performance and upgrades, the robustness of the neural network algorithm will be presented. The robustness has been studied by evaluating the stability of the algorithm’s performance under a range of variations in the pixel detector conditions.

An Associative Memory Chip for the Trigger System of the ATLAS Experiment

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00380893; The ATLAS collaboration; Liberali, Valentino; Crescioli, Francesco; Beretta, Matteo; Frontini, Luca; Annovi, Alberto; Stabile, Alberto

2017-01-01

The AM06 is the 6th version of a large associative memory chip designed in 65 nm CMOS tech- nology. The AM06 operates as a highly parallel ASIC processor for pattern recognition in the ATLAS experiment at CERN. It is the core of the Fast TracKer electronic system, which is tai- lored for on-line track finding in the trigger system of the ATLAS experiment. The Fast TracKer system is able to process events up to 100 MHz in real time. The AM06 is a complex chip, and it has been designed combining full-custom memory arrays, standard logic cells and IP blocks. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called a pattern. The chip silicon area is 168 mm2; it contains 421 millions of transistors and it stores 217 patterns. Moreover, the associative memory is suitable also for other interdisciplinary appli- cations (i.e., general purpose image filtering and analysis). In the near future we plan to design a more powerful and flexible chip in 28 nm CMOS technology.

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3

International Nuclear Information System (INIS)

Loecker, M.

2007-04-01

Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 μm 2 pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e - ). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed

TID-dependent current measurements of IBL readout chips

Energy Technology Data Exchange (ETDEWEB)

Dette, Karola [TU Dortmund, Experimentelle Physik IV (Germany); CERN (Switzerland); Collaboration: ATLAS Pixel-Collaboration

2016-07-01

The ATLAS detector consists of several subsystems with a hybrid pixel detector as the innermost component of the tracking system. The pixel detector has been composed of three layers of silicon sensor assemblies during the first data taking run of the LHC and has been upgraded with a new 4th layer, the so-called Insertable B-Layer (IBL), in summer 2014. Each silicon sensor of the IBL is connected to a Front End readout chip (FE-I4) via bump bonds. During the first year of data taking an increase of the LV current produced by the readout chips was observed. This increase could be traced back to radiation damage inside the silicon. The dependence of the current on the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations and will be presented in this talk.

The ATLAS Inner Detector operation,data quality and tracking performance.

CERN Document Server

Stanecka, E; The ATLAS collaboration

2012-01-01

The ATLAS Inner Detector comprises silicon and gas based detectors. The Semi-Conductor Tracker (SCT) and the Pixel Detector are the key precision tracking silicon devices in the Inner Detector of the ATLAS experiment at CERN LHC. And the the Transition Radiation Tracker (TRT), the outermost of the three subsystems of the ATLAS Inner Detector is made of thin-walled proportional-mode drift tubes (straws). The Pixel Detector consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The SCT is a silicon strip detector and is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. The TRT is made...

New Technique for Luminosity Measurement Using 3D Pixel Modules in the ATLAS IBL Detector

CERN Document Server

Liu, Peilian; The ATLAS collaboration

2017-01-01

The Insertable b-Layer ( IBL ) is the innermost layer of the ATLAS tracking system. It consists of planar pixel modules in the central region and 3D modules at two extremities. We use the cluster length distributions in 3D sensor modules of the IBL to determine the number of primary charged particles per event and suppress backgrounds. This Pixel Cluster Counting ( PCC ) algorithm provides a bunch-by-bunch luminosity measurement. An accurate luminosity measurement is a key component for precision measurements at the Large Hadron Collider and one of the largest uncertainties on the luminosity determination in ATLAS arises from the long-term stability of the measurement technique. The comparison of the PCC algorithm with other existing algorithms provides key insights in assessing and reducing such uncertainty.

System test and noise performance studies at the ATLAS pixel detector

International Nuclear Information System (INIS)

Weingarten, J.

2007-09-01

The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

System test and noise performance studies at the ATLAS pixel detector

Energy Technology Data Exchange (ETDEWEB)

Weingarten, J.

2007-09-15

The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

Development of a Micro Pixel Chamber for the ATLAS Upgrade

CERN Document Server

Ochi, Atsuhiko; Komai, Hidetoshi; Edo, Yuki; Yamaguchi, Takahiro

2012-01-01

The Micro Pixel Chamber (μ-PIC) is being developed a sacandidate for the muon system of the ATLAS detector for upgrading in LHC experiments. The μ-PIC is a micro-pattern gaseous detector that doesn’t have floating structure such as wires, mesh, or foil. This detector can be made by printed-circuit-board (PCB) technology, which is commercially available and suited for mass production. Operation tests have been performed under high flux neutrons under similar conditions to the ATLAS cavern. Spark rates are measured using several gas mixtures under 7 MeV neutron irradiation, and good properties were observed using neon, ethane, and CF4 mixture of gases.Using resistive materials as electrodes, we are also developing a new μ-PIC, which is not expected to damage the electrodes in the case of discharge sparks.

Optical readout in a multi-module system test for the ATLAS pixel detector

International Nuclear Information System (INIS)

Flick, Tobias; Becks, Karl-Heinz; Gerlach, Peter; Kersten, Susanne; Maettig, Peter; Nderitu Kirichu, Simon; Reeves, Kendall; Richter, Jennifer; Schultes, Joachim

2006-01-01

The innermost part of the ATLAS experiment at the LHC, CERN, will be a pixel detector, which is presently under construction. The command messages and the readout data of the detector are transmitted over an optical data path. The readout chain consists of many components which are produced at several locations around the world, and must work together in the pixel detector. To verify that these parts are working together as expected a system test has been built up. It consists of detector modules, optoboards, optical fibres, Back of Crate cards, Readout Drivers, and control computers. In this paper, the system test setup and the operation of the readout chain are described. Also, some results of tests using the final pixel detector readout chain are given

Quality Assurance and Functionality Tests on Electrical Components during the ATLAS IBL Production

CERN Document Server

Jentzsch, J

2013-01-01

To improve performance of the ATLAS inner tracker, a fourth Pixel layer, called the Insertable B-layer (IBL), will be installed in 2014 on a new beam pipe. A new read out chip generation, FE-I4, has been developed and two different sensor designs, a rather conventional planar and a 3D design, have been flip chipped to these front ends. New staves holding new stave and module flex circuits have been developed as well. Therefore, a production QA test bench has been established to test all production staves before integration with the new beam pipe. This setup combines former ATLAS Pixel services and a new readout system, namely the RCE (Reconfigurable Cluster Element) system developed at SLAC. With this setup all production staves will be tested to ensure the installation of only those staves which fulfill the IBL criteria. Quality assurance measurements under cleanroom conditions, including temperature and humidity control, are performed on the individual components during the various production steps of the I...

The Layer 1 / Layer 2 readout upgrade for the ATLAS Pixel Detector

CERN Document Server

Mullier, Geoffrey; The ATLAS collaboration

2016-01-01

The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC). The increase of instantaneous luminosity foreseen during the LHC Run 2, will lead to an increased detector occupancy that is expected to saturate the readout links of the outermost layers of the pixel detector: Layers 1 and 2. To ensure a smooth data taking under such conditions, the read out system of the recently installed fourth innermost pixel layer, the Insertable B-Layer, was modified to accomodate the needs of the older detector. The Layer 2 upgrade installation took place during the 2015 winter shutdown, with the Layer 1 installation scheduled for 2016. A report of the successful installation, together with the design of novel dedicated optical to electrical converters and the software and firmware updates will be presented.

Production and characterisation of SLID interconnected n-in-p pixel modules with 75 μm thin silicon sensors

Energy Technology Data Exchange (ETDEWEB)

Andricek, L. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Beimforde, M.; Macchiolo, A.; Moser, H.-G. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Nisius, R., E-mail: Richard.Nisius@mpp.mpg.de [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany); Richter, R.H. [Halbleiterlabor der Max-Planck-Gesellschaft, Otto Hahn Ring 6, D-81739 München (Germany); Terzo, S.; Weigell, P. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut), Föhringer Ring 6, D-80805 München (Germany)

2014-09-11

The performance of pixel modules built from 75 μm thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 μm thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of 10{sup 16}n{sub eq}/cm{sup 2}.

Performance and operation experience of the Atlas Semiconductor Tracker and Pixel Detector at the LHC.

CERN Document Server

Stanecka, E; The ATLAS collaboration

2013-01-01

After more than 3 years of successful operation at the LHC, we report on the operation and performance of the ATLAS Pixel Detector and Semi-Conductor Tracker (SCT) functioning in a high luminosity, high radiation environment.

Overview of the ATLAS Insertable B-Layer (IBL) Project

International Nuclear Information System (INIS)

Røhne, O.

2013-01-01

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade for the Pixel Detector is the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine, in 2013–2014. The new detector, called the Insertable B-Layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe at a radius of 3.3 cm. The IBL has required the development of several new technologies to cope with increased radiation and pixel occupancy and also to improve the physics performance through reduction of the pixel size and a more stringent material budget. The IBL presents several changes to the design of the present ATLAS Pixel Detector: two different and promising silicon sensor technologies, planar n-in-n and 3D, will be used for the IBL. A new read-out chip FE-I4 has been designed in 130 nm technology, the material budget is minimized by using new lightweight mechanical support materials and a CO 2 based cooling system has been developed. An overview of the IBL project, of the module design and the qualification for these sensor technologies with particular emphasis on irradiation and beam tests will be presented

Study of planar pixel sensors hardener to radiations for the upgrade of the ATLAS vertex detector

International Nuclear Information System (INIS)

Benoit, M.

2011-05-01

In this work, we present a study, using TCAD (Technology Computer-Assisted Design) simulation, of the possible methods of designing planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure, a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain the high charge collection observed in highly irradiated devices. A simple planar pixel sensor digitization model to be used in test beam and full detector system is detailed. It allows for easy comparison between experimental data and prediction by the various radiation damage models available. The digitizer has been validated using test beam data for unirradiated sensors and can be used to produce the first full scale simulation of the ATLAS detector with the IBL that include sensor effects such as slim edge and thinning of the sensor. (author)

Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

Science.gov (United States)

Benoit, M.; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Perić, I.; Rimoldi, M.; Ristić, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

2018-02-01

HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the 4th generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between 1× 1014 and 5× 1015 1-MeV- neq. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of 85 V. The sample irradiated to a fluence of 1× 1015 neq—a relevant value for a large volume of the upgraded tracker—exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.

Operational Experience and Performance with the ATLAS Pixel Detector at the Large Hadron Collider

CERN Document Server

Grummer, Aidan; The ATLAS collaboration

2018-01-01

The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 2 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency will be described, with special emphasis to radiation damage experience. In particular, radiation damage effects will be showed and signs of degradation which are visible but which are not impacting yet the tracking performance (but will): dE/dX, occupancy reduction with integrated luminosity, under-depletion effects with IBL in 2016, effects of annealing that is not insignificant for the inner-most layers. Therefore the offline software strat...

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Bomben, M., E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Bagolini, A.; Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, L. [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, Pisa (Italy); INFN Sez. di Pisa, Pisa (Italy); Chauveau, J. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

2013-12-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

International Nuclear Information System (INIS)

Bomben, M.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

2013-01-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

CERN Document Server

Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

2006-01-01

We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

The Upgraded Pixel Detector of the ATLAS Experiment for Run-2 at the LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00084948; The ATLAS collaboration

2016-01-01

Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130 nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented using collision data.

Mesure des champs de radiation dans le detecteur ATLAS et sa caverne avec les detecteurs au silicium a pixels ATLAS-MPX

Science.gov (United States)

Bouchami, Jihene

The LHC proton-proton collisions create a hard radiation environment in the ATLAS detector. In order to quantify the effects of this environment on the detector performance and human safety, several Monte Carlo simulations have been performed. However, direct measurement is indispensable to monitor radiation levels in ATLAS and also to verify the simulation predictions. For this purpose, sixteen ATLAS-MPX devices have been installed at various positions in the ATLAS experimental and technical areas. They are composed of a pixelated silicon detector called MPX whose active surface is partially covered with converter layers for the detection of thermal, slow and fast neutrons. The ATLAS-MPX devices perform real-time measurement of radiation fields by recording the detected particle tracks as raster images. The analysis of the acquired images allows the identification of the detected particle types by the shapes of their tracks. For this aim, a pattern recognition software called MAFalda has been conceived. Since the tracks of strongly ionizing particles are influenced by charge sharing between adjacent pixels, a semi-empirical model describing this effect has been developed. Using this model, the energy of strongly ionizing particles can be estimated from the size of their tracks. The converter layers covering each ATLAS-MPX device form six different regions. The efficiency of each region to detect thermal, slow and fast neutrons has been determined by calibration measurements with known sources. The study of the ATLAS-MPX devices response to the radiation produced by proton-proton collisions at a center of mass energy of 7 TeV has demonstrated that the number of recorded tracks is proportional to the LHC luminosity. This result allows the ATLAS-MPX devices to be employed as luminosity monitors. To perform an absolute luminosity measurement and calibration with these devices, the van der Meer method based on the LHC beam parameters has been proposed. Since the ATLAS

Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

CERN Document Server

La Rosa, Alessandro; The ATLAS collaboration

2016-01-01

The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

Commissioning of the Atlas pixel detector and search of the Higgs boson in the tt-H, H → bb- channel with the Atlas experiment at the LHC

International Nuclear Information System (INIS)

Aad, G.

2009-09-01

The global fit of Higgs boson quantum contributions to the electroweak experimental observables, computed within the Standard Model, favors a light Higgs boson with a mass of m H = 90 -27 +36 GeV, on the edge of the 95% Confidence Level region excluded by LEP. Finding a light Higgs boson at LHC is experimentally difficult and several channels with various signatures will be sought for. The associated production of the Higgs boson with a pair of top quarks, with the subsequent decay of the Higgs boson into b-quark pairs (dominant for m H <135 GeV), is one of the channels considered. This channel opens the possibility of measuring the top and b-quark Yukawa couplings. The potential of the ATLAS detector to observe this channel is described. Several ingredients are crucial: the reconstruction of the top-anti-top system with a high-purity, excellent b-tagging capabilities and good knowledge of the tt-bar+jets background. The pixel detector is the most important ATLAS sub-detectors for tagging b -jets. The ATLAS detector was commissioned with cosmic muon rays in autumn 2008. The pixel detector dead channels, calibration constants and slow control informations are described for this period. A detailed study about pixel noise determination and suppression is presented. Finally, the pixel detection efficiency is measured using cosmic muon rays. (author)

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

International Nuclear Information System (INIS)

Snoeys, W.; Burns, M.; Campbell, M.; Cantatore, E.; Cencelli, V.; Dinapoli, R.; Heijne, E.; Jarron, P.; Lamanna, P.; Minervini, D.; Morel, M.; O'Shea, V.; Quiquempoix, V.; Bello, D.S.S.D.San Segundo; Van Koningsveld, B.; Wyllie, K.

2001-01-01

The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μmx425 μm pixel cells in the 256x32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32x32 array of 400 μmx425 μm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology

Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

CERN Document Server

Poikela, Tuomas; Paakkulainen, J

2010-01-01

The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

Diamond and silicon pixel detectors in high radiation environments

Energy Technology Data Exchange (ETDEWEB)

Tsung, Jieh-Wen

2012-10-15

Diamond pixel detector is a promising candidate for tracking of collider experiments because of the good radiation tolerance of diamond. The diamond pixel detector must withstand the radiation damage from 10{sup 16} particles per cm{sup 2}, which is the expected total fluence in High Luminosity Large Hadron Collider. The performance of diamond and silicon pixel detectors are evaluated in this research in terms of the signal-to-noise ratio (SNR). Single-crystal diamond pixel detectors with the most recent readout chip ATLAS FE-I4 are produced and characterized. Based on the results of the measurement, the SNR of diamond pixel detector is evaluated as a function of radiation fluence, and compared to that of planar-silicon ones. The deterioration of signal due to radiation damage is formulated using the mean free path of charge carriers in the sensor. The noise from the pixel readout circuit is simulated and calculated with leakage current and input capacitance to the amplifier as important parameters. The measured SNR shows good agreement with the calculated and simulated results, proving that the performance of diamond pixel detectors can exceed the silicon ones if the particle fluence is more than 10{sup 15} particles per cm{sup 2}.

Diamond and silicon pixel detectors in high radiation environments

International Nuclear Information System (INIS)

Tsung, Jieh-Wen

2012-10-01

Diamond pixel detector is a promising candidate for tracking of collider experiments because of the good radiation tolerance of diamond. The diamond pixel detector must withstand the radiation damage from 10 16 particles per cm 2 , which is the expected total fluence in High Luminosity Large Hadron Collider. The performance of diamond and silicon pixel detectors are evaluated in this research in terms of the signal-to-noise ratio (SNR). Single-crystal diamond pixel detectors with the most recent readout chip ATLAS FE-I4 are produced and characterized. Based on the results of the measurement, the SNR of diamond pixel detector is evaluated as a function of radiation fluence, and compared to that of planar-silicon ones. The deterioration of signal due to radiation damage is formulated using the mean free path of charge carriers in the sensor. The noise from the pixel readout circuit is simulated and calculated with leakage current and input capacitance to the amplifier as important parameters. The measured SNR shows good agreement with the calculated and simulated results, proving that the performance of diamond pixel detectors can exceed the silicon ones if the particle fluence is more than 10 15 particles per cm 2 .

The ALICE Silicon Pixel Detector System (SPD)

CERN Document Server

Kluge, A; Antinori, Federico; Burns, M; Cali, I A; Campbell, M; Caselle, M; Ceresa, S; Dima, R; Elias, D; Fabris, D; Krivda, Marian; Librizzi, F; Manzari, Vito; Morel, M; Moretto, Sandra; Osmic, F; Pappalardo, G S; Pepato, Adriano; Pulvirenti, A; Riedler, P; Riggi, F; Santoro, R; Stefanini, G; Torcato De Matos, C; Turrisi, R; Tydesjo, H; Viesti, G; PH-EP

2007-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 detector modules (half-staves) each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8192 active cells, so that the total number of pixel cells in the SPD is ≈ 107. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget and detector module dimensions are very demanding.

The INFN R\\&D: new pixel detector for the High Luminosity Upgrade of the LHC

CERN Document Server

Dinardo, Mauro

2017-01-01

The High Luminosity upgrade of the CERN-LHC (HL-LHC) demands for a new high-radiation tolerant solid-state pixel sensor capable of surviving fluencies up to a few $10^{16}$~ particles/cm$^2$ at $\\sim$3~cm from the interaction point. To this extent the INFN ATLAS-CMS joint research activity, in collaboration with Fondazione Bruno Kessler-FBK, is aiming at the development of thin n-in-p type pixel sensors for the HL-LHC. The R\\&D covers both planar and single-sided 3D columnar pixel devices made with the Si-Si Direct Wafer Bonding technique, which allows for the production of sensors with 100~$\\mu {\\rm m}$ and 130~$\\mu {\\rm m}$ active thickness for planar sensors, and 130~$\\mu {\\rm m}$ for 3D sensors, the thinnest ones ever produced so far. First prototypes of hybrid modules bump-bonded to the present CMS and ATLAS readout chips have been tested in beam tests. Preliminary results on their performance before and after irradiation are presented.

Thin and edgeless sensors for ATLAS pixel detector upgrade

Science.gov (United States)

Ducourthial, A.; Bomben, M.; Calderini, G.; Marchiori, G.; D'Eramo, L.; Luise, I.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Darbo, G.; Dalla Betta, G.-F.; Giacomini, G.; Meschini, M.; Messineo, A.; Ronchin, S.; Zorzi, N.

2017-12-01

To cope with the harsh environment foreseen at the high luminosity conditions of HL-LHC, the ATLAS pixel detector has to be upgraded to be fully efficient with a good granularity, a maximized geometrical acceptance and an high read out rate. LPNHE, FBK and INFN are involved in the development of thin and edgeless planar pixel sensors in which the insensitive area at the border of the sensor is minimized thanks to the active edge technology. In this paper we report on two productions, a first one consisting of 200 μm thick n-on-p sensors with active edge, a second one composed of 100 and 130 μm thick n-on-p sensors. Those sensors have been tested on beam, both at CERN-SPS and at DESY. In terms of hit-efficiency, the first production reaches 99 % before irradiation and the second one reaches 96.3% after a fluence in excess of 1× 1016neq/cm2. The performances of those two productions before and after irradiation will be presented in details.

Robustness of the Artificial Neural Networks Used for Clustering in the ATLAS Pixel Detector

CERN Document Server

The ATLAS collaboration

2015-01-01

A study of the robustness of the ATLAS pixel neural network clustering algorithm is presented. The sensitivity to variations to its input is evaluated. These variations are motivated by potential discrepancies between data and simulation due to uncertainties in the modelling of pixel clusters in simulation, as well as uncertainties from the detector calibration. Within reasonable variation magnitudes, the neural networks prove to be robust to most variations. The neural network used to identify pixel clusters created by multiple charged particles, is most sensitive to variations affecting the total amount of charge collected in the cluster. Modifying the read-out threshold has the biggest effect on the clustering's ability to estimate the position of the particle's intersection with the detector.

Implementation and performance of the ATLAS pixel clustering neural networks

CERN Document Server

Gagnon, Louis-Guillaume; The ATLAS collaboration

2018-01-01

The high particle densities produced by the Large Hadron Collider (LHC) mean that in the ATLAS pixel detector the clusters of deposited charge start to merge. A neural network-based approach is used to estimate the number of particles contributing to each cluster, and to accurately estimate the hit positions even in the presence of multiple particles. This talk thoroughly describes the algorithm and its implementation as well as present a set of benchmark performance measurements. The problem is most acute in the core of high-momentum jets where the average separation between particles becomes comparable to the detector granularity. This is further complicated by the high number of interactions per bunch crossing. Both these issues will become worse as the Run 3 and HL-LHC programme require analysis of higher and higher pT jets, while the interaction multiplicity rises. Future prospects in the context of LHC Run 3 and the upcoming ATLAS inner detector upgrade are also discussed.

Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

CERN Document Server

Beimforde, Michael

To extend the discovery potential of the experiments at the LHC accelerator a luminosity upgrade towards the super LHC (sLHC) with an up to ten-fold peak luminosity is planned. Within this thesis a new module concept was developed and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

International Nuclear Information System (INIS)

Trimpl, M.

2005-12-01

The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Trimpl, M.

2005-12-15

The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

Radiation Damage Observations in the ATLAS Pixel Detector Using the High Voltage Delivery System

CERN Document Server

Toms, K

2011-01-01

We describe the implementation of radiation damage monitoring using leakage current measurement of the silicon pixel sensors provided by the circuits of the ATLAS Pixel Detector high voltage delivery (HVPP4) system. The dependence of the leakage current upon the integrated luminosity for several temperature scenarios is presented. Based on the analysis we have determined the sensitivity specifications for a Current Measurement System. The status of the system and the first measurement of the radiation damage corresponding to 2--4 fb$^{-1}$ of integrated luminosity are presented, as well as the comparison with the theoretical model.

Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

CERN Document Server

AUTHOR|(SzGeCERN)394193

2016-01-01

A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

CERN Document Server

Savic, Natascha

2016-01-01

In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023-2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more ra- diation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 {\\mu}m recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of th...

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

International Nuclear Information System (INIS)

Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

CERN Document Server

Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

2009-01-01

In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

A neural network clustering algorithm for the ATLAS silicon pixel detector

CERN Document Server

Aad, Georges; Abdallah, Jalal; Abdel Khalek, Samah; Abdinov, Ovsat; Aben, Rosemarie; Abi, Babak; Abolins, Maris; AbouZeid, Ossama; Abramowicz, Halina; Abreu, Henso; Abreu, Ricardo; Abulaiti, Yiming; Acharya, Bobby Samir; Adamczyk, Leszek; Adams, David; Adelman, Jahred; Adomeit, Stefanie; Adye, Tim; Agatonovic-Jovin, Tatjana; Aguilar-Saavedra, Juan Antonio; Agustoni, Marco; Ahlen, Steven; Ahmadov, Faig; Aielli, Giulio; Akerstedt, Henrik; Åkesson, Torsten Paul Ake; Akimoto, Ginga; Akimov, Andrei; Alberghi, Gian Luigi; Albert, Justin; Albrand, Solveig; Alconada Verzini, Maria Josefina; Aleksa, Martin; Aleksandrov, Igor; Alexa, Calin; Alexander, Gideon; Alexandre, Gauthier; Alexopoulos, Theodoros; Alhroob, Muhammad; Alimonti, Gianluca; Alio, Lion; Alison, John; Allbrooke, Benedict; Allison, Lee John; Allport, Phillip; Almond, John; Aloisio, Alberto; Alonso, Alejandro; Alonso, Francisco; Alpigiani, Cristiano; Altheimer, Andrew David; Alvarez Gonzalez, Barbara; Alviggi, Mariagrazia; Amako, Katsuya; Amaral Coutinho, Yara; Amelung, Christoph; Amidei, Dante; Amor Dos Santos, Susana Patricia; Amorim, Antonio; Amoroso, Simone; Amram, Nir; Amundsen, Glenn; Anastopoulos, Christos; Ancu, Lucian Stefan; Andari, Nansi; Andeen, Timothy; Anders, Christoph Falk; Anders, Gabriel; Anderson, Kelby; Andreazza, Attilio; Andrei, George Victor; Anduaga, Xabier; Angelidakis, Stylianos; Angelozzi, Ivan; Anger, Philipp; Angerami, Aaron; Anghinolfi, Francis; Anisenkov, Alexey; Anjos, Nuno; Annovi, Alberto; Antonaki, Ariadni; Antonelli, Mario; Antonov, Alexey; Antos, Jaroslav; Anulli, Fabio; Aoki, Masato; Aperio Bella, Ludovica; Apolle, Rudi; Arabidze, Giorgi; Aracena, Ignacio; Arai, Yasuo; Araque, Juan Pedro; Arce, Ayana; Arguin, Jean-Francois; Argyropoulos, Spyridon; Arik, Metin; Armbruster, Aaron James; Arnaez, Olivier; Arnal, Vanessa; Arnold, Hannah; Arratia, Miguel; Arslan, Ozan; Artamonov, Andrei; Artoni, Giacomo; Asai, Shoji; Asbah, Nedaa; Ashkenazi, Adi; Åsman, Barbro; Asquith, Lily; Assamagan, Ketevi; Astalos, Robert; Atkinson, Markus; Atlay, Naim Bora; Auerbach, Benjamin; Augsten, Kamil; Aurousseau, Mathieu; Avolio, Giuseppe; Azuelos, Georges; Azuma, Yuya; Baak, Max; Baas, Alessandra; Bacci, Cesare; Bachacou, Henri; Bachas, Konstantinos; Backes, Moritz; Backhaus, Malte; Backus Mayes, John; Badescu, Elisabeta; Bagiacchi, Paolo; Bagnaia, Paolo; Bai, Yu; Bain, Travis; Baines, John; Baker, Oliver Keith; Balek, Petr; Balli, Fabrice; Banas, Elzbieta; Banerjee, Swagato; Bannoura, Arwa A E; Bansal, Vikas; Bansil, Hardeep Singh; Barak, Liron; Baranov, Sergei; Barberio, Elisabetta Luigia; Barberis, Dario; Barbero, Marlon; Barillari, Teresa; Barisonzi, Marcello; Barklow, Timothy; Barlow, Nick; Barnett, Bruce; Barnett, Michael; Barnovska, Zuzana; Baroncelli, Antonio; Barone, Gaetano; Barr, Alan; Barreiro, Fernando; Barreiro Guimarães da Costa, João; Bartoldus, Rainer; Barton, Adam Edward; Bartos, Pavol; Bartsch, Valeria; Bassalat, Ahmed; Basye, Austin; Bates, Richard; Batkova, Lucia; Batley, Richard; Battaglia, Marco; Battistin, Michele; Bauer, Florian; Bawa, Harinder Singh; Beau, Tristan; Beauchemin, Pierre-Hugues; Beccherle, Roberto; Bechtle, Philip; Beck, Hans Peter; Becker, Anne Kathrin; Becker, Sebastian; Beckingham, Matthew; Becot, Cyril; Beddall, Andrew; Beddall, Ayda; Bedikian, Sourpouhi; Bednyakov, Vadim; Bee, Christopher; Beemster, Lars; Beermann, Thomas; Begel, Michael; Behr, Katharina; Belanger-Champagne, Camille; Bell, Paul; Bell, William; Bella, Gideon; Bellagamba, Lorenzo; Bellerive, Alain; Bellomo, Massimiliano; Belotskiy, Konstantin; Beltramello, Olga; Benary, Odette; Benchekroun, Driss; Bendtz, Katarina; Benekos, Nektarios; Benhammou, Yan; Benhar Noccioli, Eleonora; Benitez Garcia, Jorge-Armando; Benjamin, Douglas; Bensinger, James; Benslama, Kamal; Bentvelsen, Stan; Berge, David; Bergeaas Kuutmann, Elin; Berger, Nicolas; Berghaus, Frank; Beringer, Jürg; Bernard, Clare; Bernat, Pauline; Bernius, Catrin; Bernlochner, Florian Urs; Berry, Tracey; Berta, Peter; Bertella, Claudia; Bertoli, Gabriele; Bertolucci, Federico; Bertsche, David; Besana, Maria Ilaria; Besjes, Geert-Jan; Bessidskaia, Olga; Bessner, Martin Florian; Besson, Nathalie; Betancourt, Christopher; Bethke, Siegfried; Bhimji, Wahid; Bianchi, Riccardo-Maria; Bianchini, Louis; Bianco, Michele; Biebel, Otmar; Bieniek, Stephen Paul; Bierwagen, Katharina; Biesiada, Jed; Biglietti, Michela; Bilbao De Mendizabal, Javier; Bilokon, Halina; Bindi, Marcello; Binet, Sebastien; Bingul, Ahmet; Bini, Cesare; Black, Curtis; Black, James; Black, Kevin; Blackburn, Daniel; Blair, Robert; Blanchard, Jean-Baptiste; Blazek, Tomas; Bloch, Ingo; Blocker, Craig; Blum, Walter; Blumenschein, Ulrike; Bobbink, Gerjan; Bobrovnikov, Victor; Bocchetta, Simona Serena; Bocci, Andrea; Bock, Christopher; Boddy, Christopher Richard; Boehler, Michael; Boek, Thorsten Tobias; Bogaerts, Joannes Andreas; Bogdanchikov, Alexander; Bogouch, Andrei; Bohm, Christian; Bohm, Jan; Boisvert, Veronique; Bold, Tomasz; Boldea, Venera; Boldyrev, Alexey; Bomben, Marco; Bona, Marcella; Boonekamp, Maarten; Borisov, Anatoly; Borissov, Guennadi; Borri, Marcello; Borroni, Sara; Bortfeldt, Jonathan; Bortolotto, Valerio; Bos, Kors; Boscherini, Davide; Bosman, Martine; Boterenbrood, Hendrik; Boudreau, Joseph; Bouffard, Julian; Bouhova-Thacker, Evelina Vassileva; Boumediene, Djamel Eddine; Bourdarios, Claire; Bousson, Nicolas; Boutouil, Sara; Boveia, Antonio; Boyd, James; Boyko, Igor; Bracinik, Juraj; Brandt, Andrew; Brandt, Gerhard; Brandt, Oleg; Bratzler, Uwe; Brau, Benjamin; Brau, James; Braun, Helmut; Brazzale, Simone Federico; Brelier, Bertrand; Brendlinger, Kurt; Brennan, Amelia Jean; Brenner, Richard; Bressler, Shikma; Bristow, Kieran; Bristow, Timothy Michael; Britton, Dave; Brochu, Frederic; Brock, Ian; Brock, Raymond; Bromberg, Carl; Bronner, Johanna; Brooijmans, Gustaaf; Brooks, Timothy; Brooks, William; Brosamer, Jacquelyn; Brost, Elizabeth; Brown, Jonathan; Bruckman de Renstrom, Pawel; Bruncko, Dusan; Bruneliere, Renaud; Brunet, Sylvie; Bruni, Alessia; Bruni, Graziano; Bruschi, Marco; Bryngemark, Lene; Buanes, Trygve; Buat, Quentin; Bucci, Francesca; Buchholz, Peter; Buckingham, Ryan; Buckley, Andrew; Buda, Stelian Ioan; Budagov, Ioulian; Buehrer, Felix; Bugge, Lars; Bugge, Magnar Kopangen; Bulekov, Oleg; Bundock, Aaron Colin; Burckhart, Helfried; Burdin, Sergey; Burghgrave, Blake; Burke, Stephen; Burmeister, Ingo; Busato, Emmanuel; Büscher, Daniel; Büscher, Volker; Bussey, Peter; Buszello, Claus-Peter; Butler, Bart; Butler, John; Butt, Aatif Imtiaz; Buttar, Craig; Butterworth, Jonathan; Butti, Pierfrancesco; Buttinger, William; Buzatu, Adrian; Byszewski, Marcin; Cabrera Urbán, Susana; Caforio, Davide; Cakir, Orhan; Calafiura, Paolo; Calandri, Alessandro; Calderini, Giovanni; Calfayan, Philippe; Calkins, Robert; Caloba, Luiz; Calvet, David; Calvet, Samuel; Camacho Toro, Reina; Camarda, Stefano; Cameron, David; Caminada, Lea Michaela; Caminal Armadans, Roger; Campana, Simone; Campanelli, Mario; Campoverde, Angel; Canale, Vincenzo; Canepa, Anadi; Cano Bret, Marc; Cantero, Josu; Cantrill, Robert; Cao, Tingting; Capeans Garrido, Maria Del Mar; Caprini, Irinel; Caprini, Mihai; Capua, Marcella; Caputo, Regina; Cardarelli, Roberto; Carli, Tancredi; Carlino, Gianpaolo; Carminati, Leonardo; Caron, Sascha; Carquin, Edson; Carrillo-Montoya, German D; Carter, Janet; Carvalho, João; Casadei, Diego; Casado, Maria Pilar; Casolino, Mirkoantonio; Castaneda-Miranda, Elizabeth; Castelli, Angelantonio; Castillo Gimenez, Victoria; Castro, Nuno Filipe; Catastini, Pierluigi; Catinaccio, Andrea; Catmore, James; Cattai, Ariella; Cattani, Giordano; Caughron, Seth; Cavaliere, Viviana; Cavalli, Donatella; Cavalli-Sforza, Matteo; Cavasinni, Vincenzo; Ceradini, Filippo; Cerio, Benjamin; Cerny, Karel; Santiago Cerqueira, Augusto; Cerri, Alessandro; Cerrito, Lucio; Cerutti, Fabio; Cerv, Matevz; Cervelli, Alberto; Cetin, Serkant Ali; Chafaq, Aziz; Chakraborty, Dhiman; Chalupkova, Ina; Chang, Philip; Chapleau, Bertrand; Chapman, John Derek; Charfeddine, Driss; Charlton, Dave; Chau, Chav Chhiv; Chavez Barajas, Carlos Alberto; Cheatham, Susan; Chegwidden, Andrew; Chekanov, Sergei; Chekulaev, Sergey; Chelkov, Gueorgui; Chelstowska, Magda Anna; Chen, Chunhui; Chen, Hucheng; Chen, Karen; Chen, Liming; Chen, Shenjian; Chen, Xin; Chen, Yujiao; Cheng, Hok Chuen; Cheng, Yangyang; Cheplakov, Alexander; Cherkaoui El Moursli, Rajaa; Chernyatin, Valeriy; Cheu, Elliott; Chevalier, Laurent; Chiarella, Vitaliano; Chiefari, Giovanni; Childers, John Taylor; Chilingarov, Alexandre; Chiodini, Gabriele; Chisholm, Andrew; Chislett, Rebecca Thalatta; Chitan, Adrian; Chizhov, Mihail; Chouridou, Sofia; Chow, Bonnie Kar Bo; Chromek-Burckhart, Doris; Chu, Ming-Lee; Chudoba, Jiri; Chwastowski, Janusz; Chytka, Ladislav; Ciapetti, Guido; Ciftci, Abbas Kenan; Ciftci, Rena; Cinca, Diane; Cindro, Vladimir; Ciocio, Alessandra; Cirkovic, Predrag; Citron, Zvi Hirsh; Citterio, Mauro; Ciubancan, Mihai; Clark, Allan G; Clark, Philip James; Clarke, Robert; Cleland, Bill; Clemens, Jean-Claude; Clement, Christophe; Coadou, Yann; Cobal, Marina; Coccaro, Andrea; Cochran, James H; Coffey, Laurel; Cogan, Joshua Godfrey; Coggeshall, James; Cole, Brian; Cole, Stephen; Colijn, Auke-Pieter; Collot, Johann; Colombo, Tommaso; Colon, German; Compostella, Gabriele; Conde Muiño, Patricia; Coniavitis, Elias; Conidi, Maria Chiara; Connell, Simon Henry; Connelly, Ian; Consonni, Sofia Maria; Consorti, Valerio; Constantinescu, Serban; Conta, Claudio; Conti, Geraldine; Conventi, Francesco; Cooke, Mark; Cooper, Ben; Cooper-Sarkar, Amanda; Cooper-Smith, Neil; Copic, Katherine; Cornelissen, Thijs; Corradi, Massimo; Corriveau, Francois; Corso-Radu, Alina; Cortes-Gonzalez, Arely; Cortiana, Giorgio; Costa, Giuseppe; Costa, María José; Costanzo, Davide; Côté, David; Cottin, Giovanna; Cowan, Glen; Cox, Brian; Cranmer, Kyle; Cree, Graham; Crépé-Renaudin, Sabine; Crescioli, Francesco; Cribbs, Wayne Allen; Crispin Ortuzar, Mireia; Cristinziani, Markus; Croft, Vince; Crosetti, Giovanni; Cuciuc, Constantin-Mihai; Cuhadar Donszelmann, Tulay; Cummings, Jane; Curatolo, Maria; Cuthbert, Cameron; Czirr, Hendrik; Czodrowski, Patrick; Czyczula, Zofia; D'Auria, Saverio; D'Onofrio, Monica; Da Cunha Sargedas De Sousa, Mario Jose; Da Via, Cinzia; Dabrowski, Wladyslaw; Dafinca, Alexandru; Dai, Tiesheng; Dale, Orjan; Dallaire, Frederick; Dallapiccola, Carlo; Dam, Mogens; Daniells, Andrew Christopher; Dano Hoffmann, Maria; Dao, Valerio; Darbo, Giovanni; Darmora, Smita; Dassoulas, James; Dattagupta, Aparajita; Davey, Will; David, Claire; Davidek, Tomas; Davies, Eleanor; Davies, Merlin; Davignon, Olivier; Davison, Adam; Davison, Peter; Davygora, Yuriy; Dawe, Edmund; Dawson, Ian; Daya-Ishmukhametova, Rozmin; De, Kaushik; de Asmundis, Riccardo; De Castro, Stefano; De Cecco, Sandro; De Groot, Nicolo; de Jong, Paul; De la Torre, Hector; De Lorenzi, Francesco; De Nooij, Lucie; De Pedis, Daniele; De Salvo, Alessandro; De Sanctis, Umberto; De Santo, Antonella; De Vivie De Regie, Jean-Baptiste; Dearnaley, William James; Debbe, Ramiro; Debenedetti, Chiara; Dechenaux, Benjamin; Dedovich, Dmitri; Deigaard, Ingrid; Del Peso, Jose; Del Prete, Tarcisio; Deliot, Frederic; Delitzsch, Chris Malena; Deliyergiyev, Maksym; Dell'Acqua, Andrea; Dell'Asta, Lidia; Dell'Orso, Mauro; Della Pietra, Massimo; della Volpe, Domenico; Delmastro, Marco; Delsart, Pierre-Antoine; Deluca, Carolina; Demers, Sarah; Demichev, Mikhail; Demilly, Aurelien; Denisov, Sergey; Derendarz, Dominik; Derkaoui, Jamal Eddine; Derue, Frederic; Dervan, Paul; Desch, Klaus Kurt; Deterre, Cecile; Deviveiros, Pier-Olivier; Dewhurst, Alastair; Dhaliwal, Saminder; Di Ciaccio, Anna; Di Ciaccio, Lucia; Di Domenico, Antonio; Di Donato, Camilla; Di Girolamo, Alessandro; Di Girolamo, Beniamino; Di Mattia, Alessandro; Di Micco, Biagio; Di Nardo, Roberto; Di Simone, Andrea; Di Sipio, Riccardo; Di Valentino, David; Dias, Flavia; Diaz, Marco Aurelio; Diehl, Edward; Dietrich, Janet; Dietzsch, Thorsten; Diglio, Sara; Dimitrievska, Aleksandra; Dingfelder, Jochen; Dionisi, Carlo; Dita, Petre; Dita, Sanda; Dittus, Fridolin; Djama, Fares; Djobava, Tamar; Barros do Vale, Maria Aline; Do Valle Wemans, André; Doan, Thi Kieu Oanh; Dobos, Daniel; Doglioni, Caterina; Doherty, Tom; Dohmae, Takeshi; Dolejsi, Jiri; Dolezal, Zdenek; Dolgoshein, Boris; Donadelli, Marisilvia; Donati, Simone; Dondero, Paolo; Donini, Julien; Dopke, Jens; Doria, Alessandra; Dova, Maria-Teresa; Doyle, Tony; Dris, Manolis; Dubbert, Jörg; Dube, Sourabh; Dubreuil, Emmanuelle; Duchovni, Ehud; Duckeck, Guenter; Ducu, Otilia Anamaria; Duda, Dominik; Dudarev, Alexey; Dudziak, Fanny; Duflot, Laurent; Duguid, Liam; Dührssen, Michael; Dunford, Monica; Duran Yildiz, Hatice; Düren, Michael; Durglishvili, Archil; Dwuznik, Michal; Dyndal, Mateusz; Ebke, Johannes; Edson, William; Edwards, Nicholas Charles; Ehrenfeld, Wolfgang; Eifert, Till; Eigen, Gerald; Einsweiler, Kevin; Ekelof, Tord; El Kacimi, Mohamed; Ellert, Mattias; Elles, Sabine; Ellinghaus, Frank; Ellis, Nicolas; Elmsheuser, Johannes; Elsing, Markus; Emeliyanov, Dmitry; Enari, Yuji; Endner, Oliver Chris; Endo, Masaki; Engelmann, Roderich; Erdmann, Johannes; Ereditato, Antonio; Eriksson, Daniel; Ernis, Gunar; Ernst, Jesse; Ernst, Michael; Ernwein, Jean; Errede, Deborah; Errede, Steven; Ertel, Eugen; Escalier, Marc; Esch, Hendrik; Escobar, Carlos; Esposito, Bellisario; Etienvre, Anne-Isabelle; Etzion, Erez; Evans, Hal; Ezhilov, Alexey; Fabbri, Laura; Facini, Gabriel; Fakhrutdinov, Rinat; Falciano, Speranza; Falla, Rebecca Jane; Faltova, Jana; Fang, Yaquan; Fanti, Marcello; Farbin, Amir; Farilla, Addolorata; Farooque, Trisha; Farrell, Steven; Farrington, Sinead; Farthouat, Philippe; Fassi, Farida; Fassnacht, Patrick; Fassouliotis, Dimitrios; Favareto, Andrea; Fayard, Louis; Federic, Pavol; Fedin, Oleg; Fedorko, Wojciech; Fehling-Kaschek, Mirjam; Feigl, Simon; Feligioni, Lorenzo; Feng, Cunfeng; Feng, Eric; Feng, Haolu; Fenyuk, Alexander; Fernandez Perez, Sonia; Ferrag, Samir; Ferrando, James; Ferrari, Arnaud; Ferrari, Pamela; Ferrari, Roberto; Ferreira de Lima, Danilo Enoque; Ferrer, Antonio; Ferrere, Didier; Ferretti, Claudio; Ferretto Parodi, Andrea; Fiascaris, Maria; Fiedler, Frank; Filipčič, Andrej; Filipuzzi, Marco; Filthaut, Frank; Fincke-Keeler, Margret; Finelli, Kevin Daniel; Fiolhais, Miguel; Fiorini, Luca; Firan, Ana; Fischer, Adam; Fischer, Julia; Fisher, Wade Cameron; Fitzgerald, Eric Andrew; Flechl, Martin; Fleck, Ivor; Fleischmann, Philipp; Fleischmann, Sebastian; Fletcher, Gareth Thomas; Fletcher, Gregory; Flick, Tobias; Floderus, Anders; Flores Castillo, Luis; Florez Bustos, Andres Carlos; Flowerdew, Michael; Formica, Andrea; Forti, Alessandra; Fortin, Dominique; Fournier, Daniel; Fox, Harald; Fracchia, Silvia; Francavilla, Paolo; Franchini, Matteo; Franchino, Silvia; Francis, David; Franklin, Melissa; Franz, Sebastien; Fraternali, Marco; French, Sky; Friedrich, Conrad; Friedrich, Felix; Froidevaux, Daniel; Frost, James; Fukunaga, Chikara; Fullana Torregrosa, Esteban; Fulsom, Bryan Gregory; Fuster, Juan; Gabaldon, Carolina; Gabizon, Ofir; Gabrielli, Alessandro; Gabrielli, Andrea; Gadatsch, Stefan; Gadomski, Szymon; Gagliardi, Guido; Gagnon, Pauline; Galea, Cristina; Galhardo, Bruno; Gallas, Elizabeth; Gallo, Valentina Santina; Gallop, Bruce; Gallus, Petr; Galster, Gorm Aske Gram Krohn; Gan, KK; Gandrajula, Reddy Pratap; Gao, Jun; Gao, Yongsheng; Garay Walls, Francisca; Garberson, Ford; García, Carmen; García Navarro, José Enrique; Garcia-Sciveres, Maurice; Gardner, Robert; Garelli, Nicoletta; Garonne, Vincent; Gatti, Claudio; Gaudio, Gabriella; Gaur, Bakul; Gauthier, Lea; Gauzzi, Paolo; Gavrilenko, Igor; Gay, Colin; Gaycken, Goetz; Gazis, Evangelos; Ge, Peng; Gecse, Zoltan; Gee, Norman; Geerts, Daniël Alphonsus Adrianus; Geich-Gimbel, Christoph; Gellerstedt, Karl; Gemme, Claudia; Gemmell, Alistair; Genest, Marie-Hélène; Gentile, Simonetta; George, Matthias; George, Simon; Gerbaudo, Davide; Gershon, Avi; Ghazlane, Hamid; Ghodbane, Nabil; Giacobbe, Benedetto; Giagu, Stefano; Giangiobbe, Vincent; Giannetti, Paola; Gianotti, Fabiola; Gibbard, Bruce; Gibson, Stephen; Gilchriese, Murdock; Gillam, Thomas; Gillberg, Dag; Gilles, Geoffrey; Gingrich, Douglas; Giokaris, Nikos; Giordani, MarioPaolo; Giordano, Raffaele; Giorgi, Filippo Maria; Giorgi, Francesco Michelangelo; Giraud, Pierre-Francois; Giugni, Danilo; Giuliani, Claudia; Giulini, Maddalena; Gjelsten, Børge Kile; Gkaitatzis, Stamatios; Gkialas, Ioannis; Gladilin, Leonid; Glasman, Claudia; Glatzer, Julian; Glaysher, Paul; Glazov, Alexandre; Glonti, George; Goblirsch-Kolb, Maximilian; Goddard, Jack Robert; Godfrey, Jennifer; Godlewski, Jan; Goeringer, Christian; Goldfarb, Steven; Golling, Tobias; Golubkov, Dmitry; Gomes, Agostinho; Gomez Fajardo, Luz Stella; Gonçalo, Ricardo; Goncalves Pinto Firmino Da Costa, Joao; Gonella, Laura; González de la Hoz, Santiago; Gonzalez Parra, Garoe; Gonzalez-Sevilla, Sergio; Goossens, Luc; Gorbounov, Petr Andreevich; Gordon, Howard; Gorelov, Igor; Gorini, Benedetto; Gorini, Edoardo; Gorišek, Andrej; Gornicki, Edward; Goshaw, Alfred; Gössling, Claus; Gostkin, Mikhail Ivanovitch; Gouighri, Mohamed; Goujdami, Driss; Goulette, Marc Phillippe; Goussiou, Anna; Goy, Corinne; Gozpinar, Serdar; Grabas, Herve Marie Xavier; Graber, Lars; Grabowska-Bold, Iwona; Grafström, Per; Grahn, Karl-Johan; Gramling, Johanna; Gramstad, Eirik; Grancagnolo, Sergio; Grassi, Valerio; Gratchev, Vadim; Gray, Heather; Graziani, Enrico; Grebenyuk, Oleg; Greenwood, Zeno Dixon; Gregersen, Kristian; Gregor, Ingrid-Maria; Grenier, Philippe; Griffiths, Justin; Grillo, Alexander; Grimm, Kathryn; Grinstein, Sebastian; Gris, Philippe Luc Yves; Grishkevich, Yaroslav; Grivaz, Jean-Francois; Grohs, Johannes Philipp; Grohsjean, Alexander; Gross, Eilam; Grosse-Knetter, Joern; Grossi, Giulio Cornelio; Groth-Jensen, Jacob; Grout, Zara Jane; Guan, Liang; Guescini, Francesco; Guest, Daniel; Gueta, Orel; Guicheney, Christophe; Guido, Elisa; Guillemin, Thibault; Guindon, Stefan; Gul, Umar; Gumpert, Christian; Gunther, Jaroslav; Guo, Jun; Gupta, Shaun; Gutierrez, Phillip; Gutierrez Ortiz, Nicolas Gilberto; Gutschow, Christian; Guttman, Nir; Guyot, Claude; Gwenlan, Claire; Gwilliam, Carl; Haas, Andy; Haber, Carl; Hadavand, Haleh Khani; Haddad, Nacim; Haefner, Petra; Hageböck, Stephan; Hajduk, Zbigniew; Hakobyan, Hrachya; Haleem, Mahsana; Hall, David; Halladjian, Garabed; Hamacher, Klaus; Hamal, Petr; Hamano, Kenji; Hamer, Matthias; Hamilton, Andrew; Hamilton, Samuel; Hamnett, Phillip George; Han, Liang; Hanagaki, Kazunori; Hanawa, Keita; Hance, Michael; Hanke, Paul; Hanna, Remie; Hansen, Jørgen Beck; Hansen, Jorn Dines; Hansen, Peter Henrik; Hara, Kazuhiko; Hard, Andrew; Harenberg, Torsten; Hariri, Faten; Harkusha, Siarhei; Harper, Devin; Harrington, Robert; Harris, Orin; Harrison, Paul Fraser; Hartjes, Fred; Hasegawa, Satoshi; Hasegawa, Yoji; Hasib, A; Hassani, Samira; Haug, Sigve; Hauschild, Michael; Hauser, Reiner; Havranek, Miroslav; Hawkes, Christopher; Hawkings, Richard John; Hawkins, Anthony David; Hayashi, Takayasu; Hayden, Daniel; Hays, Chris; Hayward, Helen; Haywood, Stephen; Head, Simon; Heck, Tobias; Hedberg, Vincent; Heelan, Louise; Heim, Sarah; Heim, Timon; Heinemann, Beate; Heinrich, Lukas; Hejbal, Jiri; Helary, Louis; Heller, Claudio; Heller, Matthieu; Hellman, Sten; Hellmich, Dennis; Helsens, Clement; Henderson, James; Henderson, Robert; Heng, Yang; Hengler, Christopher; Henrichs, Anna; Henriques Correia, Ana Maria; Henrot-Versille, Sophie; Hensel, Carsten; Herbert, Geoffrey Henry; Hernández Jiménez, Yesenia; Herrberg-Schubert, Ruth; Herten, Gregor; Hertenberger, Ralf; Hervas, Luis; Hesketh, Gavin Grant; Hessey, Nigel; Hickling, Robert; Higón-Rodriguez, Emilio; Hill, Ewan; Hill, John; Hiller, Karl Heinz; Hillert, Sonja; Hillier, Stephen; Hinchliffe, Ian; Hines, Elizabeth; Hirose, Minoru; Hirschbuehl, Dominic; Hobbs, John; Hod, Noam; Hodgkinson, Mark; Hodgson, Paul; Hoecker, Andreas; Hoeferkamp, Martin; Hoffman, Julia; Hoffmann, Dirk; Hofmann, Julia Isabell; Hohlfeld, Marc; Holmes, Tova Ray; Hong, Tae Min; Hooft van Huysduynen, Loek; Hostachy, Jean-Yves; Hou, Suen; Hoummada, Abdeslam; Howard, Jacob; Howarth, James; Hrabovsky, Miroslav; Hristova, Ivana; Hrivnac, Julius; Hryn'ova, Tetiana; Hsu, Catherine; Hsu, Pai-hsien Jennifer; Hsu, Shih-Chieh; Hu, Diedi; Hu, Xueye; Huang, Yanping; Hubacek, Zdenek; Hubaut, Fabrice; Huegging, Fabian; Huffman, Todd Brian; Hughes, Emlyn; Hughes, Gareth; Huhtinen, Mika; Hülsing, Tobias Alexander; Hurwitz, Martina; Huseynov, Nazim; Huston, Joey; Huth, John; Iacobucci, Giuseppe; Iakovidis, Georgios; Ibragimov, Iskander; Iconomidou-Fayard, Lydia; Ideal, Emma; Iengo, Paolo; Igonkina, Olga; Iizawa, Tomoya; Ikegami, Yoichi; Ikematsu, Katsumasa; Ikeno, Masahiro; Ilchenko, Iurii; Iliadis, Dimitrios; Ilic, Nikolina; Inamaru, Yuki; Ince, Tayfun; Ioannou, Pavlos; Iodice, Mauro; Iordanidou, Kalliopi; Ippolito, Valerio; Irles Quiles, Adrian; Isaksson, Charlie; Ishino, Masaya; Ishitsuka, Masaki; Ishmukhametov, Renat; Issever, Cigdem; Istin, Serhat; Iturbe Ponce, Julia Mariana; Iuppa, Roberto; Ivarsson, Jenny; Iwanski, Wieslaw; Iwasaki, Hiroyuki; Izen, Joseph; Izzo, Vincenzo; Jackson, Brett; Jackson, Matthew; Jackson, Paul; Jaekel, Martin; Jain, Vivek; Jakobs, Karl; Jakobsen, Sune; Jakoubek, Tomas; Jakubek, Jan; Jamin, David Olivier; Jana, Dilip; Jansen, Eric; Jansen, Hendrik; Janssen, Jens; Janus, Michel; Jarlskog, Göran; Javadov, Namig; Javůrek, Tomáš; Jeanty, Laura; Jejelava, Juansher; Jeng, Geng-yuan; Jennens, David; Jenni, Peter; Jentzsch, Jennifer; Jeske, Carl; Jézéquel, Stéphane; Ji, Haoshuang; Ji, Weina; Jia, Jiangyong; Jiang, Yi; Jimenez Belenguer, Marcos; Jin, Shan; Jinaru, Adam; Jinnouchi, Osamu; Joergensen, Morten Dam; Johansson, Erik; Johansson, Per; Johns, Kenneth; Jon-And, Kerstin; Jones, Graham; Jones, Roger; Jones, Tim; Jongmanns, Jan; Jorge, Pedro; Joshi, Kiran Daniel; Jovicevic, Jelena; Ju, Xiangyang; Jung, Christian; Jungst, Ralph Markus; Jussel, Patrick; Juste Rozas, Aurelio; Kaci, Mohammed; Kaczmarska, Anna; Kado, Marumi; Kagan, Harris; Kagan, Michael; Kajomovitz, Enrique; Kalderon, Charles William; Kama, Sami; Kamenshchikov, Andrey; Kanaya, Naoko; Kaneda, Michiru; Kaneti, Steven; Kantserov, Vadim; Kanzaki, Junichi; Kaplan, Benjamin; Kapliy, Anton; Kar, Deepak; Karakostas, Konstantinos; Karastathis, Nikolaos; Karnevskiy, Mikhail; Karpov, Sergey; Karpova, Zoya; Karthik, Krishnaiyengar; Kartvelishvili, Vakhtang; Karyukhin, Andrey; Kashif, Lashkar; Kasieczka, Gregor; Kass, Richard; Kastanas, Alex; Kataoka, Yousuke; Katre, Akshay; Katzy, Judith; Kaushik, Venkatesh; Kawagoe, Kiyotomo; Kawamoto, Tatsuo; Kawamura, Gen; Kazama, Shingo; Kazanin, Vassili; Kazarinov, Makhail; Keeler, Richard; Kehoe, Robert; Keil, Markus; Keller, John; Kempster, Jacob Julian; Keoshkerian, Houry; Kepka, Oldrich; Kerševan, Borut Paul; Kersten, Susanne; Kessoku, Kohei; Keung, Justin; Khalil-zada, Farkhad; Khandanyan, Hovhannes; Khanov, Alexander; Khodinov, Alexander; Khomich, Andrei; Khoo, Teng Jian; Khoriauli, Gia; Khoroshilov, Andrey; Khovanskiy, Valery; Khramov, Evgeniy; Khubua, Jemal; Kim, Hee Yeun; Kim, Hyeon Jin; Kim, Shinhong; Kimura, Naoki; Kind, Oliver; King, Barry; King, Matthew; King, Robert Steven Beaufoy; King, Samuel Burton; Kirk, Julie; Kiryunin, Andrey; Kishimoto, Tomoe; Kisielewska, Danuta; Kiss, Florian; Kittelmann, Thomas; Kiuchi, Kenji; Kladiva, Eduard; Klein, Max; Klein, Uta; Kleinknecht, Konrad; Klimek, Pawel; Klimentov, Alexei; Klingenberg, Reiner; Klinger, Joel Alexander; Klioutchnikova, Tatiana; Klok, Peter; Kluge, Eike-Erik; Kluit, Peter; Kluth, Stefan; Kneringer, Emmerich; Knoops, Edith; Knue, Andrea; Kobayashi, Dai; Kobayashi, Tomio; Kobel, Michael; Kocian, Martin; Kodys, Peter; Koevesarki, Peter; Koffas, Thomas; Koffeman, Els; Kogan, Lucy Anne; Kohlmann, Simon; Kohout, Zdenek; Kohriki, Takashi; Koi, Tatsumi; Kolanoski, Hermann; Koletsou, Iro; Koll, James; Komar, Aston; Komori, Yuto; Kondo, Takahiko; Kondrashova, Nataliia; Köneke, Karsten; König, Adriaan; König, Sebastian; Kono, Takanori; Konoplich, Rostislav; Konstantinidis, Nikolaos; Kopeliansky, Revital; Koperny, Stefan; Köpke, Lutz; Kopp, Anna Katharina; Korcyl, Krzysztof; Kordas, Kostantinos; Korn, Andreas; Korol, Aleksandr; Korolkov, Ilya; Korolkova, Elena; Korotkov, Vladislav; Kortner, Oliver; Kortner, Sandra; Kostyukhin, Vadim; Kotov, Vladislav; Kotwal, Ashutosh; Kourkoumelis, Christine; Kouskoura, Vasiliki; Koutsman, Alex; Kowalewski, Robert Victor; Kowalski, Tadeusz; Kozanecki, Witold; Kozhin, Anatoly; Kral, Vlastimil; Kramarenko, Viktor; Kramberger, Gregor; Krasnopevtsev, Dimitriy; Krasny, Mieczyslaw Witold; Krasznahorkay, Attila; Kraus, Jana; Kravchenko, Anton; Kreiss, Sven; Kretz, Moritz; Kretzschmar, Jan; Kreutzfeldt, Kristof; Krieger, Peter; Kroeninger, Kevin; Kroha, Hubert; Kroll, Joe; Kroseberg, Juergen; Krstic, Jelena; Kruchonak, Uladzimir; Krüger, Hans; Kruker, Tobias; Krumnack, Nils; Krumshteyn, Zinovii; Kruse, Amanda; Kruse, Mark; Kruskal, Michael; Kubota, Takashi; Kuday, Sinan; Kuehn, Susanne; Kugel, Andreas; Kuhl, Andrew; Kuhl, Thorsten; Kukhtin, Victor; Kulchitsky, Yuri; Kuleshov, Sergey; Kuna, Marine; Kunkle, Joshua; Kupco, Alexander; Kurashige, Hisaya; Kurochkin, Yurii; Kurumida, Rie; Kus, Vlastimil; Kuwertz, Emma Sian; Kuze, Masahiro; Kvita, Jiri; La Rosa, Alessandro; La Rotonda, Laura; Lacasta, Carlos; Lacava, Francesco; Lacey, James; Lacker, Heiko; Lacour, Didier; Lacuesta, Vicente Ramón; Ladygin, Evgueni; Lafaye, Remi; Laforge, Bertrand; Lagouri, Theodota; Lai, Stanley; Laier, Heiko; Lambourne, Luke; Lammers, Sabine; Lampen, Caleb; Lampl, Walter; Lançon, Eric; Landgraf, Ulrich; Landon, Murrough; Lang, Valerie Susanne; Lankford, Andrew; Lanni, Francesco; Lantzsch, Kerstin; Laplace, Sandrine; Lapoire, Cecile; Laporte, Jean-Francois; Lari, Tommaso; Lassnig, Mario; Laurelli, Paolo; Lavrijsen, Wim; Law, Alexander; Laycock, Paul; Le, Bao Tran; Le Dortz, Olivier; Le Guirriec, Emmanuel; Le Menedeu, Eve; LeCompte, Thomas; Ledroit-Guillon, Fabienne Agnes Marie; Lee, Claire Alexandra; Lee, Hurng-Chun; Lee, Jason; Lee, Shih-Chang; Lee, Lawrence; Lefebvre, Guillaume; Lefebvre, Michel; Legger, Federica; Leggett, Charles; Lehan, Allan; Lehmacher, Marc; Lehmann Miotto, Giovanna; Lei, Xiaowen; Leight, William Axel; Leisos, Antonios; Leister, Andrew Gerard; Leite, Marco Aurelio Lisboa; Leitner, Rupert; Lellouch, Daniel; Lemmer, Boris; Leney, Katharine; Lenz, Tatjana; Lenzen, Georg; Lenzi, Bruno; Leone, Robert; Leone, Sandra; Leonhardt, Kathrin; Leonidopoulos, Christos; Leontsinis, Stefanos; Leroy, Claude; Lester, Christopher; Lester, Christopher Michael; Levchenko, Mikhail; Levêque, Jessica; Levin, Daniel; Levinson, Lorne; Levy, Mark; Lewis, Adrian; Lewis, George; Leyko, Agnieszka; Leyton, Michael; Li, Bing; Li, Bo; Li, Haifeng; Li, Ho Ling; Li, Lei; Li, Liang; Li, Shu; Li, Yichen; Liang, Zhijun; Liao, Hongbo; Liberti, Barbara; Lichard, Peter; Lie, Ki; Liebal, Jessica; Liebig, Wolfgang; Limbach, Christian; Limosani, Antonio; Lin, Simon; Lin, Tai-Hua; Linde, Frank; Lindquist, Brian Edward; Linnemann, James; Lipeles, Elliot; Lipniacka, Anna; Lisovyi, Mykhailo; Liss, Tony; Lissauer, David; Lister, Alison; Litke, Alan; Liu, Bo; Liu, Dong; Liu, Jianbei; Liu, Kun; Liu, Lulu; Liu, Miaoyuan; Liu, Minghui; Liu, Yanwen; Livan, Michele; Livermore, Sarah; Lleres, Annick; Llorente Merino, Javier; Lloyd, Stephen; Lo Sterzo, Francesco; Lobodzinska, Ewelina; Loch, Peter; Lockman, William; Loddenkoetter, Thomas; Loebinger, Fred; Loevschall-Jensen, Ask Emil; Loginov, Andrey; Loh, Chang Wei; Lohse, Thomas; Lohwasser, Kristin; Lokajicek, Milos; Lombardo, Vincenzo Paolo; Long, Brian Alexander; Long, Jonathan; Long, Robin Eamonn; Lopes, Lourenco; Lopez Mateos, David; Lopez Paredes, Brais; Lopez Paz, Ivan; Lorenz, Jeanette; Lorenzo Martinez, Narei; Losada, Marta; Loscutoff, Peter; Lou, XinChou; Lounis, Abdenour; Love, Jeremy; Love, Peter; Lowe, Andrew; Lu, Feng; Lubatti, Henry; Luci, Claudio; Lucotte, Arnaud; Luehring, Frederick; Lukas, Wolfgang; Luminari, Lamberto; Lundberg, Olof; Lund-Jensen, Bengt; Lungwitz, Matthias; Lynn, David; Lysak, Roman; Lytken, Else; Ma, Hong; Ma, Lian Liang; Maccarrone, Giovanni; Macchiolo, Anna; Machado Miguens, Joana; Macina, Daniela; Madaffari, Daniele; Madar, Romain; Maddocks, Harvey Jonathan; Mader, Wolfgang; Madsen, Alexander; Maeno, Mayuko; Maeno, Tadashi; Magradze, Erekle; Mahboubi, Kambiz; Mahlstedt, Joern; Mahmoud, Sara; Maiani, Camilla; Maidantchik, Carmen; Maier, Andreas Alexander; Maio, Amélia; Majewski, Stephanie; Makida, Yasuhiro; Makovec, Nikola; Mal, Prolay; Malaescu, Bogdan; Malecki, Pawel; Maleev, Victor; Malek, Fairouz; Mallik, Usha; Malon, David; Malone, Caitlin; Maltezos, Stavros; Malyshev, Vladimir; Malyukov, Sergei; Mamuzic, Judita; Mandelli, Beatrice; Mandelli, Luciano; Mandić, Igor; Mandrysch, Rocco; Maneira, José; Manfredini, Alessandro; Manhaes de Andrade Filho, Luciano; Manjarres Ramos, Joany Andreina; Mann, Alexander; Manning, Peter; Manousakis-Katsikakis, Arkadios; Mansoulie, Bruno; Mantifel, Rodger; Mapelli, Livio; March, Luis; Marchand, Jean-Francois; Marchiori, Giovanni; Marcisovsky, Michal; Marino, Christopher; Marjanovic, Marija; Marques, Carlos; Marroquim, Fernando; Marsden, Stephen Philip; Marshall, Zach; Marti, Lukas Fritz; Marti-Garcia, Salvador; Martin, Brian; Martin, Brian Thomas; Martin, Tim; Martin, Victoria Jane; Martin dit Latour, Bertrand; Martinez, Homero; Martinez, Mario; Martin-Haugh, Stewart; Martyniuk, Alex; Marx, Marilyn; Marzano, Francesco; Marzin, Antoine; Masetti, Lucia; Mashimo, Tetsuro; Mashinistov, Ruslan; Masik, Jiri; Maslennikov, Alexey; Massa, Ignazio; Massol, Nicolas; Mastrandrea, Paolo; Mastroberardino, Anna; Masubuchi, Tatsuya; Mättig, Peter; Mattmann, Johannes; Maurer, Julien; Maxfield, Stephen; Maximov, Dmitriy; Mazini, Rachid; Mazzaferro, Luca; Mc Goldrick, Garrin; Mc Kee, Shawn Patrick; McCarn, Allison; McCarthy, Robert; McCarthy, Tom; McCubbin, Norman; McFarlane, Kenneth; Mcfayden, Josh; Mchedlidze, Gvantsa; McMahon, Steve; McPherson, Robert; Meade, Andrew; Mechnich, Joerg; Medinnis, Michael; Meehan, Samuel; Mehlhase, Sascha; Mehta, Andrew; Meier, Karlheinz; Meineck, Christian; Meirose, Bernhard; Melachrinos, Constantinos; Mellado Garcia, Bruce Rafael; Meloni, Federico; Mengarelli, Alberto; Menke, Sven; Meoni, Evelin; Mercurio, Kevin Michael; Mergelmeyer, Sebastian; Meric, Nicolas; Mermod, Philippe; Merola, Leonardo; Meroni, Chiara; Merritt, Frank; Merritt, Hayes; Messina, Andrea; Metcalfe, Jessica; Mete, Alaettin Serhan; Meyer, Carsten; Meyer, Christopher; Meyer, Jean-Pierre; Meyer, Jochen; Middleton, Robin; Migas, Sylwia; Mijović, Liza; Mikenberg, Giora; Mikestikova, Marcela; Mikuž, Marko; Milic, Adriana; Miller, David; Mills, Corrinne; Milov, Alexander; Milstead, David; Milstein, Dmitry; Minaenko, Andrey; Minashvili, Irakli; Mincer, Allen; Mindur, Bartosz; Mineev, Mikhail; Ming, Yao; Mir, Lluisa-Maria; Mirabelli, Giovanni; Mitani, Takashi; Mitrevski, Jovan; Mitsou, Vasiliki A; Mitsui, Shingo; Miucci, Antonio; Miyagawa, Paul; Mjörnmark, Jan-Ulf; Moa, Torbjoern; Mochizuki, Kazuya; Mohapatra, Soumya; Mohr, Wolfgang; Molander, Simon; Moles-Valls, Regina; Mönig, Klaus; Monini, Caterina; Monk, James; Monnier, Emmanuel; Montejo Berlingen, Javier; Monticelli, Fernando; Monzani, Simone; Moore, Roger; Moraes, Arthur; Morange, Nicolas; Moreno, Deywis; Moreno Llácer, María; Morettini, Paolo; Morgenstern, Marcus; Morii, Masahiro; Moritz, Sebastian; Morley, Anthony Keith; Mornacchi, Giuseppe; Morris, John; Morvaj, Ljiljana; Moser, Hans-Guenther; Mosidze, Maia; Moss, Josh; Motohashi, Kazuki; Mount, Richard; Mountricha, Eleni; Mouraviev, Sergei; Moyse, Edward; Muanza, Steve; Mudd, Richard; Mueller, Felix; Mueller, James; Mueller, Klemens; Mueller, Thibaut; Mueller, Timo; Muenstermann, Daniel; Munwes, Yonathan; Murillo Quijada, Javier Alberto; Murray, Bill; Musheghyan, Haykuhi; Musto, Elisa; Myagkov, Alexey; Myska, Miroslav; Nackenhorst, Olaf; Nadal, Jordi; Nagai, Koichi; Nagai, Ryo; Nagai, Yoshikazu; Nagano, Kunihiro; Nagarkar, Advait; Nagasaka, Yasushi; Nagel, Martin; Nairz, Armin Michael; Nakahama, Yu; Nakamura, Koji; Nakamura, Tomoaki; Nakano, Itsuo; Namasivayam, Harisankar; Nanava, Gizo; Narayan, Rohin; Nattermann, Till; Naumann, Thomas; Navarro, Gabriela; Nayyar, Ruchika; Neal, Homer; Nechaeva, Polina; Neep, Thomas James; Nef, Pascal Daniel; Negri, Andrea; Negri, Guido; Negrini, Matteo; Nektarijevic, Snezana; Nelson, Andrew; Nelson, Timothy Knight; Nemecek, Stanislav; Nemethy, Peter; Nepomuceno, Andre Asevedo; Nessi, Marzio; Neubauer, Mark; Neumann, Manuel; Neves, Ricardo; Nevski, Pavel; Newman, Paul; Nguyen, Duong Hai; Nickerson, Richard; Nicolaidou, Rosy; Nicquevert, Bertrand; Nielsen, Jason; Nikiforou, Nikiforos; Nikiforov, Andriy; Nikolaenko, Vladimir; Nikolic-Audit, Irena; Nikolics, Katalin; Nikolopoulos, Konstantinos; Nilsson, Paul; Ninomiya, Yoichi; Nisati, Aleandro; Nisius, Richard; Nobe, Takuya; Nodulman, Lawrence; Nomachi, Masaharu; Nomidis, Ioannis; Norberg, Scarlet; Nordberg, Markus; Novgorodova, Olga; Nowak, Sebastian; Nozaki, Mitsuaki; Nozka, Libor; Ntekas, Konstantinos; Nunes Hanninger, Guilherme; Nunnemann, Thomas; Nurse, Emily; Nuti, Francesco; O'Brien, Brendan Joseph; O'grady, Fionnbarr; O'Neil, Dugan; O'Shea, Val; Oakham, Gerald; Oberlack, Horst; Obermann, Theresa; Ocariz, Jose; Ochi, Atsuhiko; Ochoa, Ines; Oda, Susumu; Odaka, Shigeru; Ogren, Harold; Oh, Alexander; Oh, Seog; Ohm, Christian; Ohman, Henrik; Ohshima, Takayoshi; Okamura, Wataru; Okawa, Hideki; Okumura, Yasuyuki; Okuyama, Toyonobu; Olariu, Albert; Olchevski, Alexander; Olivares Pino, Sebastian Andres; Oliveira Damazio, Denis; Oliver Garcia, Elena; Olszewski, Andrzej; Olszowska, Jolanta; Onofre, António; Onyisi, Peter; Oram, Christopher; Oreglia, Mark; Oren, Yona; Orestano, Domizia; Orlando, Nicola; Oropeza Barrera, Cristina; Orr, Robert; Osculati, Bianca; Ospanov, Rustem; Otero y Garzon, Gustavo; Otono, Hidetoshi; Ouchrif, Mohamed; Ouellette, Eric; Ould-Saada, Farid; Ouraou, Ahmimed; Oussoren, Koen Pieter; Ouyang, Qun; Ovcharova, Ana; Owen, Mark; Ozcan, Veysi Erkcan; Ozturk, Nurcan; Pachal, Katherine; Pacheco Pages, Andres; Padilla Aranda, Cristobal; Pagáčová, Martina; Pagan Griso, Simone; Paganis, Efstathios; Pahl, Christoph; Paige, Frank; Pais, Preema; Pajchel, Katarina; Palacino, Gabriel; Palestini, Sandro; Palka, Marek; Pallin, Dominique; Palma, Alberto; Palmer, Jody; Pan, Yibin; Panagiotopoulou, Evgenia; Panduro Vazquez, William; Pani, Priscilla; Panikashvili, Natalia; Panitkin, Sergey; Pantea, Dan; Paolozzi, Lorenzo; Papadopoulou, Theodora; Papageorgiou, Konstantinos; Paramonov, Alexander; Paredes Hernandez, Daniela; Parker, Michael Andrew; Parodi, Fabrizio; Parsons, John; Parzefall, Ulrich; Pasqualucci, Enrico; Passaggio, Stefano; Passeri, Antonio; Pastore, Fernanda; Pastore, Francesca; Pásztor, Gabriella; Pataraia, Sophio; Patel, Nikhul; Pater, Joleen; Patricelli, Sergio; Pauly, Thilo; Pearce, James; Pedersen, Maiken; Pedraza Lopez, Sebastian; Pedro, Rute; Peleganchuk, Sergey; Pelikan, Daniel; Peng, Haiping; Penning, Bjoern; Penwell, John; Perepelitsa, Dennis; Perez Codina, Estel; Pérez García-Estañ, María Teresa; Perez Reale, Valeria; Perini, Laura; Pernegger, Heinz; Perrino, Roberto; Peschke, Richard; Peshekhonov, Vladimir; Peters, Krisztian; Peters, Yvonne; Petersen, Brian; Petersen, Troels; Petit, Elisabeth; Petridis, Andreas; Petridou, Chariclia; Petrolo, Emilio; Petrucci, Fabrizio; Pettersson, Nora Emilia; Pezoa, Raquel; Phillips, Peter William; Piacquadio, Giacinto; Pianori, Elisabetta; Picazio, Attilio; Piccaro, Elisa; Piccinini, Maurizio; Piegaia, Ricardo; Pignotti, David; Pilcher, James; Pilkington, Andrew; Pina, João Antonio; Pinamonti, Michele; Pinder, Alex; Pinfold, James; Pingel, Almut; Pinto, Belmiro; Pires, Sylvestre; Pitt, Michael; Pizio, Caterina; Plazak, Lukas; Pleier, Marc-Andre; Pleskot, Vojtech; Plotnikova, Elena; Plucinski, Pawel; Poddar, Sahill; Podlyski, Fabrice; Poettgen, Ruth; Poggioli, Luc; Pohl, David-leon; Pohl, Martin; Polesello, Giacomo; Policicchio, Antonio; Polifka, Richard; Polini, Alessandro; Pollard, Christopher Samuel; Polychronakos, Venetios; Pommès, Kathy; Pontecorvo, Ludovico; Pope, Bernard; Popeneciu, Gabriel Alexandru; Popovic, Dragan; Poppleton, Alan; Portell Bueso, Xavier; Pospisil, Stanislav; Potamianos, Karolos; Potrap, Igor; Potter, Christina; Potter, Christopher; Poulard, Gilbert; Poveda, Joaquin; Pozdnyakov, Valery; Pralavorio, Pascal; Pranko, Aliaksandr; Prasad, Srivas; Pravahan, Rishiraj; Prell, Soeren; Price, Darren; Price, Joe; Price, Lawrence; Prieur, Damien; Primavera, Margherita; Proissl, Manuel; Prokofiev, Kirill; Prokoshin, Fedor; Protopapadaki, Eftychia-sofia; Protopopescu, Serban; Proudfoot, James; Przybycien, Mariusz; Przysiezniak, Helenka; Ptacek, Elizabeth; Puddu, Daniele; Pueschel, Elisa; Puldon, David; Purohit, Milind; Puzo, Patrick; Qian, Jianming; Qin, Gang; Qin, Yang; Quadt, Arnulf; Quarrie, David; Quayle, William; Queitsch-Maitland, Michaela; Quilty, Donnchadha; Qureshi, Anum; Radeka, Veljko; Radescu, Voica; Radhakrishnan, Sooraj Krishnan; Radloff, Peter; Rados, Pere; Ragusa, Francesco; Rahal, Ghita; Rajagopalan, Srinivasan; Rammensee, Michael; Randle-Conde, Aidan Sean; Rangel-Smith, Camila; Rao, Kanury; Rauscher, Felix; Rave, Tobias Christian; Ravenscroft, Thomas; Raymond, Michel; Read, Alexander Lincoln; Readioff, Nathan Peter; Rebuzzi, Daniela; Redelbach, Andreas; Redlinger, George; Reece, Ryan; Reeves, Kendall; Rehnisch, Laura; Reisin, Hernan; Relich, Matthew; Rembser, Christoph; Ren, Huan; Ren, Zhongliang; Renaud, Adrien; Rescigno, Marco; Resconi, Silvia; Rezanova, Olga; Reznicek, Pavel; Rezvani, Reyhaneh; Richter, Robert; Ridel, Melissa; Rieck, Patrick; Rieger, Julia; Rijssenbeek, Michael; Rimoldi, Adele; Rinaldi, Lorenzo; Ritsch, Elmar; Riu, Imma; Rizatdinova, Flera; Rizvi, Eram; Robertson, Steven; Robichaud-Veronneau, Andree; Robinson, Dave; Robinson, James; Robson, Aidan; Roda, Chiara; Rodrigues, Luis; Roe, Shaun; Røhne, Ole; Rolli, Simona; Romaniouk, Anatoli; Romano, Marino; Romero Adam, Elena; Rompotis, Nikolaos; Roos, Lydia; Ros, Eduardo; Rosati, Stefano; Rosbach, Kilian; Rose, Matthew; Rosendahl, Peter Lundgaard; Rosenthal, Oliver; Rossetti, Valerio; Rossi, Elvira; Rossi, Leonardo Paolo; Rosten, Rachel; Rotaru, Marina; Roth, Itamar; Rothberg, Joseph; Rousseau, David; Royon, Christophe; Rozanov, Alexandre; Rozen, Yoram; Ruan, Xifeng; Rubbo, Francesco; Rubinskiy, Igor; Rud, Viacheslav; Rudolph, Christian; Rudolph, Matthew Scott; Rühr, Frederik; Ruiz-Martinez, Aranzazu; Rurikova, Zuzana; Rusakovich, Nikolai; Ruschke, Alexander; Rutherfoord, John; Ruthmann, Nils; Ryabov, Yury; Rybar, Martin; Rybkin, Grigori; Ryder, Nick; Saavedra, Aldo; Sacerdoti, Sabrina; Saddique, Asif; Sadeh, Iftach; Sadrozinski, Hartmut; Sadykov, Renat; Safai Tehrani, Francesco; Sakamoto, Hiroshi; Sakurai, Yuki; Salamanna, Giuseppe; Salamon, Andrea; Saleem, Muhammad; Salek, David; Sales De Bruin, Pedro Henrique; Salihagic, Denis; Salnikov, Andrei; Salt, José; Salvachua Ferrando, Belén; Salvatore, Daniela; Salvatore, Pasquale Fabrizio; Salvucci, Antonio; Salzburger, Andreas; Sampsonidis, Dimitrios; Sanchez, Arturo; Sánchez, Javier; Sanchez Martinez, Victoria; Sandaker, Heidi; Sandbach, Ruth Laura; Sander, Heinz Georg; Sanders, Michiel; Sandhoff, Marisa; Sandoval, Tanya; Sandoval, Carlos; Sandstroem, Rikard; Sankey, Dave; Sansoni, Andrea; Santoni, Claudio; Santonico, Rinaldo; Santos, Helena; Santoyo Castillo, Itzebelt; Sapp, Kevin; Sapronov, Andrey; Saraiva, João; Sarrazin, Bjorn; Sartisohn, Georg; Sasaki, Osamu; Sasaki, Yuichi; Sauvage, Gilles; Sauvan, Emmanuel; Savard, Pierre; Savu, Dan Octavian; Sawyer, Craig; Sawyer, Lee; Saxon, David; Saxon, James; Sbarra, Carla; Sbrizzi, Antonio; Scanlon, Tim; Scannicchio, Diana; Scarcella, Mark; Scarfone, Valerio; Schaarschmidt, Jana; Schacht, Peter; Schaefer, Douglas; Schaefer, Ralph; Schaepe, Steffen; Schaetzel, Sebastian; Schäfer, Uli; Schaffer, Arthur; Schaile, Dorothee; Schamberger, R. Dean; Scharf, Veit; Schegelsky, Valery; Scheirich, Daniel; Schernau, Michael; Scherzer, Max; Schiavi, Carlo; Schieck, Jochen; Schillo, Christian; Schioppa, Marco; Schlenker, Stefan; Schmidt, Evelyn; Schmieden, Kristof; Schmitt, Christian; Schmitt, Christopher; Schmitt, Sebastian; Schneider, Basil; Schnellbach, Yan Jie; Schnoor, Ulrike; Schoeffel, Laurent; Schoening, Andre; Schoenrock, Bradley Daniel; Schorlemmer, Andre Lukas; Schott, Matthias; Schouten, Doug; Schovancova, Jaroslava; Schramm, Steven; Schreyer, Manuel; Schroeder, Christian; Schuh, Natascha; Schultens, Martin Johannes; Schultz-Coulon, Hans-Christian; Schulz, Holger; Schumacher, Markus; Schumm, Bruce; Schune, Philippe; Schwanenberger, Christian; Schwartzman, Ariel; Schwegler, Philipp; Schwemling, Philippe; Schwienhorst, Reinhard; Schwindling, Jerome; Schwindt, Thomas; Schwoerer, Maud; Sciacca, Gianfranco; Scifo, Estelle; Sciolla, Gabriella; Scott, Bill; Scuri, Fabrizio; Scutti, Federico; Searcy, Jacob; Sedov, George; Sedykh, Evgeny; Seidel, Sally; Seiden, Abraham; Seifert, Frank; Seixas, José; Sekhniaidze, Givi; Sekula, Stephen; Selbach, Karoline Elfriede; Seliverstov, Dmitry; Sellers, Graham; Semprini-Cesari, Nicola; Serfon, Cedric; Serin, Laurent; Serkin, Leonid; Serre, Thomas; Seuster, Rolf; Severini, Horst; Sfiligoj, Tina; Sforza, Federico; Sfyrla, Anna; Shabalina, Elizaveta; Shamim, Mansoora; Shan, Lianyou; Shang, Ruo-yu; Shank, James; Shapiro, Marjorie; Shatalov, Pavel; Shaw, Kate; Shehu, Ciwake Yusufu; Sherwood, Peter; Shi, Liaoshan; Shimizu, Shima; Shimmin, Chase Owen; Shimojima, Makoto; Shiyakova, Mariya; Shmeleva, Alevtina; Shochet, Mel; Short, Daniel; Shrestha, Suyog; Shulga, Evgeny; Shupe, Michael; Shushkevich, Stanislav; Sicho, Petr; Sidiropoulou, Ourania; Sidorov, Dmitri; Sidoti, Antonio; Siegert, Frank; Sijacki, Djordje; Silva, José; Silver, Yiftah; Silverstein, Daniel; Silverstein, Samuel; Simak, Vladislav; Simard, Olivier; Simic, Ljiljana; Simion, Stefan; Simioni, Eduard; Simmons, Brinick; Simoniello, Rosa; Simonyan, Margar; Sinervo, Pekka; Sinev, Nikolai; Sipica, Valentin; Siragusa, Giovanni; Sircar, Anirvan; Sisakyan, Alexei; Sivoklokov, Serguei; Sjölin, Jörgen; Sjursen, Therese; Skottowe, Hugh Philip; Skovpen, Kirill; Skubic, Patrick; Slater, Mark; Slavicek, Tomas; Sliwa, Krzysztof; Smakhtin, Vladimir; Smart, Ben; Smestad, Lillian; Smirnov, Sergei; Smirnov, Yury; Smirnova, Lidia; Smirnova, Oxana; Smith, Kenway; Smizanska, Maria; Smolek, Karel; Snesarev, Andrei; Snidero, Giacomo; Snyder, Scott; Sobie, Randall; Socher, Felix; Soffer, Abner; Soh, Dart-yin; Solans, Carlos; Solar, Michael; Solc, Jaroslav; Soldatov, Evgeny; Soldevila, Urmila; Solfaroli Camillocci, Elena; Solodkov, Alexander; Soloshenko, Alexei; Solovyanov, Oleg; Solovyev, Victor; Sommer, Philip; Song, Hong Ye; Soni, Nitesh; Sood, Alexander; Sopczak, Andre; Sopko, Bruno; Sopko, Vit; Sorin, Veronica; Sosebee, Mark; Soualah, Rachik; Soueid, Paul; Soukharev, Andrey; South, David; Spagnolo, Stefania; Spanò, Francesco; Spearman, William Robert; Spettel, Fabian; Spighi, Roberto; Spigo, Giancarlo; Spousta, Martin; Spreitzer, Teresa; Spurlock, Barry; St Denis, Richard Dante; Staerz, Steffen; Stahlman, Jonathan; Stamen, Rainer; Stanecka, Ewa; Stanek, Robert; Stanescu, Cristian; Stanescu-Bellu, Madalina; Stanitzki, Marcel Michael; Stapnes, Steinar; Starchenko, Evgeny; Stark, Jan; Staroba, Pavel; Starovoitov, Pavel; Staszewski, Rafal; Stavina, Pavel; Steinberg, Peter; Stelzer, Bernd; Stelzer, Harald Joerg; Stelzer-Chilton, Oliver; Stenzel, Hasko; Stern, Sebastian; Stewart, Graeme; Stillings, Jan Andre; Stockton, Mark; Stoebe, Michael; Stoicea, Gabriel; Stolte, Philipp; Stonjek, Stefan; Stradling, Alden; Straessner, Arno; Stramaglia, Maria Elena; Strandberg, Jonas; Strandberg, Sara; Strandlie, Are; Strauss, Emanuel; Strauss, Michael; Strizenec, Pavol; Ströhmer, Raimund; Strom, David; Stroynowski, Ryszard; Stucci, Stefania Antonia; Stugu, Bjarne; Styles, Nicholas Adam; Su, Dong; Su, Jun; Subramania, Halasya Siva; Subramaniam, Rajivalochan; Succurro, Antonella; Sugaya, Yorihito; Suhr, Chad; Suk, Michal; Sulin, Vladimir; Sultansoy, Saleh; Sumida, Toshi; Sun, Xiaohu; Sundermann, Jan Erik; Suruliz, Kerim; Susinno, Giancarlo; Sutton, Mark; Suzuki, Yu; Svatos, Michal; Swedish, Stephen; Swiatlowski, Maximilian; Sykora, Ivan; Sykora, Tomas; Ta, Duc; Taccini, Cecilia; Tackmann, Kerstin; Taenzer, Joe; Taffard, Anyes; Tafirout, Reda; Taiblum, Nimrod; Takahashi, Yuta; Takai, Helio; Takashima, Ryuichi; Takeda, Hiroshi; Takeshita, Tohru; Takubo, Yosuke; Talby, Mossadek; Talyshev, Alexey; Tam, Jason; Tan, Kong Guan; Tanaka, Junichi; Tanaka, Reisaburo; Tanaka, Satoshi; Tanaka, Shuji; Tanasijczuk, Andres Jorge; Tannenwald, Benjamin Bordy; Tannoury, Nancy; Tapprogge, Stefan; Tarem, Shlomit; Tarrade, Fabien; Tartarelli, Giuseppe Francesco; Tas, Petr; Tasevsky, Marek; Tashiro, Takuya; Tassi, Enrico; Tavares Delgado, Ademar; Tayalati, Yahya; Taylor, Frank; Taylor, Geoffrey; Taylor, Wendy; Teischinger, Florian Alfred; Teixeira Dias Castanheira, Matilde; Teixeira-Dias, Pedro; Temming, Kim Katrin; Ten Kate, Herman; Teng, Ping-Kun; Teoh, Jia Jian; Terada, Susumu; Terashi, Koji; Terron, Juan; Terzo, Stefano; Testa, Marianna; Teuscher, Richard; Therhaag, Jan; Theveneaux-Pelzer, Timothée; Thomas, Juergen; Thomas-Wilsker, Joshuha; Thompson, Emily; Thompson, Paul; Thompson, Peter; Thompson, Stan; Thomsen, Lotte Ansgaard; Thomson, Evelyn; Thomson, Mark; Thong, Wai Meng; Thun, Rudolf; Tian, Feng; Tibbetts, Mark James; Tikhomirov, Vladimir; Tikhonov, Yury; Timoshenko, Sergey; Tiouchichine, Elodie; Tipton, Paul; Tisserant, Sylvain; Todorov, Theodore; Todorova-Nova, Sharka; Toggerson, Brokk; Tojo, Junji; Tokár, Stanislav; Tokushuku, Katsuo; Tollefson, Kirsten; Tomlinson, Lee; Tomoto, Makoto; Tompkins, Lauren; Toms, Konstantin; Topilin, Nikolai; Torrence, Eric; Torres, Heberth; Torró Pastor, Emma; Toth, Jozsef; Touchard, Francois; Tovey, Daniel; Tran, Huong Lan; Trefzger, Thomas; Tremblet, Louis; Tricoli, Alessandro; Trigger, Isabel Marian; Trincaz-Duvoid, Sophie; Tripiana, Martin; Triplett, Nathan; Trischuk, William; Trocmé, Benjamin; Troncon, Clara; Trottier-McDonald, Michel; Trovatelli, Monica; True, Patrick; Trzebinski, Maciej; Trzupek, Adam; Tsarouchas, Charilaos; Tseng, Jeffrey; Tsiareshka, Pavel; Tsionou, Dimitra; Tsipolitis, Georgios; Tsirintanis, Nikolaos; Tsiskaridze, Shota; Tsiskaridze, Vakhtang; Tskhadadze, Edisher; Tsukerman, Ilya; Tsulaia, Vakhtang; Tsuno, Soshi; Tsybychev, Dmitri; Tudorache, Alexandra; Tudorache, Valentina; Tuna, Alexander Naip; Tupputi, Salvatore; Turchikhin, Semen; Turecek, Daniel; Turk Cakir, Ilkay; Turra, Ruggero; Tuts, Michael; Tykhonov, Andrii; Tylmad, Maja; Tyndel, Mike; Uchida, Kirika; Ueda, Ikuo; Ueno, Ryuichi; Ughetto, Michael; Ugland, Maren; Uhlenbrock, Mathias; Ukegawa, Fumihiko; Unal, Guillaume; Undrus, Alexander; Unel, Gokhan; Ungaro, Francesca; Unno, Yoshinobu; Urbaniec, Dustin; Urquijo, Phillip; Usai, Giulio; Usanova, Anna; Vacavant, Laurent; Vacek, Vaclav; Vachon, Brigitte; Valencic, Nika; Valentinetti, Sara; Valero, Alberto; Valery, Loic; Valkar, Stefan; Valladolid Gallego, Eva; Vallecorsa, Sofia; Valls Ferrer, Juan Antonio; Van Den Wollenberg, Wouter; Van Der Deijl, Pieter; van der Geer, Rogier; van der Graaf, Harry; Van Der Leeuw, Robin; van der Ster, Daniel; van Eldik, Niels; van Gemmeren, Peter; Van Nieuwkoop, Jacobus; van Vulpen, Ivo; van Woerden, Marius Cornelis; Vanadia, Marco; Vandelli, Wainer; Vanguri, Rami; Vaniachine, Alexandre; Vankov, Peter; Vannucci, Francois; Vardanyan, Gagik; Vari, Riccardo; Varnes, Erich; Varol, Tulin; Varouchas, Dimitris; Vartapetian, Armen; Varvell, Kevin; Vazeille, Francois; Vazquez Schroeder, Tamara; Veatch, Jason; Veloso, Filipe; Veneziano, Stefano; Ventura, Andrea; Ventura, Daniel; Venturi, Manuela; Venturi, Nicola; Venturini, Alessio; Vercesi, Valerio; Verducci, Monica; Verkerke, Wouter; Vermeulen, Jos; Vest, Anja; Vetterli, Michel; Viazlo, Oleksandr; Vichou, Irene; Vickey, Trevor; Vickey Boeriu, Oana Elena; Viehhauser, Georg; Viel, Simon; Vigne, Ralph; Villa, Mauro; Villaplana Perez, Miguel; Vilucchi, Elisabetta; Vincter, Manuella; Vinogradov, Vladimir; Virzi, Joseph; Vivarelli, Iacopo; Vives Vaque, Francesc; Vlachos, Sotirios; Vladoiu, Dan; Vlasak, Michal; Vogel, Adrian; Vogel, Marcelo; Vokac, Petr; Volpi, Guido; Volpi, Matteo; von der Schmitt, Hans; von Radziewski, Holger; von Toerne, Eckhard; Vorobel, Vit; Vorobev, Konstantin; Vos, Marcel; Voss, Rudiger; Vossebeld, Joost; Vranjes, Nenad; Vranjes Milosavljevic, Marija; Vrba, Vaclav; Vreeswijk, Marcel; Vu Anh, Tuan; Vuillermet, Raphael; Vukotic, Ilija; Vykydal, Zdenek; Wagner, Peter; Wagner, Wolfgang; Wahlberg, Hernan; Wahrmund, Sebastian; Wakabayashi, Jun; Walder, James; Walker, Rodney; Walkowiak, Wolfgang; Wall, Richard; Waller, Peter; Walsh, Brian; Wang, Chao; Wang, Chiho; Wang, Fuquan; Wang, Haichen; Wang, Hulin; Wang, Jike; Wang, Jin; Wang, Kuhan; Wang, Rui; Wang, Song-Ming; Wang, Tan; Wang, Xiaoxiao; Wanotayaroj, Chaowaroj; Warburton, Andreas; Ward, Patricia; Wardrope, David Robert; Warsinsky, Markus; Washbrook, Andrew; Wasicki, Christoph; Watkins, Peter; Watson, Alan; Watson, Ian; Watson, Miriam; Watts, Gordon; Watts, Stephen; Waugh, Ben; Webb, Samuel; Weber, Michele; Weber, Stefan Wolf; Webster, Jordan S; Weidberg, Anthony; Weigell, Philipp; Weinert, Benjamin; Weingarten, Jens; Weiser, Christian; Weits, Hartger; Wells, Phillippa; Wenaus, Torre; Wendland, Dennis; Weng, Zhili; Wengler, Thorsten; Wenig, Siegfried; Wermes, Norbert; Werner, Matthias; Werner, Per; Wessels, Martin; Wetter, Jeffrey; Whalen, Kathleen; White, Andrew; White, Martin; White, Ryan; White, Sebastian; Whiteson, Daniel; Wicke, Daniel; Wickens, Fred; Wiedenmann, Werner; Wielers, Monika; Wienemann, Peter; Wiglesworth, Craig; Wiik-Fuchs, Liv Antje Mari; Wijeratne, Peter Alexander; Wildauer, Andreas; Wildt, Martin Andre; Wilkens, Henric George; Will, Jonas Zacharias; Williams, Hugh; Williams, Sarah; Willis, Christopher; Willocq, Stephane; Wilson, Alan; Wilson, John; Wingerter-Seez, Isabelle; Winklmeier, Frank; Winter, Benedict Tobias; Wittgen, Matthias; Wittig, Tobias; Wittkowski, Josephine; Wollstadt, Simon Jakob; Wolter, Marcin Wladyslaw; Wolters, Helmut; Wosiek, Barbara; Wotschack, Jorg; Woudstra, Martin; Wozniak, Krzysztof; Wright, Michael; Wu, Mengqing; Wu, Sau Lan; Wu, Xin; Wu, Yusheng; Wulf, Evan; Wyatt, Terry Richard; Wynne, Benjamin; Xella, Stefania; Xiao, Meng; Xu, Da; Xu, Lailin; Yabsley, Bruce; Yacoob, Sahal; Yamada, Miho; Yamaguchi, Hiroshi; Yamaguchi, Yohei; Yamamoto, Akira; Yamamoto, Kyoko; Yamamoto, Shimpei; Yamamura, Taiki; Yamanaka, Takashi; Yamauchi, Katsuya; Yamazaki, Yuji; Yan, Zhen; Yang, Haijun; Yang, Hongtao; Yang, Un-Ki; Yang, Yi; Yanush, Serguei; Yao, Liwen; Yao, Weiming; Yasu, Yoshiji; Yatsenko, Elena; Yau Wong, Kaven Henry; Ye, Jingbo; Ye, Shuwei; Yen, Andy L; Yildirim, Eda; Yilmaz, Metin; Yoosoofmiya, Reza; Yorita, Kohei; Yoshida, Rikutaro; Yoshihara, Keisuke; Young, Charles; Young, Christopher John; Youssef, Saul; Yu, David Ren-Hwa; Yu, Jaehoon; Yu, Jiaming; Yu, Jie; Yuan, Li; Yurkewicz, Adam; Yusuff, Imran; Zabinski, Bartlomiej; Zaidan, Remi; Zaitsev, Alexander; Zaman, Aungshuman; Zambito, Stefano; Zanello, Lucia; Zanzi, Daniele; Zeitnitz, Christian; Zeman, Martin; Zemla, Andrzej; Zengel, Keith; Zenin, Oleg; Ženiš, Tibor; Zerwas, Dirk; Zevi della Porta, Giovanni; Zhang, Dongliang; Zhang, Fangzhou; Zhang, Huaqiao; Zhang, Jinlong; Zhang, Lei; Zhang, Xueyao; Zhang, Zhiqing; Zhao, Zhengguo; Zhemchugov, Alexey; Zhong, Jiahang; Zhou, Bing; Zhou, Lei; Zhou, Ning; Zhu, Cheng Guang; Zhu, Hongbo; Zhu, Junjie; Zhu, Yingchun; Zhuang, Xuai; Zhukov, Konstantin; Zibell, Andre; Zieminska, Daria; Zimine, Nikolai; Zimmermann, Christoph; Zimmermann, Robert; Zimmermann, Simone; Zimmermann, Stephanie; Zinonos, Zinonas; Ziolkowski, Michael; Zobernig, Georg; Zoccoli, Antonio; zur Nedden, Martin; Zurzolo, Giovanni; Zutshi, Vishnu; Zwalinski, Lukasz

2014-09-15

A novel technique to identify and split clusters created by multiple charged particles in the ATLAS pixel detector using a set of artificial neural networks is presented. Such merged clusters are a common feature of tracks originating from highly energetic objects, such as jets. Neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. This technique replaces the former clustering approach based on a connected component analysis and charge interpolation. The performance of the neural network splitting technique is quantified using data from proton-proton collisions at the LHC collected by the ATLAS detector in 2011 and from Monte Carlo simulations. This technique reduces the number of clusters shared between tracks in highly energetic jets by up to a factor of three. It also provides more precise position and error estimates of the clusters in both the transverse and longitudinal impact parameter resolution.

Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

Energy Technology Data Exchange (ETDEWEB)

Zorzi, N. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy)]. E-mail: zorzi@itc.it; Bisogni, M.G. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Boscardin, M. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Dalla Betta, G.-F. [Dipartimento di Informatica e Telecomunicazioni, Universita di Trento, Via Sommarive 14, I-38050 Povo (Trento) (Italy); Gregori, P. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Novelli, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Piemonte, C. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Quattrocchi, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Ronchin, S. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Rosso, V. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy)

2005-07-01

Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 {mu}m thick silicon wafers adopting a double side n{sup +}-on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n{sup +}-pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances.

Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

International Nuclear Information System (INIS)

Zorzi, N.; Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.-F.; Gregori, P.; Novelli, M.; Piemonte, C.; Quattrocchi, M.; Ronchin, S.; Rosso, V.

2005-01-01

Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 μm thick silicon wafers adopting a double side n + -on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n + -pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances

The Phase-2 ATLAS ITk Pixel Upgrade

CERN Document Server

Benoit, Mathieu; The ATLAS collaboration

2017-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The innermost portion of the ITk will consist of a pixel detector with stave-like support structures in the most central region and ring-shaped supports in the endcap regions; there may also be novel inclined support structures in the barrel-endcap overlap regions. The new detector could have as much as 14 m2 of sensitive silicon. Support structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide. The ITk will be instrumented with new sensors and readout electronics to provide improved tracking performance compared to the current detector. All the module components must be performant enough and robust enough to cope with the expected high particle multiplicity and severe radiation background of the High-Luminosity LHC. Readout...

Overview of the ATLAS Insertable B-Layer (IBL) Project

CERN Document Server

Kagan, M; The ATLAS collaboration

2013-01-01

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade for the Pixel Detector will be the construction of a new pixel layer which is currently under construction and will be installed during the first shutdown of the LHC machine, in 2013-14. The new detector, called the Insertable B-layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe at a radius of 3.3 cm. The IBL required the development of several new technologies to cope with increased radiation and pixel occupancy and also to improve the physics performance through reduction of the pixel size and a more stringent material budget. Two different silicon sensor technologies, planar n-in-n and 3D, will be used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. 32 \

Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

CERN Document Server

Sivasubramaniyan, Sriram

Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

The Phase II ATLAS Pixel Upgrade: The Inner Tracker (ITk)

CERN Document Server

Flick, Tobias; The ATLAS collaboration

2016-01-01

The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m^2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to eta < 3.2 and two to eta < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions. Support...

High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

CERN Document Server

Peric,I et al.

2013-01-01

High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

International Nuclear Information System (INIS)

Savic, N.; Beyer, J.; Rosa, A. La; Macchiolo, A.; Nisius, R.

2016-01-01

In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023–2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more radiation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 μm recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of these modules is investigated at beam tests and the results on edge efficiency will be shown.

Quality Assurance and Functionality Tests on Electrical Components during the ATLAS IBL Production

OpenAIRE

Jentzsch, J

2012-01-01

To improve performance of the ATLAS inner tracker, a fourth Pixel layer, called the Insertable B-layer (IBL), will be installed in 2014 on a new beam pipe. A new read out chip generation, FE-I4, has been developed and two different sensor designs, a rather conventional planar and a 3D design, have been flip chipped to these front ends. New staves holding new stave and module flex circuits have been developed as well. Therefore, a production QA test bench has been established to test all produ...

Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

2002-01-01

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

A review of advances in pixel detectors for experiments with high rate and radiation

Science.gov (United States)

Garcia-Sciveres, Maurice; Wermes, Norbert

2018-06-01

The large Hadron collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the high luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.

The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

CERN Document Server

Giordani, MarioPaolo; The ATLAS collaboration

2016-01-01

Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

ATLAS-TPX: a two-layer pixel detector setup for neutron detection and radiation field characterization

International Nuclear Information System (INIS)

Bergmann, B.; Caicedo, I.; Pospisil, S.; Vykydal, Z.; Leroy, C.

2016-01-01

A two-layer pixel detector setup (ATLAS-TPX), designed for thermal and fast neutron detection and radiation field characterization is presented. It consists of two segmented silicon detectors (256 × 256 pixels, pixel pitch 55 μm, thicknesses 300 μm and 500 μm) facing each other. To enhance the neutron detection efficiency a set of converter layers is inserted in between these detectors. The pixelation and the two-layer design allow a discrimination of neutrons against γs by pattern recognition and against charged particles by using the coincidence and anticoincidence information. The neutron conversion and detection efficiencies are measured in a thermal neutron field and fast neutron fields with energies up to 600 MeV. A Geant4 simulation model is presented, which is validated against the measured detector responses. The reliability of the coincidence and anticoincidence technique is demonstrated and possible applications of the detector setup are briefly outlined.

An Introduction to ATLAS Pixel Detector DAQ and Calibration Software Based on a Year's Work at CERN for the Upgrade from 8 to 13 TeV

CERN Document Server

AUTHOR|(CDS)2094561

An overview is presented of the ATLAS pixel detector Data Acquisition (DAQ) system obtained by the author during a year-long opportunity to work on calibration software for the 2015-16 Layer‑2 upgrade. It is hoped the document will function more generally as an easy entry point for future work on ATLAS pixel detector calibration systems. To begin with, the overall place of ATLAS pixel DAQ within the CERN Large Hadron Collider (LHC), the purpose of the Layer-2 upgrade and the fundamentals of pixel calibration are outlined. This is followed by a brief look at the high level structure and key features of the calibration software. The paper concludes by discussing some difficulties encountered in the upgrade project and how these led to unforeseen alternative enhancements, such as development of calibration “simulation” software allowing the soundness of the ongoing upgrade work to be verified while not all of the actual readout hardware was available for the most comprehensive testing.

Single chip camera active pixel sensor

Science.gov (United States)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Gossip: Gaseous pixels

Science.gov (United States)

Koffeman, E. N.

2007-12-01

Several years ago a revolutionary miniature TPC was developed using a pixel chip with a Micromegas foil spanned over it. To overcome the mechanical stability problems and improve the positioning accuracy while spanning a foil on top of a small readout chip a process has been developed in which a Micromegas-like grid is applied on a CMOS wafer in a post-processing step. This aluminum grid is supported on insulating pillars that are created by etching after the grid has been made. The energy resolution (measured on the absorption of the X-rays from a 55Fe source) was remarkably good. Several geometries have since been tested and we now believe that a Gas On Slimmed Silicon Pixel chip' (Gossip) may be realized. The drift region of such a gaseous pixel detector would be reduced to a millimeter. Such a detector is potentially very radiation hard (SLHC vertexing) but aging and sparking must be eliminated.

Gossip: Gaseous pixels

Energy Technology Data Exchange (ETDEWEB)

Koffeman, E.N. [Nikhef, Kruislaan 409, 1098 SJ Amsterdam (Netherlands)], E-mail: d77@nikhef.nl

2007-12-01

Several years ago a revolutionary miniature TPC was developed using a pixel chip with a Micromegas foil spanned over it. To overcome the mechanical stability problems and improve the positioning accuracy while spanning a foil on top of a small readout chip a process has been developed in which a Micromegas-like grid is applied on a CMOS wafer in a post-processing step. This aluminum grid is supported on insulating pillars that are created by etching after the grid has been made. The energy resolution (measured on the absorption of the X-rays from a {sup 55}Fe source) was remarkably good. Several geometries have since been tested and we now believe that a Gas On Slimmed Silicon Pixel chip' (Gossip) may be realized. The drift region of such a gaseous pixel detector would be reduced to a millimeter. Such a detector is potentially very radiation hard (SLHC vertexing) but aging and sparking must be eliminated.

Gossip: Gaseous pixels

International Nuclear Information System (INIS)

Koffeman, E.N.

2007-01-01

Several years ago a revolutionary miniature TPC was developed using a pixel chip with a Micromegas foil spanned over it. To overcome the mechanical stability problems and improve the positioning accuracy while spanning a foil on top of a small readout chip a process has been developed in which a Micromegas-like grid is applied on a CMOS wafer in a post-processing step. This aluminum grid is supported on insulating pillars that are created by etching after the grid has been made. The energy resolution (measured on the absorption of the X-rays from a 55 Fe source) was remarkably good. Several geometries have since been tested and we now believe that a Gas On Slimmed Silicon Pixel chip' (Gossip) may be realized. The drift region of such a gaseous pixel detector would be reduced to a millimeter. Such a detector is potentially very radiation hard (SLHC vertexing) but aging and sparking must be eliminated

Electrical characterization of thin edgeless N-on-p planar pixel sensors for ATLAS upgrades

International Nuclear Information System (INIS)

Bomben, M; Calderini, G; Chauveau, J; Marchiori, G; Bagolini, A; Boscardin, M; Giacomini, G; Zorzi, N; Bosisio, L; Rosa, A La

2014-01-01

In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulation results, a complete overview of the electrical characterization of the produced devices will be given

Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

International Nuclear Information System (INIS)

Nellist, C.; Dinu, N.; Gkougkousis, E.; Lounis, A.

2015-01-01

The LHC accelerator complex will be upgraded between 2020–2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented

Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

CERN Document Server

INSPIRE-00304438; Gkougkousis, E.; Lounis, A.

2015-01-01

The LHC accelerator complex will be upgraded between 2020-2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented.

Optical readout and control interface for the BTeV pixel vertex detector

CERN Document Server

Vergara-Limon, S; Sheaff, M; Vargas, M A

2002-01-01

Optical links will be used for sending data back and forth from the counting room to the detector in the data acquisition systems for future high energy physics experiments, including ATLAS and CMS in the LHC at CERN (Switzerland) and BTeV at Fermilab (USA). This is because they can be ultra-high speed and are relatively immune to electro-magnetic interference (EMI). The baseline design for the BTeV Pixel Vertex Detector includes two types of optical link, one to control and monitor and the other to read out the hit data from the multi-chip modules on each half-plane of the detector. The design and performance of the first prototype of the Optical Readout and Control Interface for the BTeV Pixel Vertex Detector is described.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

International Nuclear Information System (INIS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S.R.; Stabile, A.

2017-01-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called 'pattern'. Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm 2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

Planar pixel sensors in commercial CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

2015-07-01

For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

The Phase-2 ATLAS ITk Pixel Upgrade

CERN Document Server

Rossi, Leonardo Paolo; The ATLAS collaboration

2018-01-01

The entire tracking system of the ATLAS experiment will be replaced in 2025 during the LHC Phase-II shutdown by an all-silicon detector called the “ITk” (Inner Tracker). The innermost part of ITk will be a pixel detector containing about 12.5m2 of sensitive silicon. The silicon modules are arranged on 5 layers of stave-like support structures in the most central region and ring-shaped supports in the endcap regions covering out to |η| < 4; a mid-eta region (~1 < |η| < ~2) will be occupied by novel inclined support structures which keep the angle of incidence of high-momentum tracks more closely normal to the sensitive silicon. All supports will be based on low mass, highly stable and highly thermally-conductive carbon-based materials cooled by evaporative carbon dioxide flowing in thin-walled titanium pipes. An extensive prototyping programme, including thermal, mechanical and electrical studies, is being carried out on all the types of support structures. The HL-LHC is expected to deliver up t...

A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

International Nuclear Information System (INIS)

Sotiropoulou, C L; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Annovi, A; Beretta, M; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of

Tracking and b-tagging with pixel vertex detector in ATLAS experiment at LHC

International Nuclear Information System (INIS)

Vacavant, L.

1997-06-01

The capability of the ATLAS detector to tag b-jets is studied, using the impact parameter of charged tracks. High b-tagging performance is needed at LHC, especially during the first years of running, in order to see evidence of the Higgs boson if its mass lies between 80 and 120 GeV/c 2 . A pattern-recognition algorithm has been developed for this purpose, using a detailed simulation of the ATLAS inner detector. Track-finding starts from the pixel detector layers. A 'hyper-plane' concept allows the use of a simple tracking algorithm though the complex geometry. High track-finding efficiency and reconstruction quality ensure the discrimination of b-jets from other kinds of jets. After full simulation and reconstruction of H → bb-bar, H → gg, H → uu-bar, H → ss-bar and H → cc-bar events (m H = 100 GeV/c 2 ), the mean rejections achieved against non-b-jets for a 50% b-jet tagging efficiency are as follows: R g =39±5 R u = 60 ± 9 R s = 38 ± 5 R c = 9 ± 1 The analysis of data from the first radiation-hard pixel detector prototypes justifies the potential of these detectors for track-finding and high-precision impact parameter measurement at LHC. (author)

New Generation GridPix: Development and characterisation of pixelated gaseous detectors based on the Timepix3 chip

CERN Document Server

AUTHOR|(CDS)2082958; Hessey, Nigel

Due to the increasing demands of high energy physics experiments there is a need for particle detectors which enable high precision measurements. In this regard, the GridPix detector is a novel detector concept which combines the benefits of a pixel chip with an integrated gas amplification structure. The resulting unit is a detector sensitive to single electrons with a great potential for particle tracking and energy loss measurements. This thesis is focusing on the development of a new generation of GridPix detectors based on the Timepix3 chip, which implements a high resolution Time to Digital Converter (TDC) in each pixel. After an introductory chapter describing the motivation behind GridPix, the manuscript presents the physics of gaseous detectors in chapter 2 along with the gaseous detectors used for particle tracking in chapter 3. Chapters 4 and 5 are focusing on the tracking performance of GridPix detectors. Chapter 4 presents results obtained with a GridPix detector based on a small scale prototy...

Measurements of Ultra-Fast single photon counting chip with energy window and 75 μm pixel pitch with Si and CdTe detectors

International Nuclear Information System (INIS)

Maj, P.; Grybos, P.; Kasinski, K.; Koziol, A.; Krzyzanowska, A.; Kmon, P.; Szczygiel, R.; Zoladz, M.

2017-01-01

Single photon counting pixel detectors become increasingly popular in various 2-D X-ray imaging techniques and scientific experiments mainly in solid state physics, material science and medicine. This paper presents architecture and measurement results of the UFXC32k chip designed in a CMOS 130 nm process. The chip consists of about 50 million transistors and has an area of 9.64 mm × 20.15 mm. The core of the IC is a matrix of 128 × 256 pixels of 75 μm pitch. Each pixel contains a CSA, a shaper with tunable gain, two discriminators with correction circuits and two 14-bit ripple counters operating in a normal mode (with energy window), a long counter mode (one 28-bit counter) and a zero-dead time mode. Gain and noise performance were verified with X-ray radiation and with the chip connected to Si (320 μm thick) and CdTe (750 μ m thick) sensors.

ATLAS IBL operational experience

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00237659; The ATLAS collaboration

2017-01-01

The Insertable B-Layer (IBL) is the inner most pixel layer in the ATLAS experiment, which was installed at 3.3 cm radius from the beam axis in 2014 to improve the tracking performance. To cope with the high radiation and hit occupancy due to proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed for the IBL. After the long shut-down period over 2013 and 2014, the ATLAS experiment started data-taking in May 2015 for Run-2 of the Large Hadron Collider (LHC). The IBL has been operated successfully since the beginning of Run-2 and shows excellent performance with the low dead module fraction, high data-taking efficiency and improved tracking capability. The experience and challenges in the operation of the IBL is described as well as its performance.

Design and evaluation of the IBL BOC for the ATLAS experiment at CERN

Energy Technology Data Exchange (ETDEWEB)

Schroer, Nicolai

2013-02-14

In 2013 during a 20 month long shutdown of the LHC the Pixel Detector of the ATLAS Experiment at CERN will be upgraded by inserting a fourth innermost layer between the beam pipe and the current detector. This so called Insertable B-Layer (IBL) will be constructed with 448 of the new FE-I4 chips to handle the readout of the about 12 million pixels provided by the sensors of this layer. The improved architecture and increased bandwidth of these new readout chips requires new off-detector electronics which were decided to be also backwards compatible to the existing system. Hence the VME card pair establishing the optical interface to front-end and data acquisition (BOC) and managing the data processing and calibration (ROD) have been redesigned for the IBL. In this thesis the redesign of the BOC card is motivated and presented. At first the ATLAS Experiment is described and the need to upgrade the Pixel Detector with a new layer is explained. As the readout chip architecture of the current system has flaws preventing its use for the IBL the new FE-I4 is introduced, and with a look at the current off-detector electronics the need for a redesign of it is justified. Starting with the conceptual planning, the redesign process of the BOC card is presented from hard- and firmware development to testing of the first prototypes. The redesigned BOC is based on modern FPGA technology in conjunction with commercial off-the-shelf optical transceiver modules to provide an integration four times higher than the current system, including the flexibility to adjust to different use cases by simply changing the firmware.

Design and evaluation of the IBL BOC for the ATLAS experiment at CERN

International Nuclear Information System (INIS)

Schroer, Nicolai

2013-01-01

In 2013 during a 20 month long shutdown of the LHC the Pixel Detector of the ATLAS Experiment at CERN will be upgraded by inserting a fourth innermost layer between the beam pipe and the current detector. This so called Insertable B-Layer (IBL) will be constructed with 448 of the new FE-I4 chips to handle the readout of the about 12 million pixels provided by the sensors of this layer. The improved architecture and increased bandwidth of these new readout chips requires new off-detector electronics which were decided to be also backwards compatible to the existing system. Hence the VME card pair establishing the optical interface to front-end and data acquisition (BOC) and managing the data processing and calibration (ROD) have been redesigned for the IBL. In this thesis the redesign of the BOC card is motivated and presented. At first the ATLAS Experiment is described and the need to upgrade the Pixel Detector with a new layer is explained. As the readout chip architecture of the current system has flaws preventing its use for the IBL the new FE-I4 is introduced, and with a look at the current off-detector electronics the need for a redesign of it is justified. Starting with the conceptual planning, the redesign process of the BOC card is presented from hard- and firmware development to testing of the first prototypes. The redesigned BOC is based on modern FPGA technology in conjunction with commercial off-the-shelf optical transceiver modules to provide an integration four times higher than the current system, including the flexibility to adjust to different use cases by simply changing the firmware.

High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

CERN Document Server

Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

2013-01-01

High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

Subpixel mapping and test beam studies with a HV2FEI4v2 CMOS-Sensor-Hybrid Module for the ATLAS inner detector upgrade

Science.gov (United States)

Bisanz, T.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.

2017-08-01

The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33× 125 μm2, while the pixels of the read-out chip have a pitch of 50× 250 μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.

Studio di un algoritmo lineare di ricostruzione analogica della posizione per il rivelatore a pixel di ATLAS

CERN Document Server

Arelli-Maffioli, A; Troncon, C; Lari, T

2007-01-01

A detailed study of spatial resolution of Atlas pixel sensors prototypes was performed. Charge interpolation was used and allowed for a significant improvement with respect to digital resolution. A simplified algorithm for charge interpolation was developed. Its application to both unirradiated and irradiated sensors is presented and discussed.

Simulation of the depletion voltage evolution of the ATLAS Pixel Detector

CERN Document Server

Beyer, Julien-christopher; The ATLAS collaboration

2017-01-01

The ATLAS Pixel detector has been operating since 2010 and consists of hybrid pixel modules where the sensitive elements are planar n-in-n sensors. In order to investigate and predict the evolution of the depletion voltage and of the leakage current in the different layers, a fully analytical implementation of the Hamburg model was derived. The parameters of the model, describing the dependence of the depletion voltage (U_depl) on fluence, temperature and time were tuned with a fit to the available measurements of Udepl in the last years of operation. A particular emphasis is put on the B-Layer, where the highest fluence has been accumulated up to now. A precise input of temperature and radiation dose is generated from the on-module temperature monitoring and the luminosity data. The analysis is then also extended to the Insertable B-Layer (IBL), installed at the end of Run-1, where we expect the fastest evolution of the radiation damage with luminosity, due to its closer position to the interaction point. Di...

Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

CERN Document Server

AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

Overview of the ATLAS Insertable B-Layer (IBL) Project

CERN Document Server

Pohl, D-L; The ATLAS collaboration

2013-01-01

The upgrades for the ATLAS Pixel Detector will be staged in preparation for high luminosity LHC. The first upgrade for the Pixel Detector will be the construction of a new pixel layer which is currently under construction and will be installed during the first shutdown of the LHC machine, in 2013-14. The new detector, called the Insertable B-layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe at a radius of 3.3 cm. The IBL required the development of several new technologies to cope with increased radiation and pixel occupancy and also to improve the physics performance through reduction of the pixel size and a more stringent material budget. Two different silicon sensor technologies, planar n-in-n and 3D, will be used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. 32 FEs with sensors are glued to a light weight carbon-carbon structure which incorporates a titanium cooling tube for a CO2 cooling system. In total th...

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

Science.gov (United States)

Rimoldi, M.

2017-12-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS inner detector

International Nuclear Information System (INIS)

Poley, Luise; Bloch, Ingo; Edwards, Sam

2016-04-01

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). This glue has several disadvantages, which motivated the search for an alternative. This paper presents a study concerning the use of six ultra-violet (UV) cure glues and a glue pad for use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, the thermal conduction and shear strength, thermal cycling, radiation hardness, corrosion resistance and shear strength tests. These investigations led to the exclusion of three UV cure glues as well as the glue pad. Three UV cure glues were found to be possible better alternatives. Results from electrical tests of first prototype modules constructed using these glues are presented.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS inner detector

Energy Technology Data Exchange (ETDEWEB)

Poley, Luise [DESY, Zeuthen (Germany); Humboldt Univ. Berlin (Germany); Bloch, Ingo [DESY, Zeuthen (Germany); Edwards, Sam [Birmingham Univ. (United Kingdom); and others

2016-04-15

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). This glue has several disadvantages, which motivated the search for an alternative. This paper presents a study concerning the use of six ultra-violet (UV) cure glues and a glue pad for use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, the thermal conduction and shear strength, thermal cycling, radiation hardness, corrosion resistance and shear strength tests. These investigations led to the exclusion of three UV cure glues as well as the glue pad. Three UV cure glues were found to be possible better alternatives. Results from electrical tests of first prototype modules constructed using these glues are presented.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS Inner Detector

Science.gov (United States)

Poley, L.; Bloch, I.; Edwards, S.; Friedrich, C.; Gregor, I.-M.; Jones, T.; Lacker, H.; Pyatt, S.; Rehnisch, L.; Sperlich, D.; Wilson, J.

2016-05-01

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive used initially between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). However, this glue has several disadvantages, which motivated the search for an alternative. This paper presents a study of six ultra-violet (UV) cure glues and a glue pad for possible use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, thermal conduction and shear strength. Samples were thermally cycled, radiation hardness and corrosion resistance were also determined. These investigations led to the exclusion of three UV cure glues as well as the glue pad. Three UV cure glues were found to be possible better alternatives than silver loaded glue. Results from electrical tests of first prototype modules constructed using these glues are presented.

Alternative glues for the production of ATLAS silicon strip modules for the Phase-II upgrade of the ATLAS Inner Detector

International Nuclear Information System (INIS)

Poley, L.; Bloch, I.; Friedrich, C.; Gregor, I.-M.; Edwards, S.; Pyatt, S.; Wilson, J.; Jones, T.; Lacker, H.; Rehnisch, L.; Sperlich, D.

2016-01-01

The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive used initially between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). However, this glue has several disadvantages, which motivated the search for an alternative. This paper presents a study of six ultra-violet (UV) cure glues and a glue pad for possible use in the assembly of silicon strip detector modules for the ATLAS upgrade. Trials were carried out to determine the ease of use, thermal conduction and shear strength. Samples were thermally cycled, radiation hardness and corrosion resistance were also determined. These investigations led to the exclusion of three UV cure glues as well as the glue pad. Three UV cure glues were found to be possible better alternatives than silver loaded glue. Results from electrical tests of first prototype modules constructed using these glues are presented.

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

Science.gov (United States)

Vigani, L.; Bortoletto, D.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-02-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

CERN Document Server

Vigani, L.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-01-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

CERN Document Server

INSPIRE-00052711; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

2016-01-01

In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

Energy Technology Data Exchange (ETDEWEB)

Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Beccherle, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Pisa (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste (Italy); INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

2016-09-21

In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

Characterization of active CMOS sensors for capacitively coupled pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

2015-07-01

Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

First experiences with the ATLAS pixel detector control system at the combined test beam 2004

International Nuclear Information System (INIS)

Imhaeuser, Martin; Becks, Karl-Heinz; Henss, Tobias; Kersten, Susanne; Maettig, Peter; Schultes, Joachim

2006-01-01

Detector control systems (DCS) include the readout, control and supervision of hardware devices as well as the monitoring of external systems like cooling system and the processing of control data. The implementation of such a system in the final experiment also has to provide the communication with the trigger and data acquisition system (TDAQ). In addition, conditions data which describe the status of the pixel detector modules and their environment must be logged and stored in a common LHC wide database system. At the combined test beam all ATLAS subdetectors were operated together for the first time over a longer period. To ensure the functionality of the pixel detector, a control system was set up. We describe the architecture chosen for the pixel DCS, the interfaces to hardware devices, the interfaces to the users and the performance of our system. The embedding of the DCS in the common infrastructure of the combined test beam and also its communication with surrounding systems will be discussed in some detail

Test su fascio di prototipi del rivelatore a pixel per l'esperimento ATLAS

CERN Document Server

Matera, Andrea; Andreazza, A

2005-01-01

Silicon pixel detectors, developed to meet LHC requirements, were tested within the ATLAS collaboration in the H8 beam at CERN. Different sensor designs were studied using various versions of front end electronics developed during the R&D process. In this thesis a detailed experimental study of the overall performance of both irradiated and unirradiated detectors is presented, with special enphasis on efficiency, charge collection and spatial resolution. For the first time their dependence on timewalk is carefully investigated. Possible solutions to avoid spatial resolution deterioration due to timewalk are presented and discussed.

Quality assurance and functionality tests on electrical components during the ATLAS IBL production

International Nuclear Information System (INIS)

Jentzsch, J

2013-01-01

To improve performance of the ATLAS inner tracker, a fourth Pixel layer, called the Insertable B-layer (IBL), will be installed in 2014 on a new beam pipe. A new read out chip generation, FE-I4, has been developed and two different sensor designs, a rather conventional planar and a 3D design, have been flip chipped to these front ends. New staves holding new stave and module flex circuits have been developed as well. Therefore, a production QA test bench has been established to test all production staves before integration with the new beam pipe. This setup combines former ATLAS Pixel services and a new readout system, namely the RCE (Reconfigurable Cluster Element) system developed at SLAC. With this setup all production staves will be tested to ensure the installation of only those staves which fulfill the IBL criteria. Quality assurance measurements under cleanroom conditions, including temperature and humidity control, are performed on the individual components during the various production steps of the IBL, namely connectivity as well as electrical tests and signal probing on individual parts and assembled subsystems. The pre-assembly QC procedures, the capabilities of the stave qualification setup, and recent results from testing a prototype stave are presented and discussed.

Quality assurance and functionality tests on electrical components during the ATLAS IBL production

Science.gov (United States)

Jentzsch, J.

2013-02-01

To improve performance of the ATLAS inner tracker, a fourth Pixel layer, called the Insertable B-layer (IBL), will be installed in 2014 on a new beam pipe. A new read out chip generation, FE-I4, has been developed and two different sensor designs, a rather conventional planar and a 3D design, have been flip chipped to these front ends. New staves holding new stave and module flex circuits have been developed as well. Therefore, a production QA test bench has been established to test all production staves before integration with the new beam pipe. This setup combines former ATLAS Pixel services and a new readout system, namely the RCE (Reconfigurable Cluster Element) system developed at SLAC. With this setup all production staves will be tested to ensure the installation of only those staves which fulfill the IBL criteria. Quality assurance measurements under cleanroom conditions, including temperature and humidity control, are performed on the individual components during the various production steps of the IBL, namely connectivity as well as electrical tests and signal probing on individual parts and assembled subsystems. The pre-assembly QC procedures, the capabilities of the stave qualification setup, and recent results from testing a prototype stave are presented and discussed.

A 3D photograph with 92 million pixels for tagging particles

CERN Multimedia

Antonella Del Rosso

2013-01-01

Where was a given particle born? How can we tag it precisely enough to be able to then follow it along its track and through its decays? This is the job of the pixel detector installed at the heart of the ATLAS detector, only centimeters away from the LHC collisions. In order to improve its identification and tagging capabilities, the ATLAS collaboration has recently taken a big step towards the completion of the upgrade of its Pixel detector, which will include the insertion of a brand-new layer of 12 million pixels.   The 7 metre long beryllium beam pipe inserted in the carbon-fibre positioning tool is being prepared ready for the new innermost layer of the Pixel detector to be mounted. Photo: ATLAS Collaboration. With its three layers and 80 million channels concentrated in 2.2 square metres, the ATLAS pixel detector was already the world’s largest pixel-based system used in particle physics. Its excellent performance was instrumental in the discovery of the Higgs boson in July ...

A passive CMOS pixel sensor for the high luminosity LHC

Energy Technology Data Exchange (ETDEWEB)

Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

2016-07-01

The high luminosity upgrade for the Large Hadron Collider at CERN requires a new inner tracking detector for the ATLAS experiment. About 200 m{sup 2} of silicon detectors are needed demanding new, low cost hybridization- and sensor technologies. One promising approach is to use commercial CMOS technologies to produce the passive sensor for a hybrid pixel detector design. In this talk a fully functional prototype of a 300 μm thick, backside biased CMOS pixel sensor in 150 nm LFoundry technology is presented. The sensor is bump bonded to the ATLAS FE-I4 with AC and DC coupled pixels. Results like leakage current, noise performance, and charge collection efficiency are presented and compared to the actual ATLAS pixel sensor design.

Gas pixel detectors

International Nuclear Information System (INIS)

Bellazzini, R.; Baldini, L.; Brez, A.; Cavalca, F.; Latronico, L.; Massai, M.M.; Minuti, M.; Omodei, N.; Pesce-Rollins, M.; Sgro, C.; Spandre, G.; Costa, E.; Soffitta, P.

2007-01-01

With the Gas Pixel Detector (GPD), the class of micro-pattern gas detectors has reached a complete integration between the gas amplification structure and the read-out electronics. To obtain this goal, three generations of application-specific integrated circuit of increased complexity and improved functionality has been designed and fabricated in deep sub-micron CMOS technology. This implementation has allowed manufacturing a monolithic device, which realizes, at the same time, the pixelized charge-collecting electrode and the amplifying, shaping and charge measuring front-end electronics of a GPD. A big step forward in terms of size and performances has been obtained in the last version of the 0.18 μm CMOS analog chip, where over a large active area of 15x15 mm 2 a very high channel density (470 pixels/mm 2 ) has been reached. On the top metal layer of the chip, 105,600 hexagonal pixels at 50 μm pitch have been patterned. The chip has customable self-trigger capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way, by limiting the output signal to only those pixels belonging to the region of interest, it is possible to reduce significantly the read-out time and data volume. In-depth tests performed on a GPD built up by coupling this device to a fine pitch (50 μm) gas electron multiplier are reported. Matching of the gas amplification and read-out pitch has let to obtain optimal results. A possible application of this detector for X-ray polarimetry of astronomical sources is discussed

32 x 16 CMOS smart pixel array for optical interconnects

Science.gov (United States)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Development of edgeless n-on-p planar pixel sensors for future ATLAS upgrades

Energy Technology Data Exchange (ETDEWEB)

Bomben, Marco, E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Bagolini, Alvise; Boscardin, Maurizio [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, Luciano [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, and INFN Sez. di Pisa, Pisa (Italy); Chauveau, Jacques [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Giacomini, Gabriele [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, Alessandro [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Zorzi, Nicola [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

2013-06-01

The development of n-on-p “edgeless” planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the “active edge” technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of 1×10{sup 15}n{sub eq}/cm{sup 2} comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb{sup −1}) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach. -- Highlights: ► We conceive n-on-p edgeless planar silicon sensors. ► These sensors are aimed at the Phase-II of the ATLAS experiment. ► Simulations show sensors can be operated well in overdepletion. ► Simulations show the sensor capability to collect charge at the periphery. ► Simulations prove the above statements to be true even after irradiation.

The ATLAS IBL BOC Prototype Evaluation

CERN Document Server

Schroer, N; The ATLAS collaboration; Bruni, G; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Neumann, M; Polini, A; Rizzi, M; Travaglini, R; Zannoli, S; Zoccoli, A; Bruschi, M; Dantone, I; Falchieri, D; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Heim, T

2012-01-01

In 2013 an additional layer, the Insertable B-Layer (IBL) will be added to the pixel detector of the ATLAS experiment at the LHC at CERN. For this fourth and innermost layer 448 newly developed pixel sensor readout chips (FE-I4) are used which will provide data from about 12 million pixel. For the readout of the IBL new off-detector electronic components are needed as the FE-I4s feature an increased readout bandwidth which can not be handled by the current system. To provide a degree of backward compatibility the new system will keep the structure of VME card pairs: The back of crate card (BOC) establishes the optical interfaces to the detector front end as well as to the read out system (ROS) while the read out driver (ROD) manages data processing and calibration. Both cards, the BOC and the ROD, have been redesigned and feature modern FPGA technology, yielding an integration four times higher than the current system. Regarding the new BOC this is achieved by replacing custom made optical and electrical (e.g...

A study of SEU-tolerant latches for the RD53A chip

CERN Document Server

Fougeron, Denis

2018-01-01

The RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process has been adopted in order to satisfy the high level of integration requirement. However, the SEU immunity should be carefully considered for a deep submicron process like the 65 nm. Indeed, the device dimensions are small and the capacitance of the storage nodes becomes very low. A chip prototype including different SEU tolerant structures was designed in a 65 nm technology. Several proton irradiation tests were carried out in order to estimate the SEU tolerance of the proposed structures and the level of improvement comparing with a standard architecture.

X-ray imaging with photon counting hybrid semiconductor pixel detectors

CERN Document Server

Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

1999-01-01

Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

Science.gov (United States)

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

Pixelized M-pi-n CdTe detector coupled to Medipix2 readout chip

CERN Document Server

Kalliopuska, J; Penttila, R; Andersson, H; Nenonen, S; Gadda, A; Pohjonen, H; Vanttajac, I; Laaksoc, P; Likonen, J

2011-01-01

We have realized a simple method for patterning an M-pi-n CdTe diode with a deeply diffused pn-junction, such as indium anode on CdTe. The method relies on removing the semiconductor material on the anode-side of the diode until the physical junction has been reached. The pixelization of the p-type CdTe diode with an indium anode has been demonstrated by patterning perpendicular trenches with a high precision diamond blade and pulsed laser. Pixelization or microstrip pattering can be done on both sides of the diode, also on the cathode-side to realize double sided detector configuration. The article compares the patterning quality of the diamond blade process, pulsed pico-second and femto-second lasers processes. Leakage currents and inter-strip resistance have been measured and are used as the basis of the comparison. Secondary ion mass spectrometry (SIMS) characterization has been done for a diode to define the pn-junction depth and to see the effect of the thermal loads of the flip-chip bonding process. Th...

Operational Experience with and Performance of the ATLAS Pixel Detector at the Large Hadron Collider

CERN Document Server

Grummer, Aidan; The ATLAS collaboration

2018-01-01

The operational experience and requirements to ensure optimum data quality and data taking efficiency with the 4-layer ATLAS Pixel Detector are discussed. The detector has undergone significant hardware and software upgrades to meet the challenges imposed by the fact that the Large Hadron Collider is exceeding expectations for instantaneous luminosity by more than a factor of two (more than $2 \\times 10^{34}$ cm$^{-2}$ s$^{-1}$). Emphasizing radiation damage effects, the key status and performance metrics are described.

Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

CERN Document Server

INSPIRE-00218480

2016-01-01

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

Overview of the ATLAS Insertable B-Layer (IBL) Project

CERN Document Server

Kagan, M; The ATLAS collaboration

2014-01-01

The first upgrade for the Pixel Detector will be a new pixel layer which is currently under construction and will be installed during the first shutdown of the LHC machine, in 2013-14. The new detector, called the Insertable B-layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe. Two different silicon sensor technologies, planar n-in-n and 3D, will be used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. A production quality control test bench was setup in the ATLAS inner detector assembly clean room to verify and rate the performance of the detector elements before integration around the beam pipe. An overview of the IBL project, of the module design, the qualification for these sensor technologies, the integration quality control setups and recent results in the construction of this full scale new concept detector is discussed.

Overview of the ATLAS Insertable B-Layer (IBL) Project

Science.gov (United States)

Kagan, M. A.

2014-06-01

The first upgrade for the Pixel Detector will be a new pixel layer which is currently under construction and will be installed during the first shutdown of the LHC machine, in 2013-14. The new detector, called the Insertable B-layer (IBL), will be installed between the existing Pixel Detector and a new, smaller radius beam-pipe. Two different silicon sensor technologies, planar n-in-n and 3D, will be used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. A production quality control test bench was set up in the ATLAS inner detector assembly clean room to verify and rate the performance of the detector elements before integration around the beam-pipe. An overview of the IBL project, of the module design, the qualification for these sensor technologies, the integration quality control setups and recent results in the construction of this full scale new concept detector is discussed.

Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC

CERN Document Server

Karagounis, M

2008-01-01

Motivated by the upcoming upgrade of the ATLAS hybrid pixel detector, a new Front-End (FE) IC is being developed in a 130nm technology to face the tightened requirements of the upgraded pixel system. The main design goals are the reduction of material and a decrease in power consumption combined with the capability to handle the higher hit rates that will result from the upgraded machine. New technology features like the higher integration density for digital circuits, better radiation tolerance and Triple-Well transistors are used for optimization and the implementation of new concepts. A description of the ongoing design work is given, focusing more on the analog part and peripheral design blocks.

Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

CERN Document Server

Posch, C

2002-01-01

Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

Performance of capacitively coupled active pixel sensors in 180 nm HV-CMOS technology after irradiation to HL-LHC fluences

International Nuclear Information System (INIS)

Feigl, S

2014-01-01

In this ATLAS upgrade R and D project, we explore the concept of using a deep-submicron HV-CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the basic design of the HV2FEI4 test ASIC, results after irradiation with X-rays to 862 Mrad and neutrons up to 10 16 (1 MeV n eq )/cm 2 will be presented. Finally, a brief outlook on further development plans is given

Étude des détecteurs planaires pixels durcis aux radiations pour la mise à jour du détecteur de vertex d'ATLAS

CERN Document Server

Benoit, Mathieu

In this work, is presented a study, using TCAD simulation, of the possible methods of designing of a planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure,a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor's process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain ...

A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Gaioni, L., E-mail: luigi.gaioni@unibg.it [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Braga, D.; Christian, D.C.; Deptuch, G.; Fahim, F. [Fermi National Accelerator Laboratory, Batavia IL (United States); Nodari, B. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Centre National de Recherche Scientifique, APC/IN2P3, Paris (France); Ratti, L. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Zimmerman, T. [Fermi National Accelerator Laboratory, Batavia IL (United States)

2017-02-11

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10{sup 34} cm{sup −2} s{sup −1} in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

Development of edgeless silicon pixel sensors on p-type substrate for the ATLAS high-luminosity upgrade

Energy Technology Data Exchange (ETDEWEB)

Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste and INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

2014-11-21

In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R and D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

CERN Document Server

Wang, Jinhong; The ATLAS collaboration

2014-01-01

The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon detectors for the Phase-I upgrade of the ATLAS New Small Wheel (NSW) muon detector. Signals from both the sTGC pad and strip detectors will be first read out by the Amplifier-Shaper-Discriminator (ASD) chip designed by the Brookhaven National Laboratory, and then collected and transmitted by a Trigger Data Serializer (TDS) chip at a rate of 4.8 Gbps to other related circuits. The pad-TDS chip checks the presence of pad hits and sends the information together with Bunching Crossing ID to the pad-trigger logic to define roads of interest. The strip-TDS chip collects and buffers strip charge information and transmits a range of strips within the road of interest to the router board located on the rim of the NSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environme...

The ATLAS IBL CO2 Cooling System

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00237783; The ATLAS collaboration; Zwalinski, L.; Bortolin, C.; Vogt, S.; Godlewski, J.; Crespo-Lopez, O.; Van Overbeek, M.; Blaszcyk, T.

2017-01-01

The ATLAS Pixel detector has been equipped with an extra B-layer in the space obtained by a reduced beam pipe. This new pixel detector called the ATLAS Insertable B-Layer (IBL) is installed in 2014 and is operational in the current ATLAS data taking. The IBL detector is cooled with evaporative CO2 and is the first of its kind in ATLAS. The ATLAS IBL CO2 cooling system is designed for lower temperature operation (<-35⁰C) than the previous developed CO2 cooling systems in High Energy Physics experiments. The cold temperatures are required to protect the pixel sensors for the high expected radiation dose up to 550 fb^-1 integrated luminosity.

Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00356268

The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

ISPA (imaging silicon pixel array) experiment

CERN Multimedia

Patrice Loïez

2002-01-01

The bump-bonded silicon pixel detector, developed at CERN by the EP-MIC group, is shown here in its ceramic carrier. Both represent the ISPA-tube anode. The chip features between 1024 (called OMEGA-1) and 8196 (ALICE-1) active pixels.

Analyses of test beam data for the ATLAS upgrade readout chip (ABC130)

Energy Technology Data Exchange (ETDEWEB)

Peschke, Richard [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

2015-07-01

As part of the ATLAS phase II upgrade it is planned to replace the current tracker with an all silicon tracker. The outer part of the new tracker will consist of silicon strip detectors. For the readout of the strip detector a new Analog to Binary Converter chip (ABC130) was designed. The chip is processed in the 130 nm technology. In laboratory measurements the preamplifier of the new ABC130 showed a significant lower gain than expected. From the measurements in the laboratory it was not possible to distinguish if the malfunction is in the preamplifier or in the test circuit. Therefore an unbiased test was mandatory. Among other measurements, one was a test beam campaign at the Stanford Linear Accelerator Collider (SLAC). The result of measurement is shown in the presentation.

Two ATLAS suppliers honoured

CERN Multimedia

2007-01-01

The ATLAS experiment has recognised the outstanding contribution of two firms to the pixel detector. Recipients of the supplier award with Peter Jenni, ATLAS spokesperson, and Maximilian Metzger, CERN Secretary-General.At a ceremony held at CERN on 28 November, the ATLAS collaboration presented awards to two of its suppliers that had produced sensor wafers for the pixel detector. The CiS Institut für Mikrosensorik of Erfurt in Germany has supplied 655 sensor wafers containing a total of 1652 sensor tiles and the firm ON Semiconductor has supplied 515 sensor wafers (1177 sensor tiles) from its foundry at Roznov in the Czech Republic. Both firms have successfully met the very demanding requirements. ATLAS’s huge pixel detector is very complicated, requiring expertise in highly specialised integrated microelectronics and precision mechanics. Pixel detector project leader Kevin Einsweiler admits that when the project was first propo...

The ALICE silicon pixel detector front-end and read-out electronics

CERN Document Server

Kluge, A

2006-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost barrel layers of the ALICE inner tracker system. The SPD includes 120 half staves each of which consists of a linear array of 10 ALICE pixel chips bump bonded to two silicon sensors. Each pixel chip contains 8192 active cells, so the total number of pixel cells in the SPD is ≈107. The tight material budget and the limitation in physical dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. An essential part of the half stave is a low-mass multi-layer flex that carries power, ground, and signals to the pixel chips. Each half stave is read out using a multi-chip module (MCM). The MCM contains three radiation hard ASICs and an 800 Mbit/s custom developed optical link for the data transfer between the detector and the control room. The detector components are less than 3 mm thick. The production of the half-staves and MCMs is currently under way. Test results as well as on overvie...

CMOS foveal image sensor chip

Science.gov (United States)

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

3D silicon sensors: Design, large area production and quality assurance for the ATLAS IBL pixel detector upgrade

Science.gov (United States)

Da Via, Cinzia; Boscardin, Maurizio; Dalla Betta, Gian-Franco; Darbo, Giovanni; Fleta, Celeste; Gemme, Claudia; Grenier, Philippe; Grinstein, Sebastian; Hansen, Thor-Erik; Hasi, Jasmine; Kenney, Chris; Kok, Angela; Parker, Sherwood; Pellegrini, Giulio; Vianello, Elisa; Zorzi, Nicola

2012-12-01

3D silicon sensors, where electrodes penetrate the silicon substrate fully or partially, have successfully been fabricated in different processing facilities in Europe and USA. The key to 3D fabrication is the use of plasma micro-machining to etch narrow deep vertical openings allowing dopants to be diffused in and form electrodes of pin junctions. Similar openings can be used at the sensor's edge to reduce the perimeter's dead volume to as low as ˜4 μm. Since 2009 four industrial partners of the 3D ATLAS R&D Collaboration started a joint effort aimed at one common design and compatible processing strategy for the production of 3D sensors for the LHC Upgrade and in particular for the ATLAS pixel Insertable B-Layer (IBL). In this project, aimed for installation in 2013, a new layer will be inserted as close as 3.4 cm from the proton beams inside the existing pixel layers of the ATLAS experiment. The detector proximity to the interaction point will therefore require new radiation hard technologies for both sensors and front end electronics. The latter, called FE-I4, is processed at IBM and is the biggest front end of this kind ever designed with a surface of ˜4 cm2. The performance of 3D devices from several wafers was evaluated before and after bump-bonding. Key design aspects, device fabrication plans and quality assurance tests during the 3D sensors prototyping phase are discussed in this paper.

3D silicon sensors: Design, large area production and quality assurance for the ATLAS IBL pixel detector upgrade

Energy Technology Data Exchange (ETDEWEB)

Da Via, Cinzia [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester, M13 9PL (United Kingdom); Boscardin, Maurizio [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [DISI, Universita degli Studi di Trento and INFN, Via Sommarive 14, I-38123 Trento (Italy); Darbo, Giovanni [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Fleta, Celeste [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Gemme, Claudia [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Grenier, Philippe [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Grinstein, Sebastian [Institut de Fisica d' Altes Energies (IFAE) and ICREA, Universitat Autonoma de Barcelona (UAB), E-08193 Bellaterra, Barcelona (Spain); Hansen, Thor-Erik [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Hasi, Jasmine; Kenney, Chris [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Kok, Angela [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Parker, Sherwood [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States); Pellegrini, Giulio [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Vianello, Elisa; Zorzi, Nicola [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

2012-12-01

3D silicon sensors, where electrodes penetrate the silicon substrate fully or partially, have successfully been fabricated in different processing facilities in Europe and USA. The key to 3D fabrication is the use of plasma micro-machining to etch narrow deep vertical openings allowing dopants to be diffused in and form electrodes of pin junctions. Similar openings can be used at the sensor's edge to reduce the perimeter's dead volume to as low as {approx}4 {mu}m. Since 2009 four industrial partners of the 3D ATLAS R and D Collaboration started a joint effort aimed at one common design and compatible processing strategy for the production of 3D sensors for the LHC Upgrade and in particular for the ATLAS pixel Insertable B-Layer (IBL). In this project, aimed for installation in 2013, a new layer will be inserted as close as 3.4 cm from the proton beams inside the existing pixel layers of the ATLAS experiment. The detector proximity to the interaction point will therefore require new radiation hard technologies for both sensors and front end electronics. The latter, called FE-I4, is processed at IBM and is the biggest front end of this kind ever designed with a surface of {approx}4 cm{sup 2}. The performance of 3D devices from several wafers was evaluated before and after bump-bonding. Key design aspects, device fabrication plans and quality assurance tests during the 3D sensors prototyping phase are discussed in this paper.

Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

International Nuclear Information System (INIS)

Giacomini, G; Bagolini, A; Boscardin, M; Zorzi, N; Bomben, M; Calderini, G; Chauveau, J; Marchiori, G; Bosisio, L; Rosa, A La

2014-01-01

In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch

Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

CERN Document Server

Giacomini, Gabriele; Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

2014-01-01

In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch.

Status of the CMS Phase I pixel detector upgrade

Energy Technology Data Exchange (ETDEWEB)

Spannagel, S., E-mail: simon.spannagel@desy.de

2016-09-21

A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip.

Status of the CMS Phase I Pixel Detector Upgrade

CERN Document Server

Spannagel, Simon

2016-09-21

A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase~I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip.

Firmware development and testing of the ATLAS IBL Readout Driver card

CERN Document Server

Chen, S; The ATLAS collaboration

2014-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector is inserting an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development focused on migrating and tailoring HDL code blocks from PixelROD to ensure modular compatibility in future ROD upgrades, in which a unified code version will interface with IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path implementation, tested in testbench and on ROD prototypes, will be report...

Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

Energy Technology Data Exchange (ETDEWEB)

Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

2016-09-21

This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

A digital pixel cell for address event representation image convolution processing

Science.gov (United States)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

Prototyping of larger structures for the Phase-II upgrade of the pixel detector of the ATLAS experiment

CERN Document Server

Alvarez Feito, Diego; The ATLAS collaboration

2017-01-01

For the high luminosity era of the Large Hadron Collider (HL-LHC) it is forseen to replace the current inner tracker of the ATLAS experiment with a new detector to cope with the occuring increase in occupancy, bandwidth and radiation damage. It will consist of an inner pixel and outer strip detector aiming to provide tracking coverage up to |η|<4. The layout of the pixel detector is foreseen to consist of five layers of pixel silicon sensor modules in the central region and several ring-shaped layers in the forward region. It results in up to 14 m² of silicon depending on the selected layout. Beside the challenge of radiation hardness and high-rate capable silicon sensors and readout electronics many system aspects have to be considered for a fully functional detector. Both stable and low mass mechanical structures and services are important. Within the collaboration a large effort is started to prototype larger detector structures for both the central and forward region of the detector. The aspect of sy...

ATLAS inner detector: the Run 1 to Run 2 transition, and first experience from Run 2

CERN Document Server

Dobos, Daniel; The ATLAS collaboration

2015-01-01

The ATLAS experiment is equipped with a tracking system, the Inner Detector, built using different technologies, silicon planar sensors (pixel and micro-strip) and gaseous drift- tubes, all embedded in a 2T solenoidal magnetic field. For the LHC Run II, the system has been upgraded; taking advantage of the long showdown, the Pixel Detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm from the beam axis. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point and the increase of Luminosity that LHC will face in Run-2, a new read-out chip within CMOS 130nm and two different silicon sensor pixel technologies (planar and 3D) have been developed. SCT and TRT systems consolidation was also carri...

Performance of new radiation tolerant thin n-in-p Silicon pixel sensors for the CMS experiment at High Luminosity LHC

CERN Document Server

Dalla Betta, G.F; Darbo, G; Dinardo, Mauro; Giacomini, G; Menasce, Dario; Meschini, Marco; Messineo, Alberto; Moroni, Luigi; Rivera, Ryan Allen; Ronchin, S; Uplegger, Lorenzo; Viliani, Lorenzo; Zoi, Irene; Zuolo, Davide

2017-01-01

The High Luminosity upgrade of the CERN-LHC (HL-LHC) demands for a new high-radiation tolerant solid-state pixel sensor capable of surviving fluencies up to a few 10$^{16}$ particles/cm$^2$ at $\\sim$3 cm from the interaction point. To this extent the INFN ATLAS-CMS joint research activity in collaboration with Fondazione Bruno Kessler-FBK, is aiming at the development of thin n-in-p type pixel sensors for the HL-LHC. The R and D covers both planar and single-sided 3D columnar pixel devices made with the Si-Si Direct Wafer Bonding technique, which allows for the production of sensors with 100~$\\mu {\\rm m}$ and 130~$\\mu {\\rm m}$ active thickness for planars, and 130~$\\mu {\\rm m}$ for 3D sensors, the thinnest ones ever produced so far. First prototypes of hybrid modules bump-bonded to the present CMS readout chip have been tested in beam tests. Preliminary results on their performance before and after irradiation are presented.

Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

International Nuclear Information System (INIS)

Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

2011-01-01

Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

Firmware development and testing of the ATLAS IBL Read-Out Driver card

CERN Document Server

Chen, S-P; The ATLAS collaboration; Falchieri, D; Gabrielli, A; Hauck, S; Hsu, S-C; Kretz, M; Kugel, A; Travaglini, R; Wensing, M

2014-01-01

The ATLAS Experiment is reworking and upgrading systems during the current LHC shutdown. In particular, the Pixel detector is inserting an additional inner layer called Insertable B-Layer (IBL). The Read-Out Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development focused on migrating and tailoring HDL code blocks from Pixel ROD to ensure modular compatibility in future ROD upgrades, in which a unified code version will interface with IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using a realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, tested in testbench and on ROD prototypes, will be ...

Progress in the development of the DTMROC time measurement chip for the ATLAS transition radiation tracker (TRT)

CERN Document Server

Alexander, C; Dressnandt, N; Ekenberg, T; Farthouat, Philippe; Keener, P T; Lam, N; La Marra, D; Mann, J; Newcomer, F M; Ryzhov, V; Söderberg, M; Szczygiel, R; Van Berg, R; Williams, H H

2001-01-01

A 16-channel digital time-measurement readout chip (DTMROC) has been fabricated in the TEMIC/DM1LL left bracket 1 right bracket BI- CMOS radiation-hard process for the Large Hadron Collider's (LHC) Transition Radiation Tracker (ATLAS/TRT) at CERN left bracket 2 right bracket . The chip receives discriminated straw-drift-tube signals from bipolar amplifier-shaper-discriminator chips (ASDBLR). measures the arrival time in 3.125 ns increments ( plus or minus 1 ns), and stores the data in a pipeline for 3.3mus. A trigger signal (L1A) causes the data to be tagged with a time stamp and stored for readout- Up to 13 events may be stored in an on-chip buffer while data is being clocked out in a 40 MHz serial stream. The chip has been designed to function after exposure to 1x10**1**4 protons/cm**2 and 1 Mrad total dose. System beam-tests have demonstrated measurement of track positions with a resolution of 165mum and 85% efficiency at rates up to 18MHz. 6 Refs.

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

Science.gov (United States)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

CMOS Image Sensors: Electronic Camera On A Chip

Science.gov (United States)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Development of a Detector Control System for the ATLAS Pixel detector in the HL-LHC

International Nuclear Information System (INIS)

Lehmann, N.; Kersten, S.; Zeitnitz, C.; Karagounis, M.

2016-01-01

The upgrade of the LHC to the HL-LHC requires a new ITk detector. The innermost part of this new tracker is a pixel detector. The University of Wuppertal is developing a new DCS to monitor and control this new pixel detector. The current concept envisions three parallel paths of the DCS. The first path, called security path, is hardwired and provides an interlock system to guarantee the safety of the detector and human beings. The second path is a control path. This path is used to supervise the entire detector. The control path has its own communication lines independent from the regular data readout for reliable operation. The third path is for diagnostics and provides information on demand. It is merged with the regular data readout and provides the highest granularity and most detailed information. To reduce the material budget, a serial power scheme is the baseline for the pixel modules. A new ASIC used in the control path is in development at Wuppertal for this serial power chain. A prototype exists already and a proof of principle was demonstrated. Development and research is ongoing to guarantee the correct operation of the new ASIC in the harsh environment of the HL-LHC. The concept for the new DCS will be presented in this paper. A focus will be made on the development of the DCS chip, used for monitoring and control of pixel modules in a serial power chain.

Quality Assurance and Functionality Tests on Electrical Components during the ATLAS IBL Production

CERN Document Server

Jentzsch, J; The ATLAS collaboration

2012-01-01

For the first ATLAS pixel upgrade scheduled in 2013 a new front-end chip generation (FE- I4) has been developed. The second version (FE-I4B) hosting two different solid-state sensor technologies (planar silicon and 3D silicon) has been produced to be built into a new pixel layer (the Insertable B-Layer, IBL). Prototypes of these assembled modules have been tested in laboratory and testbeam measurements before and after irradiation. Quality assurance measurements under clean room conditions, including temperature and humidity control, have been and will be performed on the required parts during the various production steps of the IBL, namely connectivity as well as electrical tests and signal probing on individual parts and also assembled subsystems. Test results of measurements on flexes, modules and staves will be presented.