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Sample records for 90-nm cmos adaptive

  1. Record RF performance of standard 90 nm CMOS technology

    Tiemeijer, L.F.; Havens, R.J.; Kort, de, YAW Yvonne; Scholten, A.J.; Langevelde, van, H.J.; Klaassen, D.B.M.; Sasse, G.T.; Bouttement, Y.; Petot, C.; Bardy, S.; Gloria, D.; Scheer, P.; Boret, S.; Haaren, van, M.; Clement, C.

    2005-01-01

    We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

  2. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported

  3. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    Rivetti, A; Wyss, J; Bisello, D; Costa, M; Kloukinas, K; Demaria, N; Pantano, D; Rousset, J; Battaglia, M; Mansuy, C; Potenza, A; Ikemoto, Y; Giubilato, P; Chalmet, P; Mugnier, H; Silvestrin, L; Marchioro, A

    2013-01-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Omega cm, which is at least one order of magnitude greater than the typical value (1-10 Omega cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. (C) 2013 Elsevier B.V. All rights reserved

  4. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply. (semiconductor integrated circuits)

  5. A 90 nm CMOS, 6 μW Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection

    Badami, Komail; Lauwereins, Steven; Meert, Wannes; Verhelst, Marian

    2016-01-01

    This work presents a sub-6 µW acoustic front-end for speech/non-speech classification in a voice activity detection (VAD) in 90 nm CMOS. Power consumption of the VAD system is minimized by architectural design around a new Power-Proportional sensing paradigm and the use of machine-learning assisted moderate-precision analog analytics for classification. Power-Proportional sensing allows for hierarchical and context-aware scaling of the frontend’s power consumption depending on the complexity ...

  6. The temperature dependence of single-event transients in 90-nm CMOS dual-well and triple-well NMOSFETs

    Li Da-Wei; Qin Jun-Rui; Chen Shu-Ming

    2013-01-01

    This paper investigates the temperature dependence of single-event transients (SETs) in 90-nm complementary metat-oxide semiconductor (CMOS) dual-well and triple-well negative metal-oxide semiconductor field-effect transistors (NMOSFETs).Technology computer-aided design (TCAD) three-dimensional (3D) simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55 ℃C to 125 ℃C,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.

  7. A low power 20 GHz comparator in 90 nm COMS technology

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications. (semiconductor integrated circuits)

  8. A low power 20 GHz comparator in 90 nm COMS technology

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

    2014-05-01

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

  9. CMOS continuous-time adaptive equalizers for high-speed serial links

    Gimeno Gasca, Cecilia; Aldea Chagoyen, Concepción

    2015-01-01

    This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc.  The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-...

  10. Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

    2006-01-01

    A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0.25 μm 2.5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

  11. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems. PMID:25955990

  12. Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

    Edwin Becerra‐Álvarez

    2009-04-01

    Full Text Available This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA for the next generation of wireless hand‐held devicesby using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing thefulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such thatthe mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit underanalysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topologyincluding inductive‐source degeneration, MOS‐varactor based tuning networks, and programmable bias currents. This proposal,with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications;the LNA is designed to cope with the requirements of GSM (PCS1900, WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g. In orderto evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA featuresNF16dB, S11‐3.3 dBm over the 1.85‐2.48 GHz band. For all the standards understudy the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of thereconfigurable LNA occupies an area of 1.8mm2.

  13. Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE

    Johansson, Mattias; Ehrs, Jonas

    2010-01-01

    The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator. A current mode envelope...

  14. FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Ho, Jonathan; Wu, Xin; Panaite, Petrisor; Chacko, Manoj; Zhang, Yunqiang; Lei, Wen-Kang

    2005-11-01

    In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  15. A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

    Ju Hao; Zhou Yumei; Zhao Jianzhong

    2011-01-01

    This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid IO.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6 × 0.57 mm2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.

  16. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  17. DOE experiment for scattering bars optimization at the 90nm node

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  18. Phase-change memory technology with self-aligned μTrench cell architecture for 90 nm node and beyond

    Pirovano, A.; Pellizzer, F.; Tortorelli, I.; Riganó, A.; Harrigan, R.; Magistretti, M.; Petruzza, P.; Varesi, E.; Redaelli, A.; Erbetta, D.; Marangon, T.; Bedeschi, F.; Fackenthal, R.; Atwood, G.; Bez, R.

    2008-09-01

    A novel self-aligned μTrench-based cell architecture for phase change memory (PCM) process is presented. The low programming current and the good dimensional control of the sub-lithographic features achieved with the μTrench structure are combined with a self-aligned patterning strategy that simplify the integration process in term of alignment tolerances and of number of critical masks. The proposed architecture has been integrated in a 90 nm 128 Mb vehicle based on a pnp bipolar junction transistor for the array selection. The good active and leakage currents achieved by the purposely optimized selecting transistors combined with programming currents of 300 μA of the storage element and good distributions measured on the 128 Mb array demonstrate the suitability of the proposed architecture for the production of high-density PCM arrays at 90 nm and beyond.

  19. Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications

    Srinivasan, R; Bhat, Navakanta

    2005-01-01

    In this paper, we have studied and compared the RF performance metrics, unity gain frequency $(f_t)$ and Noise Figure (NF), of the devices with channel engineering consisting of halo and super steep retrograde channel (SSRC) implants, and the devices with uniform channel doping concentration, using process, device, and mixed mode simulations. The simulation results show that at 90nm gate lengths, for a given off-state leakage constraint $(I_O_F_F)$, devices with uniform channel doping conc...

  20. ESD protection device and circuit design for advanced CMOS technologies

    Semenov, Oleg; Sachdev, Manoj

    2008-01-01

    Strategies for design-oriented ESD protectionDistributed ESD protection networks optimized for sub-90nm CMOS ICsESD protection strategies for smart power ICs used in automotive industryThe impact of burn-in testing (accelerated test methods) on the ESD robustnessThe charge board ESD (CBM) testing used for wireless products

  1. Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

    A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 x 320 μm2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V. (semiconductor integrated circuits)

  2. Ion traps fabricated in a CMOS foundry

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  3. Performance Analysis of Si3N4 Capping Layer and SOI Technology in Sub 90 nm PMOS Device

    Rahim, Noor Ashikin Binti Abdul; Abdullah, Mohd. Hanapiah B.; Rusop, Mohamad

    2009-06-01

    This technical paper investigates the electrical analysis in sub 90 nm of PMOS. The investigation was carried out by using two different methods which is PMOS with strained silicon and Silicon-on-Insulator (SOI) technology. Strained silicon engineering has become a key innovation to enhance device on current. Recently, SOI technology has been widely accepted for use in mainstream high performance logic applications due to some advantageous offered over the bulk silicon. The performance of the devices is analyzed by focusing on the electrical characteristics of Id-Vd and Id-Vg curves for three different structures. Firstly, PMOS with strained silicon of Si3N4 capping layer covering the gate area and secondly the device with and without SOI technology. The fabrication process simulation was simulated by using SILVACO TCAD ATHENA simulator and the electrical characteristic was simulated by SILVACO TCAD ATLAS simulator to obtain Id-Vd and Id-Vg curves. A fruitful and knowledgeable results were reported from this paper, it could be seen that high tensile strain introduced to the device causing the drain current to decreased from Id(bulk) = -400 uA/um of bulk to Id(Strain) = -310 uA/um which is about 25% of decrement. Since the drain current decreased, the carrier mobility and the performance also decreased proportional to drain current. However when SOI technology is applied to the PMOS device, the drain current was increased up to Id(SOI) = -431 uA/um over the bulk, the increment of about 9.25% reported. A higher Id-Vg curve and lower threshold of about pVth(SOI) = -0.2178 V also reported from this paper which tells that the device with SOI technology exhibits low power consumption device and fast switching which in turns contribute to a faster performance.

  4. Nano CMOS

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  5. Nano CMOS

    Malay Ranjan Tripathy

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  6. Hot-carrier degradation for 90 nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

    Chen Hai-Feng; Hao Yue; Ma Xiao-Hua; Li Kang; Ni Jin-Yu

    2007-01-01

    The hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide under the low gate voltage (LGV) (at Vg=Vth,where Vth is the threshold voltage) stress has been investigated.It is found that the drain current decreases and the threshold voltage increases after the LGV (Vg=Yth) stress.The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress.By analysing the gate-induced drain leakage (GIDL) current before and after stresses,it is confirmed that under the LGV stress in uItra-short gate LDD-NMOSFET with ultra-thin gate oxide,the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do.which leads to the different degradation phenomena from those of the conventional NMOS devices.This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Vg=Vth with various drain biases.Experimental results show that the degradation slopes(n) range from 0.21 to 0.41.The value of n is less than that of conventional MOSFET(0.5-0.6) and also that of the long gate length LDD MOSFET (~0.8).

  7. A CMOS VLSI cochlea

    Lyon, Richard F.; Mead, Carver A.

    1988-01-01

    An engineered system that hears, such as a speech recognizer, can be designed by modeling the cochlea, or inner ear, and higher levels of the auditory nervous system. To be useful in such a system, a model of the cochlea should incorporate a variety of known effects, such as an asymmetric lowpass/bandpass response at each output channel, a short ringing time, and active adaptation to a wide range of input signal levels. An analog electronic cochlea has been built in CMOS VLSI technology...

  8. CMOS circuits manual

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  9. Nano watt power rail-to-rail CMOS amplifier with adaptive biasing circuits for ultralow-power analog LSIs

    Ozaki, Toshihiro; Hirose, Tetsuya; Tsubaki, Keishi; Kuroki, Nobutaka; Numa, Masahiro

    2015-04-01

    In this paper, we present a rail-to-rail folded-cascode amplifier (AMP) with adaptive biasing circuits (ABCs). The circuit uses a nano ampere current reference circuit to achieve ultralow-power and ABCs to achieve high-speed operation. The ABCs are based on conventional circuits and modified to be suitable for rail-to-rail operation. The measurement results demonstrated that the AMP with the proposed ABCs can operate with an ultralow-power of 384 nA when the input voltage was 0.9 V and achieve high speeds of 0.162 V/µs at the rise time and 0.233 V/µs at the fall time when the input pulse frequency and the amplitude were 10 kHz and 1.5 Vpp, respectively.

  10. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    Chun-Chi Chen; Chao-Lieh Chen; Yi Lin

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point cal...

  11. A novel colour-sensitive CMOS detector

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-10-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  12. A 0.76-pJ/Pulse 0.1-1 Gpps Microwatt IR-UWB CMOS Pulse Generator with Adaptive PSD Control Using A Limited Monocycle Precharge Technique

    Shen, Ming; Yin, Ying-Zheng; Jiang, Hao;

    2015-01-01

    This brief presents an ultra-wideband pulse generator topology featuring adaptive control of power spectral density for a broad range of applications with different data rate requirements. The adaptivity is accomplished by employing a limited monocycle precharge approach to control the energy used...... for pulse generation at different desired data rates. By doing so, the need for tuning circuits is eliminated and the radiated power is maintained at the highest level allowed by the Federal Communications Commission. A prototype pulse generator has been implemented using the UMC 180-nm CMOS process...... for validation. The measured results show that the pulse generator can be used for a wide pulse repetition rate range from 100 Mpps to 1 Gpps. In addition, the pulse generator consumes 0.76 pJ/pulse at 1 Gpps, equivalent to 760 μW and has a compact size of 0.09 mm2....

  13. Analog domain adaptive equalizer for low power 40 Gbps DP-QPSK receivers

    Nandakumar Nambath; Pawan Kumar Moyade; Allmin Ansari; Shalabh Gupta

    2014-04-01

    Electrical domain equalization of chromatic and polarization mode dispersion is attractive in coherent optical communication links. Digital coherent receivers used for this purpose are based on high speed ADCs followed by DSP, which dissipate excessive amount of power and are very costly to implement. We propose analog coherent receiver to drastically reduce the power consumption, size and cost. An adaptive feed forward equalizer for 40 Gbps dual polarization quadrature phase shift keying (DP-QPSK) systems, which processes signals in analog domain itself, is demonstrated using circuit and system simulations. The equalizer, designed in 90 nm CMOS technology, consumes 450 mW of power and occupies 1.8 mm × 1.1 mm chip area. System simulations are used to show that blind equalization is also possible when this approach is used in decision directed mode.

  14. Développement de capteurs à pixels CMOS pour un détecteur de vertex adapté au collisionneur ILC

    Fu, Yunan

    2012-01-01

    The thesis has been a priority as taking ownership of vertical integration technologies used in the industry to realize a multistage development, and to evaluate the contributions on CMOS pixel sensors (CPS). 3D integration technologies (3DIT) provide a way to mitigate this hampering correlation between speed and resolution, since they allow to staple layers of readout circuitry on top of the sensing layer, which results in a drastic increase of the functionalities located in (the shadow of) ...

  15. The modulation effect of substrate doping on multi-node charge collection and single-event transient propagation in 90-nm bulk complementary metal-oxidesemiconductor technology

    Qin Jun-Rui; Chen Shu-Ming; Liu Bi-Wei; Liu Zheng; Liang Bin; Du Yan-Kang

    2011-01-01

    Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor (CMOS) technologies,which are significant for charge sharing,thus affecting the propagated single event transient pulsewidths in circuits.The trends of charge collected by the drain of a positive channel metal-oxide semiconductor (PMOS) and an N metal-oxide semiconductor (NMOS) are opposite as the substrate doping increases.The PMOS source will inject carriers after strike and the amount of charge injected will increase as the substrate doping increases,whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough.Additionally,it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current,and has little effect on the drift and diffusion.The change in substrate doping has a much greater effect on PMOS than on NMOS.

  16. CAOS-CMOS camera.

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  17. Beyond CMOS nanodevices 2

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  18. Customized CMOS wavefront sensor

    Monteiro, D. W. L.; Vdovin, G.; Rocha, J.G.; Iordanov, V.; Loktev, M.; Sarro, P.

    2002-01-01

    We report on an integrated Hartmann wavefront sensor (WFS) using passive-pixel architecture and pixels clustered as position-sensitive detectors for dynamic wavefront analysis. This approach substitutes a conventional imager, such as a CCD or CMOS imager, by a customized detector, thus improving the overall speed performance. CMOS (complementary-metal- oxide-semiconductor) technology enables on-chip integration of several analog and digital circuitry. The sensor performance depends on the fea...

  19. Beyond CMOS nanodevices 1

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  20. BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design

    Uday Panwar; Kavita Khare

    2014-01-01

    A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time condition, here aim is to focus on run time leakage reduction techn...

  1. A Light Source for Testing CMOS Imagers

    Hancock, Jed J.; Baker, Doran

    2003-01-01

    Testing the optical properties of complementary metal oxide (CMOS) imagers requires a light source. The light source must produce stable uniform light with calibrated wavelength and intensity. Available commercial light source units are costly and often unalterable to a custom test setup. The proposed light source is designed to be affordable and adaptable while maintaining the necessary optical quality. The design consists of an array of light emitting diodes (LED), an infrared (IR) cut-off ...

  2. CMOS dot matrix microdisplay

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  3. MicroCMOS design

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  4. Wideband CMOS receivers

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  5. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  6. Further developments on a novel color sensitive CMOS detector

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-05-01

    The Transverse Field Detector (TFD) is a recently proposed Silicon pixel device designed to perform color imaging without the use of color filters. The color detection principle is based on the dependence of the Silicon absorption coefficient from the wavelength and relies on the generation of a suitable transverse electric field configuration, within the semiconductor active layer, to drive photocarriers generated at different depths towards different collecting electrodes. Each electrode has in this way a different spectral response with respect to the incoming wavelength. Pixels with three or four different spectral responses can be implemented within ~ 6 μm of pixel dimension. Thanks to the compatibility with standard triple well CMOS processes, the TFD can be used in an Active Pixel Sensor exploiting a dedicated readout topology, based on a single transistor charge amplifier. The overall APS electronics includes five transistors (5T) and a feedback capacitance, with a resulting overall fill factor around 50%. In this work the three colors and four colors TFD pixel simulations and implementations in a 90 nm standard CMOS triple well technology are described. Details on the design of a TFD APS mini matrix are provided and preliminary experimental results on four colors pixels are presented.

  7. Implantable CMOS Biomedical Devices

    Toshihiko Noda

    2009-11-01

    Full Text Available The results of recent research on our implantable CMOS biomedical devices are reviewed. Topics include retinal prosthesis devices and deep-brain implantation devices for small animals. Fundamental device structures and characteristics as well as in vivo experiments are presented.

  8. High-Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

    Mak, Pui-In

    2012-01-01

    This book presents high-/mixed-voltage analog and radio frequency (RF) circuit techniques for developing low-cost multistandard wireless receivers in nm-length CMOS processes.  Key benefits of high-/mixed-voltage RF and analog CMOS circuits are explained, state-of-the-art examples are studied, and circuit solutions before and after voltage-conscious design are compared. Three real design examples are included, which demonstrate the feasibility of high-/mixed-voltage circuit techniques.    Provides a valuable summary and real case studies of the state-of-the-art in high-/mixed-voltage circuits and systems; Includes novel high-/mixed-voltage analog and RF circuit techniques – from concept to practice; Describes the first high-voltage-enabled mobile-TVRF front-end in 90nm CMOS and the first mixed-voltage full-band mobile-TV Receiver in 65nm CMOS; Demonstrates the feasibility of high-/mixed-voltage circuit techniques with real design examples.  

  9. CMOS Low Power Cell Library for Digital Design

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  10. CMOS-controlled rapidly tunable photodetectors

    Chen, Ray

    With rapidly increasing data bandwidth demands, wavelength-division-multiplexing (WDM) optical access networks seem unavoidable in the near future. To operate WDM optical networks in an efficient scheme, wavelength reconfigurability and scalability of the network are crucial. Unfortunately, most of the existing wavelength tunable technologies are neither rapidly tunable nor spectrally programmable. This dissertation presents a tunable photodetector that is designed for dynamic-wavelength allocation WDM network environments. The wavelength tuning mechanism is completely different from existing technologies. The spectrum of this detector is programmable through low-voltage digital patterns. Since the wavelength selection is achieved by electronic means, the device wavelength reconfiguration time is as fast as the electronic switching time. In this dissertation work, we have demonstrated a tunable detector that is hybridly integrated with its customized CMOS driver and receiver with nanosecond wavelength reconfiguration time. In addition to its nanosecond wavelength reconfiguration time, the spectrum of this detector is digitally programmable, which means that it can adapt to system changes without re-fabrication. We have theoretically developed and experimentally demonstrated two device operating algorithms based on the same orthogonal device-optics basis. Both the rapid wavelength tuning time and the scalability make this novel device very viable for new reconfigurable WDM networks. By taking advantage of CMOS circuit design, this detector concept can be further extended for simultaneous multiple wavelength detection. We have developed one possible chip architecture and have designed a CMOS tunable optical demux for simultaneous controllable two-wavelength detection.

  11. Single photon detection and localization accuracy with an ebCMOS camera

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  12. Single photon detection and localization accuracy with an ebCMOS camera

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  13. Automation of CMOS technology migration illustrated by RGB to YCrCb analogue converter

    Naumowicz, M.; Melosik, M.; Katarzynski, P.; Handkiewicz, A.

    2013-09-01

    The paper illustrates a practical example of technology migration applied to the colour space converter realized in CMOS technology. The element has analogue excitation and response signals expressed in current mode. Such converter may be incorporated into an integrated vision sensor for preconditioning acquired image data. The idea of a computer software tool supporting the automated migration and design reuse is presented as the major contribution. The mentioned tools implement the Hooke-Jeeves direct search method for performing the multivariable optimization. Our purpose is to ensure transferring the circuit between usable fabrication technologies and preserving its functional properties. The colour space converter is treated as the case study for performance evaluation of the proposed tool in cooperation with HSPICE simulation software. The original CMOS technology files for Taiwan semiconductor (TSMC) plant were utilized for the research. The automated design migration from 180 nm into 90 nm resulted with obtaining compact IC layout characterized by a smaller area and lower power consumption. The paper is concluded with a brief summary that proves the usability of the proposed tool in designing CMOS cells dedicated for low power image processing.

  14. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Mouna Karmani

    2011-07-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layoutsimulation results.

  15. Analysis of EMCCD and sCMOS readout noise models for Shack-Hartmann wavefront sensor accuracy

    Basden, Alastair

    2015-01-01

    In recent years, detectors with sub-electron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: EMCCD and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models for sCMOS readout noise are optimistic, and recommend that a proper treatment of the sCMOS rms readout noise probability distribution should be considered during instrument performance modelling and development.

  16. Comparators in nanometer CMOS technology

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  17. CMOS Nonlinear Signal Processing Circuits

    Hung,; Yu-Cherng,

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  18. Adapt

    Bargatze, L. F.

    2015-12-01

    Active Data Archive Product Tracking (ADAPT) is a collection of software routines that permits one to generate XML metadata files to describe and register data products in support of the NASA Heliophysics Virtual Observatory VxO effort. ADAPT is also a philosophy. The ADAPT concept is to use any and all available metadata associated with scientific data to produce XML metadata descriptions in a consistent, uniform, and organized fashion to provide blanket access to the full complement of data stored on a targeted data server. In this poster, we present an application of ADAPT to describe all of the data products that are stored by using the Common Data File (CDF) format served out by the CDAWEB and SPDF data servers hosted at the NASA Goddard Space Flight Center. These data servers are the primary repositories for NASA Heliophysics data. For this purpose, the ADAPT routines have been used to generate data resource descriptions by using an XML schema named Space Physics Archive, Search, and Extract (SPASE). SPASE is the designated standard for documenting Heliophysics data products, as adopted by the Heliophysics Data and Model Consortium. The set of SPASE XML resource descriptions produced by ADAPT includes high-level descriptions of numerical data products, display data products, or catalogs and also includes low-level "Granule" descriptions. A SPASE Granule is effectively a universal access metadata resource; a Granule associates an individual data file (e.g. a CDF file) with a "parent" high-level data resource description, assigns a resource identifier to the file, and lists the corresponding assess URL(s). The CDAWEB and SPDF file systems were queried to provide the input required by the ADAPT software to create an initial set of SPASE metadata resource descriptions. Then, the CDAWEB and SPDF data repositories were queried subsequently on a nightly basis and the CDF file lists were checked for any changes such as the occurrence of new, modified, or deleted

  19. Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.

    Carrillo, Snaider; Harkin, Jim; McDaid, Liam; Pande, Sandeep; Cawley, Seamus; McGinley, Brian; Morgan, Fearghal

    2012-09-01

    The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware. PMID:22561008

  20. Large area CMOS image sensors

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  1. CMOS Integrated Carbon Nanotube Sensor

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  2. Electrical Interconnections Through CMOS Wafers

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis descri...

  3. CMOS MEMS Fabrication Technologies and Devices

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  4. From vertex detectors to inner trackers with CMOS pixel sensors

    Besson, A; Spiriti, E; Baudot, J; Claus, G; Goffe, M; Winter, M

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  5. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  6. Latch-up control in CMOS integrated circuits

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

  7. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption

  8. Analog filters in nanometer CMOS

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  9. High-voltage CMOS detectors

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  10. CMOS test and evaluation a physical perspective

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  11. Fabrication of CMOS image sensors

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  12. A Surface Micromachined CMOS MEMS Humidity Sensor

    Jian-Qiu Huang; Fei Li; Min Zhao; Kai Wang

    2015-01-01

    This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. A...

  13. Microelectronic test structures for CMOS technology

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  14. CMOS Image Sensors for High Speed Applications

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  15. Absorbed dose by a CMOS in radiotherapy

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  16. A 0.76-pJ/Pulse 0.1-1 Gpps Microwatt IR-UWB CMOS Pulse Generator with Adaptive PSD Control Using A Limited Monocycle Precharge Technique

    Shen, Ming; Yin, Ying-Zheng; Jiang, Hao; Tian, Tong; Jensen, Ole Kiel; Mikkelsen, Jan Hvolgaard

    2015-01-01

    This brief presents an ultra-wideband pulse generator topology featuring adaptive control of power spectral density for a broad range of applications with different data rate requirements. The adaptivity is accomplished by employing a limited monocycle precharge approach to control the energy used for pulse generation at different desired data rates. By doing so, the need for tuning circuits is eliminated and the radiated power is maintained at the highest level allowed by the Federal Communi...

  17. Analysis of EMCCD and sCMOS readout noise models for Shack-Hartmann wavefront sensor accuracy

    Basden, Alastair

    2015-01-01

    In recent years, detectors with sub-electron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: EMCCD and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models fo...

  18. Analysis of electron multiplying charge coupled device and scientific CMOS readout noise models for Shack–Hartmann wavefront sensor accuracy.

    Basden, A. G.

    2015-01-01

    In recent years, detectors with subelectron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: electron multiplying charge coupled device (EMCCD) and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also ...

  19. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Bowen, Chris R.; John Taylor; Anthony H. D. Graham; Jon Robbins

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanr...

  20. JFET-CMOS microstrip front-end

    While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper. (orig.)

  1. Design of Current steering DAC using 250nm CMOS Technology

    Vineet Tiwari

    2012-06-01

    applied at the reference terminal. Analog to digital converter performs the reverse operation. It has many era of operations in audio and Video form and whiffletree electromagnetic device uses DAC linkage in typewriter. It describes the 3.3 volt, 65 MHz 8 bit CMOS digital to analog converter, includes two stage current cell matrix. This paper describes a 1v CMOS 8 bit DAC with two stage current cell matrix architecture which consists of 4 MSB and 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also the no of high swing current mirrors. The designed DAC with a by 90 nm nwell CMOS standard process. The experiment is based on settling time, Integrity, or non linearity. The designed DAC is fully operational for power supply down to 1 volt such that DAC is suitable for low voltage and low power applications.

  2. 0.18μm CMOS, MONOLITHIC MSTP ASIC

    Wang Peng; Jin Depeng; Zeng Lieguang

    2006-01-01

    A highly integrated monolithic Multi-Service Transport Platform (MSTP) Application Specified Integrated Circuit (ASIC) MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×106 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring (RPR) and E1 traffics into protected Synchronous Digital Hierarchy (SDH) STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.

  3. Optoelectronic circuits in nanometer CMOS technology

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  4. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    Valente, V.; Demosthenous, A.

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) ...

  5. Analysis of electron multiplying charge coupled device and scientific CMOS readout noise models for Shack-Hartmann wavefront sensor accuracy

    Basden, Alastair G.

    2015-07-01

    In recent years, detectors with subelectron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: electron multiplying charge coupled device (EMCCD) and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models for sCMOS readout noise are optimistic, and we recommend that a proper treatment of the sCMOS root mean square readout noise probability distribution should be considered during instrument performance modeling and development.

  6. Carbon Nanotube Integration with a CMOS Process

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  7. Batch Processing of CMOS Compatible Feedthroughs

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    process scheme allows for post processing of feedthroughs in any kind of fully processed CMOS wafer. The fabrication of the electrical feedthroughs is based on wet etching of through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and feedthrough metal. The...... feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  8. Carbon Nanotube Integration with a CMOS Process

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  9. Fully CMOS Memristor Based Chaotic Circuit

    S. C. Yener

    2014-12-01

    Full Text Available This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.

  10. Yield enhancement methodologies for 90-nm technology and beyond

    Allgair, John; Carey, Todd; Dougan, James; Etnyre, Tony; Langdon, Nate; Murray, Brooke

    2006-03-01

    In order to stay competitive in the rapidly advancing international semiconductor industry, a manufacturing company needs to continually focus on several areas including rapid yield learning, manufacturing cost, statistical process control limits, process yield, equipment availability, cycle time, turns per direct labor hour, customer on time delivery and zero customer defects. To hold a competitive position in the semiconductor market, performance to these measurable factors mut be maintained regardless of the technology generation. In this presentation, the methodology applied by Freescale Semiconductor to achieve the fastest yield learning curve in the industry, as cited by Dr. Robert Leachman of UC Berkley in 2003, will be discussed.

  11. Ultralow-loss CMOS copper plasmonic waveguides

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.; Volkov, Valentyn S.

    2016-01-01

    microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  12. BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design

    Uday Panwar

    2014-04-01

    Full Text Available A new algorithm based on Input Vector Control (IVC technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited by stacking effect when the series transistors are maximized in OFF state condition. This method is independent of process technology and does not require any additional power supply. This paper gives an optimized solution of input pattern determination of some small circuit to find minimum leakage vector considering promising and non-promising node which helps to reduce the time complexity of the algorithm. Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and different logics respectively.

  13. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  14. Device Considerations for Nanophotonic CMOS Global Interconnects

    Manipatruni, Sasikanth; Lipson, Michal; Young, Ian A.

    2012-01-01

    We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub 100 fJ/cm/bit interconnects including tuning power, serialization-deserialization energy, optical insertion losses, extinction ratio and bit error rates. Using CMOS with integrated nanophotonics as an example platform, we derive the energy/bit, linear and areal bandwidth density ...

  15. Terahertz Circuits and Systems in CMOS

    Sherry, Hani Mahmoud

    2014-01-01

    This PhD dissertation presents and analyses various room-temperature circuits for Terahertz detection and generation implemented in CMOS 65nm bulk and 28nm FDSOI throughout the course of the thesis. The work discusses the methodology of design and feasibility of fully-integrated focal-plane arrays of detectors in CMOS technologies as potential commercial solutions for various THz applications. The interesting characteristics of the Terahertz portion (300GHz-3THz) of the Electromagnetic sp...

  16. On evolution of CMOS image sensors

    Choubey, Bhaskar; Gouveia, Luiz

    2014-01-01

    CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the...

  17. Fully CMOS Memristor Based Chaotic Circuit

    Yener, S. C.; H. H. Kuntman

    2014-01-01

    This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the succ...

  18. Heavy ion effect on MOS and CMOS structures on insulator (CMOS/SOI)

    The effects of cosmic ions on Metal-Oxide-Semiconductor structures are described. Measurements done at different energies on MOS capacitors and CMOS on insulator transistors (CMOS/SOI) show a substrate funneling which gives rise to a transient current on device electrodes. The pulse amplitude is simply related to capacitor bias, lifetime of substrate minority carriers and range of the impinging ion

  19. CMOS prototype for retinal prosthesis applications with analog processing

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  20. Characterization and reliability of CMOS microstructures

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  1. Delay estimation for CMOS functional cells

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr...... arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on...

  2. A Standard CMOS Humidity Sensor without Post-Processing

    Oleg Nizhnik; Kazusuke Maenaka; Kohei Higuchi

    2011-01-01

    A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  3. Noise in sub-micron CMOS image sensors

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  4. Integrated 60GHz RF beamforming in CMOS

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  5. Scaling CMOS devices through alternative structures

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  6. Modeling of Amperometric Immunosensor for CMOS Integration

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  7. Device Considerations for Nanophotonic CMOS Global Interconnects

    Manipatruni, Sasikanth; Young, Ian A

    2012-01-01

    We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub 100 fJ/bit interconnects including tuning power, serialization-deserialization energy, and optical insertion losses. Using silicon photonics as an example platform, we derive the energy/bit, linear and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for continued improvements in mode volume (40 Gb/s), tuning power ( 6 channels). We also contrast the figures of merits for CMOS electrical interconnects with nanophotonic interconnects.

  8. Radiation-hardened bulk CMOS technology

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  9. CMOS circuit design, layout and simulation

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  10. A Novel Method to Increase LinLog CMOS Sensors’ Performance in High Dynamic Range Scenarios

    Andrés Iborra

    2011-08-01

    Full Text Available Images from high dynamic range (HDR scenes must be obtained with minimum loss of information. For this purpose it is necessary to take full advantage of the quantification levels provided by the CCD/CMOS image sensor. LinLog CMOS sensors satisfy the above demand by offering an adjustable response curve that combines linear and logarithmic responses. This paper presents a novel method to quickly adjust the parameters that control the response curve of a LinLog CMOS image sensor. We propose to use an Adaptive Proportional-Integral-Derivative controller to adjust the exposure time of the sensor, together with control algorithms based on the saturation level and the entropy of the images. With this method the sensor’s maximum dynamic range (120 dB can be used to acquire good quality images from HDR scenes with fast, automatic adaptation to scene conditions. Adaptation to a new scene is rapid, with a sensor response adjustment of less than eight frames when working in real time video mode. At least 67% of the scene entropy can be retained with this method.

  11. Ultra-low Voltage CMOS Cascode Amplifier

    Lehmann, Torsten; Cassia, Marco

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique...

  12. Nanometer CMOS ICS from basics to asics

    Veendrick, Harry

    2008-01-01

    Explores all associated disciplines of nanometer CMOS ICs Includes physics, design, process, yield, packaging, power, variability, reliability and signal integrityIncludes extensive discussions on future trends and challengesAll subjects are described at the same level of clarity Well-suited for self-study

  13. CMOS VHF transconductance-C lowpass filter

    Nauta, B.

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  14. A 24GHz Radar Receiver in CMOS

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  15. Analog IC reliability in nanometer CMOS

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  16. Fully CMOS-compatible titanium nitride nanoantennas

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing

  17. Smart temperature sensors in standard CMOS

    Makinwa, K.A.A.

    2010-01-01

    A smart temperature sensor is an integrated system consisting of a temperature sensor, its bias circuitry and an analog-to-digital converter (ADC). When manufactured in CMOS technology, such sensors have found widespread use due to their low cost, small size and ease of use. In this paper the basic

  18. Low energy CMOS for space applications

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  19. Fully CMOS-compatible titanium nitride nanoantennas

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  20. Low noise monolithic CMOS front end electronics

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  1. CMOS MEMS capacitive absolute pressure sensor

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa−1 in the pressure range of 0–300 kPa. (paper)

  2. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  3. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  4. A Zero Suppression Micro-Circuit for Binary Readout CMOS Monolithic Sensors

    Himmi, A; Torheim, O; Hu-Guo, C; Winter, A

    2009-01-01

    The EUDET-JRA1 beam telescope and the STAR vertex detector upgrade will be equipped with CMOS pixel sensors allowing to provide high density tracking adapted to intense particle beams. The EUDET sensor Mimosa26, is designed and fabricated in a CMOS-0.35μm Opto process. Its architecture is based on a matrix of 1152x576 pixels, 1152 column-level Analogue-to-Digital Conversion (ADC) by discriminators and a zero suppression circuitry. This paper focused on the data sparsification architecture, allowing a data compression factor between from 10 and 1000, depending on the hit density per frame. It can be extended to the final sensor for the STAR upgrade.

  5. PALM and STORM: Into large fields and high-throughput microscopy with sCMOS detectors.

    Almada, Pedro; Culley, Siân; Henriques, Ricardo

    2015-10-15

    Single Molecule Localization Microscopy (SMLM) techniques such as Photo-Activation Localization Microscopy (PALM) and Stochastic Optical Reconstruction Microscopy (STORM) enable fluorescence microscopy super-resolution: the overcoming of the resolution barrier imposed by the diffraction of light. These techniques are based on acquiring hundreds or thousands of images of single molecules, locating them and reconstructing a higher-resolution image from the high-precision localizations. These methods generally imply a considerable trade-off between imaging speed and resolution, limiting their applicability to high-throughput workflows. Recent advancements in scientific Complementary Metal-Oxide Semiconductor (sCMOS) camera sensors and localization algorithms reduce the temporal requirements for SMLM, pushing it toward high-throughput microscopy. Here we outline the decisions researchers face when considering how to adapt hardware on a new system for sCMOS sensors with high-throughput in mind. PMID:26079924

  6. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

    Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from −354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply. (semiconductor integrated circuits)

  7. Modeling and parameter extraction of CMOS on-chip coplanar waveguides up to 67 GHz for mm-wave applications

    Coplanar waveguides (CPW) are widely used in mm-wave circuits designs for their good performance. A novel unified model of various on chip CPWs for mm-wave application, together with corresponding direct parameter extraction methodologies, are proposed and investigated, where standard CPW, grounded CPW (GCPW) and CPW with slotted shield (SCPW) are included. Several kinds of influences of different structures are analyzed and considered into the model to explain the frequency-dependent per-unit-length L, C, R, and G parameters, among which the electromagnetic coupling for CPWs with large lower ground or shield is described by a new C–L–R series path in the parallel branch. The direct extraction procedures are established, which can ensure both accuracy and simplicity compared with other reported methods. Different CPWs are fabricated and measured on 90-nm CMOS processes with Short-Open-Load-Through (SOLT) de-embedding techniques. Excellent agreement between the model and the measured data for different CPWs is achieved up to 67 GHz. (semiconductor integrated circuits)

  8. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  9. An Implantable CMOS Amplifier for Nerve Signals

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact on...... the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a...

  10. IR CMOS: infrared enhanced silicon imaging

    Pralle, M. U.; Carey, J. E.; Haddad, Homayoon; Vineis, C.; Sickler, J.; Li, X.; Jiang, J.; Sahebi, F.; Palsule, C.; McKee, J.

    2013-06-01

    SiOnyx has developed visible and infrared CMOS image sensors leveraging a proprietary ultrafast laser semiconductor process technology. This technology demonstrates 10 fold improvements in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Furthermore, these sensitivity enhancements are achieved on a focal plane with state of the art noise performance of 2 electrons/pixel. By capturing light in the visible regime as well as infrared light from the night glow, this sensor technology provides imaging in daytime through twilight and into nighttime conditions. The measured 10x quantum efficiency at the critical 1064 nm laser node enables see spot imaging capabilities in a variety of ambient conditions. The spectral sensitivity is from 400 to 1200 nm.

  11. Noise in a CMOS digital pixel sensor

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  12. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips. PMID:26654281

  13. Noise in a CMOS digital pixel sensor

    Based on the study of noise performance in CMOS digital pixel sensor (DPS), a mathematical model of noise is established with the pulse-width-modulation (PWM) principle. Compared with traditional CMOS image sensors, the integration time is different and A/D conversion is implemented in each PWM DPS pixel. Then, the quantitative calculating formula of system noise is derived. It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model, photodiode shot noise does not vary with luminance, but dark current shot noise does. According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator, the total noise can be reduced. These results serve as a guideline for the design of PWM DPS. (semiconductor integrated circuits)

  14. Cmos spdt switch for wlan applications

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  15. CMOS Camera Array With Onboard Memory

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  16. Cantilever-Based Biosensors in CMOS Technology

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  17. Air Quality Monitoring Using CCD/ CMOS Devices

    Low, Khee Lam; Joanna, Tan Choay Ee; Sim, Keat; Jafri, Mohd Zubir Mat; and, Khiruddin Abdullah

    2010-01-01

    In this chapter, we showed a method for measuring of the air quality index by using the CCD/CMOS sensor. We showed two examples to obtain index values by using webcam and CCTV. Both devices provided a high correlation between the measured and estimated PM10. So, the imaging method is capable to measure PM10 values in the environment. Futher application can be conducted using different devices.

  18. Low Power Oriented CMOS Circuit Optimization Protocol

    Verle, A.; Michel, X.; Azemard, Nadine; Maurine, Philippe; Auvergne, Daniel

    2007-01-01

    Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternative. The target is delay constraint satisfaction with minimum area cost. We validate the design space exploration method, defining maximum...

  19. Measurements of Si hybrid CMOS x-ray detector characteristics

    Bongiorno, Stephen D.; Falcone, Abraham D.; Burrows, David N.; Cook, Robert

    2010-07-01

    The recent development of active pixel sensors as X-Ray focal plane arrays will place them in contention with CCDs on future satellite missions. Penn State University (PSU) is working with Teledyne Imaging Sensors (TIS) to develop X-Ray Hybrid CMOS devices (HCDs), a type of active pixel sensor with fast frame rates, adaptable readout timing and geometry, low power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However, their bucket-brigade readout architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels through the detector substrate with low power, on-chip readout integrated circuits. Faster frame rates, achieved with adaptable readout timing and geometry, will allow the next generation's larger effective area telescopes to observe brighter sources free of pileup. In HCDs, radiation damaged lattice sites affect a single pixel instead of an entire row. The PSU X-ray group is currently testing 4 Teledyne HCDs, with low cross-talk CTIA devices in development. We will report laboratory measurements of HCD readnoise, interpixel-capacitance and its impact on event selection, linearity, and energy resolution as a function of energy.

  20. A Surface Micromachined CMOS MEMS Humidity Sensor

    Jian-Qiu Huang

    2015-10-01

    Full Text Available This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. According to the test results, the sensitivity of the sensor was 7 mV/%RH (relative humidity and the linearity of the sensor was 1.9% at 20 °C. Both the sensitivity and linearity were not sensitive to the temperature but the curve of the output voltage shifted with the temperature. The hysteresis of the humidity sensor decreased from 3.2% RH to 1.9% RH as the temperature increased from 10 to 40 °C. The recovery time of the sensor was 85 s at room temperature (25 °C.

  1. CMOS imagers from phototransduction to image processing

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  2. A Standard CMOS Humidity Sensor without Post-Processing

    Oleg Nizhnik

    2011-06-01

    Full Text Available A 2 µW power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023-10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  3. Interferometric comparison of the performance of a CMOS and sCMOS detector

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  4. On-chip solar battery structure for CMOS LSI

    Arima, Yutaka; Ehara, Masaya

    2006-01-01

    A built-in method of on-chip solar battery in a CMOS LSI is proposed. The proposed solar battery can be formed using conventional CMOS process technology. It can generate a high voltage of 0.6-0.83 V by a series connection structure of two types of p-n junction diodes formed with the CMOS circuit simultaneously on the LSI chip. The generated voltage is sufficient to drive the conventional CMOS circuit without modi. cation. The test chip was produced experimentally using conventional 0.35 mu m...

  5. Current-mode CMOS hybrid image sensor

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  6. Current Development of CMOS Image Sensors%CMOS 图像传感器的发展现状

    王宝元; 吴三灵; 温波; 焦明纲; 周发明

    2000-01-01

    Aim To review the current development of CMOS image sensors. Methods The background, architecture and current development of CMOS image sensors is describled. The trade-offs between the CMOS image sensors and the CCD image sensors are put forword. Results The development tendency of CMOS image sensors is discussed. Conclusion The CMOS image sensor has the potential of a wide range of application.%目的 了解当前CMOS图像传感器的发展状况. 方法 详细介绍了图像传感器的历史背景、发展现状、像素单元的结构、工作原理以及 CMOS 图像传感器芯片的整体结构,并比较了 CMOS 图像传感器和 CCD 图像传感器的优、 缺点. 结果 指出了 CMOS 图像传感器发展趋势. 结论 CMOS 图像传感器具有美好的发展前途.

  7. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    A. Schmitz

    2005-01-01

    Full Text Available Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0. Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  8. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.;

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  9. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  10. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  11. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radiation and device physics amongst each other.

  12. BioCMOS Interfaces and Co-Design

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  13. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    R. Turchetta; A. Fant; P. Gasiorek; C. Esbrand; J.A. Griffiths; M.G. Metaxas; G.J. Royle; R. Speller; C. Venanzi; P.F. van der Stelt; H.G.C. Verheij; G. Li; S. Theodoridis; H. Georgiou; D. Cavouras; G. Hall; M. Noy; J. Jones; J. Leaver; D. Machin; S. Greenwood; M. Khaleeq; H. Schulerud; J.M. Østby; F. Triantis; A. Asimidis; D. Bolanakis; N. Manthos; R. Longo; A. Bergamaschi

    2007-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end app

  14. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    R. Turchetta; A. Fant; P. Gasiorek; C. Esbrand; J.A. Griffiths; M.G. Metaxas; G.J. Royle; R. Speller; C. Venanzi; P.F. van der Stelt; H.G.C. Verheij; G. Li; S. Theodoridis; H. Georgiou; D. Cavouras; G. Hall; M. Noy; J. Jones; J. Leaver; D. Machin; S. Greenwood; M. Khaleeq; H. Schulerud; J.M. Østby; F. Triantis; A. Asimidis; D. Bolanakis; N. Manthos; R. Longo; A. Bergamaschi

    2006-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end app

  15. CMOS biomicrosystems where electronics meets biology

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  16. Nano-CMOS gate dielectric engineering

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  17. An Implantable CMOS Amplifier for Nerve Signals

    Nielsen, Jannik Hammel; Lehmann, Torsten

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard...

  18. Measurement device for cmos-mems accelerometer

    Somasundaram, Namitha

    2014-01-01

    [ANGLÈS] This project reports the process of development of the Printed Circuit Board (PCB) - Zephyr for the experimental CMOS MEMS accelerometer testchip, Bailed II. The problem of capacitance mismatch at the input bridge is solved through a simple and innovative arrangement of resistors, jumpers and capacitors on the PCB. A filter is designed with the inductor capacitor pair to filter noise from the DC source. An amplifier with a gain of 10 is designed to amplify the output signals of the B...

  19. SEU error rates in advanced digital CMOS

    Space-based electronics is exposed to cosmic radiations that result in bit reversal errors or Single Event Upsets. Those errors are generally taken into account through an error-rate quantification expressed in Expected errors per Bit-Day (EBD). A procedure to evaluate this EBD for CMOS memory devices is presented here and applied to a typical data set. This method arises from a development of the upset rate convolution integral. It can be applied to ground-based test data, and provide a realistic upset-rate estimate for space flight conditions. (D.L.). 20 refs., 7 figs

  20. Plasmonic Modulator Using CMOS Compatible Material Platform

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.; Ferrera, Marcello; Lavrinenko, Andrei; Shalaev, Vladimir M.; Boltasseva, Alexandra

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation is...... obtained by varying the ca rrier concentration of th e transparent conducting oxide layer and exciting plasmonic resonance in the structure. The analysis shows that an extinction ratio of 46 dB/μm can be achieved at the telecommunication wavelength. Proposed structure is particularly convenient for...... integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  1. Plasmonic Modulator Using CMOS Compatible Material Platform

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation is...... obtained by varying the ca rrier concentration of th e transparent conducting oxide layer and exciting plasmonic resonance in the structure. The analysis shows that an extinction ratio of 46 dB/μm can be achieved at the telecommunication wavelength. Proposed structure is particularly convenient for...

  2. Variation-aware advanced CMOS devices and SRAM

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  3. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  4. Theoretical performance analysis for CMOS based high resolution detectors.

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-01

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive. PMID:24353390

  5. A CMOS high speed imaging system design based on FPGA

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  6. Vulnerability and failure modes of CMOS/SOS or CMOS/SO: technologies in nuclear and space environments

    Nuclear and space environments consist of several fluxes of ionizing particles. Some of them (photons, electrons, protons) lead to progressive degradation of characteristics. Heavy ions ionize active layers along tracks, and involve specific effects. These effects are discussed in the cases of bipolar (TTL-LS, ECL), CMOS on Sapphire and CMOS on Insulator technologies, through different versions of a unique microprocessor 2901

  7. Planar pixel sensors in commercial CMOS technologies

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  8. Challenges of nickel silicidation in CMOS technologies

    Breil, Nicolas [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Lavoie, Christian [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Ozcan, Ahmet [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Baumann, Frieder [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Klymko, Nancy [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Nummy, Karen [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Sun, Bing [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Jordan-Sweet, Jean [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Yu, Jian [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Zhu, Frank [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Narasimha, Shreesh [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Chudzik, Michael [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States)

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  9. Modulated CMOS camera for fluorescence lifetime microscopy.

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  10. A Biologically Inspired CMOS Image Sensor

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  11. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  12. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

    Shin, SangHak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage...

  13. High-speed multicolor photometry with CMOS cameras

    Pokhvala, S M; Reshetnyk, V M

    2012-01-01

    We present the results of testing the commercial digital camera Nikon D90 with a CMOS sensor for high-speed photometry with a small telescope Celestron 11" on Peak Terskol. CMOS sensor allows to perform photometry in 3 filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR color system of CMOS sensors is close to the Johnson BVR system. The results of testing show that we can measure the stars up to V $\\simeq$ 14 with the precision of 0.01 mag. Stars up to magnitude V $\\sim$ 10 can shoot at 24 frames per second in the video mode.

  14. Development of a CMOS process using high energy ion implantation

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  15. Ink-Jet Printed CMOS Electronics from Oxide Semiconductors.

    Garlapati, Suresh Kumar; Baby, Tessy Theres; Dehm, Simone; Hammad, Mohammed; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

    2015-08-01

    Complementary metal oxide semiconductor (CMOS) technology with high transconductance and signal gain is mandatory for practicable digital/analog logic electronics. However, high performance all-oxide CMOS logics are scarcely reported in the literature; specifically, not at all for solution-processed/printed transistors. As a major step toward solution-processed all-oxide electronics, here it is shown that using a highly efficient electrolyte-gating approach one can obtain printed and low-voltage operated oxide CMOS logics with high signal gain (≈21 at a supply voltage of only 1.5 V) and low static power dissipation. PMID:25867029

  16. CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors

    This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good performance in terms of spatial resolution, efficiency, radiation hardness have been demonstrated and work is now well under way to deliver the first MAPS-based vertex detectors

  17. High-Speed Low Power Design in CMOS

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand the...

  18. CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors

    Turchetta, R

    2006-01-01

    This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good performance in terms of spatial resolution, efficiency, radiation hardness have been demonstrated and work is now well under way to deliver the first MAPS-based vertex detectors.

  19. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  20. IMEC pushes the limits of CMOS

    George Marsh

    2002-06-01

    Visionary stuff, but although the day of the cyborg may still be some way off, IMEC (Inter-University MicroElectronics Centre — Europe’s leading independent microelectronics research organization — sees its role as expediting some aspects of this future. This means, inter alia, a dedication to maintaining the currency of Moore’s Law, in the belief that this can continue for several years yet before fundamental limits impose insurmountable barriers. Success will require further extension of the boundaries of complementary metal oxide silicon (CMOS, that backbone of mainstream electronic technology. Materials, both the manipulation of existing and development of new, are germane to this, as Materials Today discovered on a recent visit.

  1. Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

    Lauri Koskinen

    2012-06-01

    Full Text Available This paper presents the first known timing-error detection (TED microprocessor able to operate in subthreshold. Since the minimum energy point (MEP of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV.

  2. CMOS front ends for millimeter wave wireless communication systems

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  3. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

  4. Depleted CMOS pixels for LHC proton-proton experiments

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  5. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Fangming Deng; Yigang He; Chaolong Zhang; Wei Feng

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate ...

  6. Delta Doping High Purity CCDs and CMOS for LSST

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  7. A Low Power Low Voltage High Performance CMOS Current Mirror

    Sirish Rao,; Sampath Kumar V

    2015-01-01

    The current mirrors are one of the most important circuits in designing the analog and mixed-mode circuit. A low power and low voltage high-performance CMOS current mirror with optimized input and output resistance are presented in this paper. SPICE simulations confirm the high-performance CMOS current mirror with power supply close to the threshold voltage of the transistor. In this paper, for achieving the low input resistance and a very high output resistance, the combination o...

  8. RF CMOS Integrated Circuit: History, Current Status and Future Prospects

    Ishihara, Noboru; Amakawa, Shuhei; Masu, Kazuya

    2011-01-01

    As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimet...

  9. CMOS Image Sensors: Electronic Camera On A Chip

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  10. High performances monolithic CMOS detectors for space applications

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Vignon, Bruno; Magnan, Pierre; Farre, Jean; Corbière, Franck; Martin-Gonthier, Philippe

    2001-01-01

    During the last 10 years, research about CMOS image sensors (also called APS -Active Pixel Sensors) has been intensively carried out, in order to offer an alternative to CCDs as image sensors. This is particularly the case for space applications as CMOS image sensors feature characteristics which are obviously of interest for flight hardware: parallel or semi-parallel architecture, on chip control and processing electronics, low power dissipation, high level ofradiation tolerance... Many imag...

  11. CMOS monolithic pixel sensors research and development at LBNL

    D Contarato; J-M Bussat; P Denes; L Griender; T Kim; T Stezeberger; H Weiman; M Battaglia; B Hooberman; L Tompkins

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  12. Integrating security solutions to support nanoCMOS electronics research

    Sinnott, R.O.; Bayliss, C.; T. Doherty; Martin, D.; Millar, C.; Stewart, G; Watt, J; A. Asenov; Roy, G.; S Roy; Davenhall, C.; Harbulot, B.; Jones, M

    2008-01-01

    The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative electronics research across multiple institutions in the UK with especially strong industrial and commercial involvement. Unlike other domains, the electronics industry is driven by the necessity of protecting the intellectual property of the data, designs and software associated with next generation...

  13. OLED-on-CMOS integration for optoelectronic sensor applications

    Vogel, Uwe; Kreye, Daniel; Reckziegel, Sven; Törker, Michael; Grillberger, Christiane; Amelung, Jörg

    2007-02-01

    Highly-efficient, low-voltage organic light emitting diodes (OLEDs) are well suitable for post-processing integration onto the top metal layer of CMOS devices. This has been proven for OLED microdisplays so far. Moreover, OLEDon- CMOS technology may also be excellently suitable for various optoelectronic sensor applications by combining highly efficient emitters, use of low-cost materials and cost-effective manufacturing together with silicon-inherent photodetectors and CMOS circuitry. The use of OLEDs on CMOS substrates requires a top-emitting, low-voltage and highly efficient OLED structure. By reducing the operating voltage for the OLED below 5V, the costs for the CMOS process can be reduced, because a process without high-voltage option can be used. Red, orange, white, green and blue OLED-stacks with doped charge transport layers were prepared on different dualmetal layer CMOS test substrates without active transistor area. Afterwards, the different devices were measured and compared with respect to their performance (current, luminance, voltage, luminance dependence on viewing angle, optical outcoupling etc.). Low operating voltages of 2.4V at 100cd/m2 for the red p-i-n type phosphorescent emitting OLED stack, 2.5V at 100cd/m2 for the orange phosphorescent emitting OLED stack and 3.2V at 100cd/m2 for the white fluorescent emitting OLED have been achieved here. Therefore, those OLED stacks are suitable for use in a CMOS process even within a regular 5V process option. Moreover, the operating voltage achieved so far is expected to be reduced further when using different top electrode materials. Integrating such OLEDs on a CMOS-substrate provide a preferable choice for silicon-based optical microsystems targeted towards optoelectronic sensor applications, as there are integrated light barriers, optocouplers, or lab-onchip devices.

  14. CMOS integration of inkjet-printed graphene for humidity sensing

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; S. K. Ray; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graph...

  15. Poly-SiGe for MEMS-above-CMOS sensors

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  16. Advancement of CMOS Doping Technology in an External Development Framework

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  17. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μ m TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when ...

  18. Multiband CMOS sensor simplify FPA design

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  19. A CMOS readout circuit for microstrip detectors

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation

  20. CMOS absorbance detection system for capillary electrophoresis

    This paper presents a cost-effective portable photodetection system for capillary electrophoresis absorptiometry. By using a CMOS BDJ (buried double p-n junction) detector, a dual-wavelength method for absorbance measurement is implemented. This system includes associated electronics for low-noise pre-amplification and A/D conversion, followed by digital signal acquisition and processing. Two signal processing approaches are adopted to enhance the signal to noise ratio. One is variable time synchronous detection, which optimizes the sensitivity and measuring rate compared to a conventional synchronous detection technique. The other is a statistical approach based on principal component analysis, which allows optimal estimation of detected signal. This system has been designed and tested in capillary electrophoresis conditions. Its operation has been verified with performances comparable to those of a commercialized spectrophotometric system (HP-3D CE). With potential on-chip integration of associated electronics, it may be operated as an integrable detection module for microchip electrophoresis and other microanalysis systems

  1. Fast Hopping Frequency Generation in Digital CMOS

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  2. Electrothermal frequency references in standard CMOS

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  3. Optical detection of ultrasound from optically rough surfaces using a custom CMOS sensor

    The optical detection of ultrasound from optically rough surfaces is severely limited when using a conventional interferometric or optical beam deflection (OBD) setup because the detected light is speckled. This means that complicated and expensive setups are required to detect ultrasound optically on rough surfaces. We present a CMOS integrated circuit that can detect laser ultrasound in the presence of speckle. The detector circuit is based on the simple knife edge detector. It is self-adapting and is fast, inxepensive, compact and robust. The CMOS circuit is implemented as a widefield array of 32×32 pixels. At each pixel the received light is compared with an adjacent pixel in order to determine the local light gradient. The result of this comparison is stored and used to connect each pixel to the positive or negative gradient output as appropriate (similar to a balanced knife edge detector). The perturbation of the surface due to ultrasound preserves the speckle distribution whilst deflecting it. The spatial disturbance of the speckle pattern due to the ultrasound is detected by considering each pair of pixels as a knife edge detector. The sensor can adapt itself to match the received optical speckle pattern in less than 0.1 μs, and then detect the ultrasound within 0.5 μs of adaptation. This makes it possible to repeatedly detect ultrasound from optically rough surfaces very quickly. The detector is capable of independent operation controlled by a local microcontroller, or it may be connected to a computer for more sophisticated configuration and control. We present the theory of its operation and discuss results validating the concept and operation of the device. We also present preliminary results from an improved design which grants a higher bandwidth, allowing for optical detection of higher frequency ultrasound

  4. A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

    The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results

  5. CMOS image sensor noise reduction method for image signal processor in digital cameras and camera phones

    Yoo, Youngjin; Lee, SeongDeok; Choe, Wonhee; Kim, Chang-Yong

    2007-02-01

    Digital images captured from CMOS image sensors suffer Gaussian noise and impulsive noise. To efficiently reduce the noise in Image Signal Processor (ISP), we analyze noise feature for imaging pipeline of ISP where noise reduction algorithm is performed. The Gaussian noise reduction and impulsive noise reduction method are proposed for proper ISP implementation in Bayer domain. The proposed method takes advantage of the analyzed noise feature to calculate noise reduction filter coefficients. Thus, noise is adaptively reduced according to the scene environment. Since noise is amplified and characteristic of noise varies while the image sensor signal undergoes several image processing steps, it is better to remove noise in earlier stage on imaging pipeline of ISP. Thus, noise reduction is carried out in Bayer domain on imaging pipeline of ISP. The method is tested on imaging pipeline of ISP and images captured from Samsung 2M CMOS image sensor test module. The experimental results show that the proposed method removes noise while effectively preserves edges.

  6. A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

    Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

    2015-01-01

    The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

  7. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Orit Skorka

    2011-04-01

    Full Text Available Technologies to fabricate integrated circuits (IC with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  8. CMOS Cell Sensors for Point-of-Care Diagnostics

    Haluk Kulah

    2012-07-01

    Full Text Available The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS. CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  9. Improved Space Object Observation Techniques Using CMOS Detectors

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  10. VLSI scaling methods and low power CMOS buffer circuit

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  11. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  12. Towards a 10{mu}s, thin and high resolution pixelated CMOS sensor system for future vertex detectors

    De Masi, R., E-mail: rita.demasi@ires.in2p3.f [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Amar-Youcef, S. [IFK, Goethe-Universitaet, Frankfurt am Main (Germany); Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Degerli, Y. [IRFU/SEDI (CEA) Saclay (France); Deveaux, M. [IFK, Goethe-Universitaet, Frankfurt am Main (Germany); Dorokhov, A.; Doziere, G.; Dulinski, W. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Gelin, M. [IRFU/SEDI (CEA) Saclay (France); Goffe, M.; Fontaine, J.C.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France)

    2011-02-01

    The physics goals of many high energy experiments require a precise determination of decay vertices, imposing severe constraints on vertex detectors (readout speed, granularity, material budget,...). The IPHC-IRFU collaboration developed a sensor architecture to comply with these requirements. The first full scale CMOS sensor was realised and equips the reference planes of the EUDET beam telescope. Its architecture is being adapted to the needs of the STAR (RHIC) and CBM (FAIR) experiments. It is a promising candidate for the ILC experiments and the ALICE detector upgrade (LHC). A substantial improvement to the CMOS sensor performances, especially in terms of radiation hardness, should come from a new fabrication technology with depleted sensitive volume. A prototype sensor was fabricated to explore the benefits of the technology. The crucial system integration issue is also currently being addressed. In 2009 the PLUME collaboration was set up to investigate the feasibility and performances of a light double sided ladder equipped with CMOS sensors, aimed primarily for the ILC vertex detector but also of interest for other applications such as the CBM vertex detector.

  13. Towards a 10 μs, thin and high resolution pixelated CMOS sensor system for future vertex detectors

    De Masi, R.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Degerli, Y.; Deveaux, M.; Dorokhov, A.; Doziére, G.; Dulinski, W.; Gelin, M.; Goffe, M.; Fontaine, J. C.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Voutsinas, G.; Wagner, F. M.; Winter, M.

    2011-02-01

    The physics goals of many high energy experiments require a precise determination of decay vertices, imposing severe constraints on vertex detectors (readout speed, granularity, material budget,…). The IPHC-IRFU collaboration developed a sensor architecture to comply with these requirements. The first full scale CMOS sensor was realised and equips the reference planes of the EUDET beam telescope. Its architecture is being adapted to the needs of the STAR (RHIC) and CBM (FAIR) experiments. It is a promising candidate for the ILC experiments and the ALICE detector upgrade (LHC). A substantial improvement to the CMOS sensor performances, especially in terms of radiation hardness, should come from a new fabrication technology with depleted sensitive volume. A prototype sensor was fabricated to explore the benefits of the technology. The crucial system integration issue is also currently being addressed. In 2009 the PLUME collaboration was set up to investigate the feasibility and performances of a light double sided ladder equipped with CMOS sensors, aimed primarily for the ILC vertex detector but also of interest for other applications such as the CBM vertex detector.

  14. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits Project

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  15. Microinjection of antisense c-mos oligonucleotides prevents meiosis II in the maturing mouse egg.

    O'Keefe, S J; Wolfes, H; Kiessling, A A; Cooper, G M

    1989-01-01

    Injection of antisense oligonucleotides was used to investigate the function of c-mos in murine oocytes. Oocytes injected with antisense c-mos oligonucleotides completed the first meiotic division but failed to initiate meiosis II. Instead, loss of c-mos function led to chromosome decondensation, reformation of a nucleus after meiosis I, and cleavage to two cells. Therefore, c-mos is required for meiosis II during murine oocyte maturation.

  16. Study of CMOS integrated signal processing circuit in capacitive sensors

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  17. Fabrication of the planar angular rotator using the CMOS process

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  18. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  19. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    Turchetta, R. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)], E-mail: r.turchetta@rl.ac.uk; Fant, A.; Gasiorek, P. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom); Esbrand, C.; Griffiths, J.A.; Metaxas, M.G.; Royle, G.J.; Speller, R.; Venanzi, C. [Department of Medical Physics and Bioengineering, University College London (United Kingdom); Stelt, P.F. van der; Verheij, H.; Li, G. [Academic Centre for Dentistry, Vrije Universiteit and University of Amsterdam (Netherlands); Theodoridis, S.; Georgiou, H. [Department of Informatics and Telecommunications, University of Athens (Greece); Cavouras, D. [Medical Image and Signal Processing Laboratory, Department of Medical Instrument Technology, Technological Education Institution of Athens (Greece); Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D. [High Energy Physics Group, Department of Physics, Imperial College, London (United Kingdom)] (and others)

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS)

  20. Design and characterization of avalanche photodiodes in submicron CMOS technologies

    Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

    2014-03-01

    The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

  1. Low-voltage CMOS operational amplifiers theory, design and implementation

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  2. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS)

  3. IGBT scaling principle toward CMOS compatible wafer processes

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  4. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  5. Spectrometer with CMOS demodulation of fiber optic Bragg grating sensors

    Christiansen, Martin Brokner

    A CMOS imager based spectrometer is developed to interrogate a network containing a large number of Bragg grating sensors. The spectrometer uses a Prism-Grating- Prism (PGP) to spectrally separate serially multiplexed Bragg reflections on a single fiber. As a result, each Bragg grating produces a discrete spot on the CMOS imager that shifts horizontally as the Bragg grating experiences changes in strain or temperature. The reflected wavelength of the spot can be determined by finding the center of the spot produced. The use of a randomly addressable CMOS imager enables a flexible sampling rate. Some fibers can be interrogated at a high sampling rate while others can be interrogated at a low sampling rate. However, the use of a CMOS imager leads to several unique problems in terms of signal processing. These include a logarithmic pixel response, a low signal-to-noise ratio, a long pixel time constant, and software issues. The expected capabilities of the CMOS imager based spectrometer are determined with a theoretical model. The theoretical model tests three algorithms for determining the center of the spot: single row centroid, single row parabolic fit, and entire spot centroid. The theoretical results are compared to laboratory test data and field test data. The CMOS based spectrometer is capable of interrogating many optical fibers, and in the configuration tested, the fiber bundle consisted of 23 fibers. Using this system, a single fiber can be interrogated from 778 nm to 852 nm at 2100 Hz or multiple fibers can be interrogated over the same wavelength so that the total number of fiber interrogations is up to 2100 per second. The reflected Bragg wavelength can be determined within +/-3pm, corresponding to a +/-3μɛ uncertainty.

  6. E-Beam Effects on CMOS Active Pixel Sensors

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  7. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  8. New Active Digital Pixel Circuit for CMOS Image Sensor

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  9. CMOS sensor as charged particles and ionizing radiation detector

    This paper reports results of CMOS sensor suitable for use as charged particles and ionizing radiation detector. The CMOS sensor with 640 × 480 pixels area has been integrated into an electronic circuit for detection of ionizing radiation and it was exposed to alpha particle (Am-241, Unat), beta (Sr-90), and gamma photons (Cs-137). Results show after long period of time (168 h) irradiation the sensor had not loss of functionality and also the energy of the charge particles and photons were very well obtained

  10. CMOS voltage references an analytical and practical perspective

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  11. An equivalent doping profile for CMOS substrate characterization

    Quaresma, Henrique J.; Mendonça dos Santos, P.; Cruz Serra, A.

    2013-01-01

    This work presents a non-destructive methodology to accurately estimate an equivalent substrate doping profile of a typical CMOS process. The methodology is based on simple experimental resistive measurements at different temperatures, obtained from a set of basic integrated test structures, and in 3D semiconductor simulations, to compute an estimate for the unknown CMOS process parameters. It is demonstrated that the resultant box distribution equivalent doping profile could be used to evaluate the variation of the substrate impedance as a function of temperature and substrate contact distance.

  12. Linear CMOS RF power amplifiers a complete design workflow

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  13. Low-voltage CMOS log companding analog design

    Serra-Graells, Francisco; Huertas, Jos ̌L 0

    2004-01-01

    This work presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modelling of the MOS transistor for Companding is supplied at the b

  14. From vertex detectors to inner trackers with CMOS pixel sensors

    Besson, A.; Pérez, A. Pérez; Spiriti, E.; Baudot, J.; Claus, G; Goffe, M.; de Winter, M.

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming ...

  15. Process optimization of radiation-hardened CMOS integrated circuits

    The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed

  16. A 0.5-GHz CMOS digital RF memory chip

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  17. Proton therapy beam dosimetry with silicon CMOS image sensors

    In a previous publication, it has been shown how neutron and proton beams in a quite broad energy interval, could be simply monitored with a position sensitive CMOS image detector. The direct read out, the lack of pile up effects, the stability of the signal, the detector linear response with proton energy and current and the very low costs of the device could make the CMOS detector a good candidate in addition to other well established detectors for proton radiation dosimetry. (N.T.)

  18. Effects of Proton Irradiation on a CMOS Image Sensor

    HUANG Qiang; MENG Xiang-Ti

    2007-01-01

    We perform 9 MeV proton irradiation of a complementary metal oxide semiconductor (CMOS) image sensor at doses from 1×109 to 4×1010 cm-2. In general, the average brightness of dark output images increases with an increasing dose, and reaches the maximum at 1×1010 cm-2. The captured colour images become very blurry at 4×1010 cm-2. These can be explained by change of concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of CMOS image sensor calculated by the TRIM simulation programme with dose.

  19. A 65 nm CMOS LNA for Bolometer Application

    Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

    2016-04-01

    Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

  20. New Curvature-Compensated CMOS Bandgap Voltage Reference

    Lu Shen; Ning Ning; Qi Yu; Yan Luo; Chun-Sheng Li

    2007-01-01

    A novel curvaturecompensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit,designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from 40 ℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is 56 dB at 10 MHz.

  1. High Q-factor CMOS-MEMS inductor

    Dai, Ching-Liang; Hong, Jin-Yu; Liu, Mao-Chen

    2008-01-01

    This study investigates a high Q-factor spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process. The spiral inductor is manufactured on silicon substrate using the 0.35 micrometers CMOS process. In order to reduce the substrate loss and enhance the Q-factor of the inductor, silicon substrate under the inductor is removed using a post-process. The post-process uses RIE (reactive ion etching) to etch the sacrificial layer of silicon dioxide, a...

  2. Low-power CMOS circuit design for fast infrared imagers

    Margarit Taule, Josep Maria

    2008-01-01

    La present tesi de màster detalla novedoses tècniques circuitals per al disseny de circuits integrats digitals CMOS de lectura compactes, de baixa potència i completament programables, destinats a aplicacions d'IR d'alta velocitat operant a temperatura ambient. En aquest sentit, el treball recull i amplia notablement la recerca iniciada en el Projecte Final de Carrera "Tècniques de disseny CMOS per a sistemes de visió híbrids de pla focal modular" obtenint-se resultats específics en tres dife...

  3. CMOS sigma-delta converters practical design guide

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  4. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  5. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  6. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  7. A toroidal inductor integrated in a standard CMOS process

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico;

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  8. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    Mao-Chen Liu

    2010-02-01

    Full Text Available This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K.

  9. Design for manufacturability and yield for nano-scale CMOS

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  10. Planar CMOS analog SiPMs: design, modeling, and characterization

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  11. A CMOS Camera-Based Pulse Oximetry Imaging System

    Humphries, K.; Ward, T.; Markham, C.

    2005-01-01

    In this paper a CMOS camera-based system for non-contact pulse oximetry imaging in transmission mode is described. Attention is drawn to the current uses of conventional pulse oximetry and the potential application of pulse oximetry imaging to developing objective wound assessment systems

  12. Single-chip RF communications systems in CMOS

    Olesen, Ole

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  13. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  14. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  15. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Rescigno R.; Finck Ch.; Juliani D.; Baudot J.; Dauvergne D.; Dedes G.; Krimmer J.; Ray C.; Reithinger V.; Rousseau M.; Testa E; Winter M.

    2014-01-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  16. Photon imaging using post-processed CMOS chips

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  17. New source of random telegraph signal in CMOS image sensors

    Goiffon, Vincent; Magnan, Pierre; Martin-Gonthier, Philippe; Virmontois, Cédric; Gaillardin, Marc

    2012-01-01

    We report a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley-Read-Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations.

  18. Study of CMOS image sensors for laser beam position detection

    We report on the study made on commercial CMOS image sensors in order to determine their feasibility for light beam position reconstruction. Measurements of the intrinsic position resolution, sensor photoresponse and uniformity were done. The effect of eventual background illumination was evaluated. The precision on the spatial point reconstruction was determined from linearity measurements. First results on gamma-ray radiation tolerance are presented

  19. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  20. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the outpu

  1. CMOS image sensors as an efficient platform for glucose monitoring.

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-01

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications. PMID:23900281

  2. High performance flexible CMOS SOI FinFETs

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  3. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  4. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80μm×16μm was fabricated in a 0.18μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors

  5. High-Voltage-Input Level Translator Using Standard CMOS

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  6. CMOS VLSI Active-Pixel Sensor for Tracking

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  7. Improved Space Object Orbit Determination Using CMOS Detectors

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  8. A high precision CMOS weak current readout circuit

    This paper presents a high precision CMOS weak current readout circuit. This circuit is capable of converting a weak current into a frequency signal for amperometric measurements with high precision and further delivering a 10-bit digital output. A fast stabilization-enhanced potentiostat has been proposed in the design, which is used to maintain a constant bias potential for amperometric biochemical sensors. A technique based on source voltage shifting that reduces the leakage current of the MOS transistor to the reverse diode leakage level at room temperature was employed in the circuit. The chip was fabricated in the 0.35 μm chartered CMOS process, with a single 3.3 V power supply. The interface circuit maintains a dynamic range of more than 100 dB. Currents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.

  9. Low power RF circuit design in standard CMOS technology

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  10. Pixel readout development in 65 nm CMOS technology

    Continuous trend of increasing luminosity of particle accelerators places severe constraints on detector tracking systems in terms of radiation hardness and ability to cope with high hit rates. One possible way for particle detectors to keep track with increasing luminosity is using of more advanced technologies. Ultra deep sub-micron CMOS technologies allow design of complex and high speed electronics with high integration density. In addition these technologies are inherently radiation hard. We present two prototypes of analog pixel front-end designed in 65 nm CMOS technology with applications oriented to upgrade of the ATLAS Pixel Detector. The silicon area of the pixel front-end prototypes is shared with other test circuits designed for applications in upgrade of the Pixel Vertex Detector of the Belle II experiment. Aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits are presented.

  11. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  12. Experimental research on transient ionizing radiation effects of CMOS microcontroller

    This paper presents an experimental test system of CMOS microcontroller EE80C196KC20. Based on this system, the transient ionizing radiation effects on microcontroller were investigated using 'Qiangguang-I' accelerator. The gamma pulse width was 20 ns and the dose rate (for the Si atom) was in the range of 6.7 x 106 to 2.0 x 108 Gy/s in the experimental study. The disturbance and latchup effects were observed at different dose rate levels. Latchup threshold of the microcontroller was obtained. Disturbance interval and the system power supply current have a relationship with the dose rate level. The transient ionizing radiation induces photocurrent in the PN junctions that are inherent in CMOS circuits. The photocurrent is responsible for the electrical and functional degradation. (authors)

  13. Nanocantilever based mass sensor integrated with cmos circuitry

    Davis, Zachary James; Abadal, G.; Campabadal, F.;

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of the...... mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... integrated with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

  14. 65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction

    Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

    2014-01-01

    Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

  15. A linear stepping PGA used in CMOS image sensors

    徐江涛; 李斌桥; 赵士彬; 李红乐; 姚素英

    2009-01-01

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  16. Submicron CMOS technologies for high energy physics and space applications

    Anelli, G; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Snoeys, W

    2001-01-01

    The radiation environment present in some of today's High-Energy Physics (HEP) experiments and in space has a detrimental influence on the integrated circuits working in these environments. Special technologies, called radiation hardened, have been used in the past to prevent the radiation-induced degradation. In the last decades, the market of these special technologies has undergone a considerable shrinkage, rendering them less reliably available and far more expensive than today's mainstream technologies. An alternative approach is to use a deep submicron CMOS technology. The most sensitive part to radiation effects in a MOS transistor is the gate oxide. One way to reduce the effects of ionizing radiation in the gate oxide is to reduce its thickness, which is a natural trend in modern technologies. Submicron CMOS technologies seem therefore a good candidate for implementing radiation-hardened integrated circuits using a commercial, inexpensive technology. Nevertheless, a certain number of radiation-induced...

  17. A linear stepping PGA used in CMOS image sensors

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  18. Effect of Threshold Voltage on Various CMOS Performance Parameter

    Mr. Abhishek Verma

    2014-04-01

    Full Text Available SiO2, once thought of as the most precious element in the design of CMOS circuits has not lived up to the expectations of being the perfect gate oxide. Efforts have been made to replace it with High K oxides such as Lanthanum Oxide (La2O3, Hafnium Oxide (HfO2 and many more. This review covers the problems faced by the High K oxides, one of them being escalation in threshold voltage which results in increased power dissipation. The solution to the above stated problem is to reduce the threshold voltage by several techniques, also covered in the review. Effect of threshold voltage on leakage current and power and reliability of CMOS are also taken under consideration.

  19. Future challenges in single event effects for advanced CMOS technologies

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  20. A New CMOS Current Reference with High Order Temperature Compensation

    2006-01-01

    A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 (m standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [(50~100℃] at a 1.8 V supply, and also achieves line regulation of 0.01%/V and (120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.

  1. TID Simulation of Advanced CMOS Devices for Space Applications

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  2. Diffuse reflectance measurements using lensless CMOS imaging chip

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ∼250 μm thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view

  3. Diffuse reflectance measurements using lensless CMOS imaging chip

    Schelkanova, I.; Pandya, A.; Shah, D.; Lilge, L.; Douplik, A.

    2014-10-01

    To assess superficial epithelial microcirculation, a diagnostic tool should be able to detect the heterogeneity of microvasculature, and to monitor qualitative derangement of perfusion in a diseased condition. Employing a lensless CMOS imaging chip with an RGB Bayer filter, experiments were conducted with a microfluidic platform to obtain diffuse reflectance maps. Haemoglobin (Hb) solution (160 g/l) was injected in the periodic channels (grooves) of the microfluidic phantom which were covered with ~250 μm thick layer of intralipid to obtain a diffusive environment. Image processing was performed on data acquired on the surface of the phantom to evaluate the diffuse reflectance from the subsurface periodic pattern. Thickness of the microfluidic grooves, the wavelength dependent contrast between Hb and the background, and effective periodicity of the grooves were evaluated. Results demonstrate that a lens-less CMOS camera is capable of capturing images of subsurface structures with large field of view.

  4. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  5. A CMOS ASIC Design for SiPM Arrays

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S.; Rudell, Jacques C.

    2011-01-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further descr...

  6. Photon imaging using post-processed CMOS chips

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic signals (in the extreme case this conversion is from a single photon into a single electron), an electron multiplication structure to increase the magnitude of the signal pulse and a position sensit...

  7. CMOS Image Sensor with a Built-in Lane Detector

    Li-Chen Fu; Hsien-Chein Cheng; Pei-Yung Hsiao; Shih-Shinh Huang

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chi...

  8. Smart CMOS image sensor for lightning detection and imaging

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  9. Nanocantilever based mass sensor integrated with cmos circuitry

    Davis, Zachary James; Abadal, G.; Campabadal, F; Figueras, E.; Esteve, J.; Verd, J.; Perez-Murano, F.; Borrise, X.; Nilsson, S. G.; Miximov, I.; Montelius, L.; Barniol, N.; Boisen, Anja

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The d...

  10. CMOS Terahertz Sensors and Circuits for Imaging Applications

    Domingues, Suzana

    2014-01-01

    A low-cost THz sensor, with a broadband high responsivity, low noise equivalent power, and capable of working at room temperature is still a challenge. Moreover, sensor integration with signal processing electronics is required in order to realize compact systems to be used in commercial imaging applications. In this thesis, CMOS FET-based THz detectors and with integrated noise-efficient readout circuits are presented as a solution. In an attempt to improve the THz focal plane arrays stat...

  11. Photon detection with CMOS sensors for fast imaging

    Baudot, J.; Dulinski, W.; de Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N

    2008-01-01

    International audience Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e-, and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of have been reached for 100 kilo-pixels sens...

  12. High-speed modulator in zero-change CMOS photonics

    Alloatti, Luca; Ram, Rajeev Jagga

    2016-01-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  13. Proton therapy beam dosimetry with silicon CMOS image sensors

    A 16 mm2 CMOS Image Sensor with more than 100 000 pixels and with a standard video output was irradiated with 48, 95 and 180 MeV protons. Proton-induced nuclear reactions in silicon were detected as bright spots or tracks in the images. The angular and energy-dependent response of the detector were studied. The application to proton dosimetry is discussed

  14. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Orit Skorka; Dileepan Joseph

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensor...

  15. CMOS circuits generating arbitrary chaos by using pulsewidthmodulation techniques

    Morie, Takashi; Sakabayashi, S; Nagata, M.; Iwata, A

    2000-01-01

    This paper describes CMOS circuits generating arbitrary chaotic signals. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain. Arbitrary nonlinear transformation functions can be generated by using the conversion from an analog voltage to a pulsewidth modulation (PWM) signal; for the transformation, time-domain nonlinear voltage waveforms having the same shape as the inverse function of the desired transformation function are u...

  16. A CMOS Smart Temperature and Humidity Sensor with Combined Readout.

    Clemens Eder; Virgilio Valente; Nick Donaldson; Andreas Demosthenous

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ra...

  17. CMOS Smart Sensor for Monitoring the Quality of Perishables

    Ueno, K.; Hirose, T; Asai, T.; Amemiya, Y.

    2007-01-01

    We developed a CMOS integrated-circuit sensor to monitor the change in quality of perishables that depends on surrounding temperatures. Our sensor makes use of the fact that the temperature dependence of the subthreshold current in MOSFETs is analogous to that of the degradation of perishables. The sensor is attached to perishable goods such as farm and marine products and is distributed from producers to consumers along with the goods. During their distribution process, the sensor measures t...

  18. CMOS bandgap references and temperature sensors and their applications

    Wang, G.

    2005-01-01

    Two main parts have been presented in this thesis: device characterization and circuit. In integrated bandgap references and temperature sensors, the IC(VBE, characteristics of bipolar transistors are used to generate the basic signals with high accuracy. To investigate the possibilities to fabricate high-precision bandgap references and temperature sensors in low-cost CMOS technology, the electrical characteristics of substrate bipolar pnp transistors have been investigated over a wide tempe...

  19. Tin (Sn) for enhancing performance in silicon CMOS

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  20. High-performance imagers for space applications: The strong benefits of CMOS image sensors processes

    Space community has quickly understood the benefits that CMOS technology can procure for the design and manufacture of image sensors, with respect to CCDs which have been the detector of choice for most optical applications during the last 25 years. On the other hand, a majority of space applications is requesting high electro-optics performances to avoid payload oversizing. This was not reachable by CMOS monolithic devices built with standard mixed signal processes. Since the end of the 90s, foundries have developed outstanding CMOS processes optimised for Image Sensors. Combined with the intrinsic advantages of CMOS, they allow developing powerful imagers for space missions. After explaining specificity of CIS processes, the development of a first generation of CMOS Image Sensors for optical instrument will be detailed. Continuation of this route, thanks to the use of advanced CMOS processes, will then be presented.

  1. CMOS integration of inkjet-printed graphene for humidity sensing

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  2. Multi-target electrochemical biosensing enabled by integrated CMOS electronics

    An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

  3. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development

  4. CMOS Monolithic Active Pixel Sensors (MAPS): New 'eyes' for science

    Re-invented in the early 1990s on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology have slowly invaded the world of consumer imaging and are now on the edge of becoming the first technology in this field, previously dominated by Charge-Coupled Devices (CCD). Thanks to the advantages brought by the use of standard CMOS technology, MAPS have great potential in many areas including function integration, leading to the concept of a camera-on-a-chip, pixel size, random access to selected region-of-interest, low power, higher speed and radiation resistance. In many ways, MAPS have introduced a new way of doing imaging. Despite their success in the consumer arena, MAPS are still to make a definitive impact in the world of scientific imaging. This paper first briefly reviews the way radiation is detected by a CMOS sensor, before analysing the main noise source and its relationship with the full well capacity and the dynamic range. This paper will also show first examples of scientific results, obtained in the detection of low-energy electrons

  5. Aluminum nitride on titanium for CMOS compatible piezoelectric transducers

    Piezoelectric materials are widely used for microscale sensors and actuators but can pose material compatibility challenges. This paper reports a post-CMOS compatible fabrication process for piezoelectric sensors and actuators on silicon using only standard CMOS metals. The piezoelectric properties of aluminum nitride (AlN) deposited on titanium (Ti) by reactive sputtering are characterized and microcantilever actuators are demonstrated. The film texture of the polycrystalline Ti and AlN films is improved by removing the native oxide from the silicon substrate in situ and sequentially depositing the films under vacuum to provide a uniform growth surface. The piezoelectric properties for several AlN film thicknesses are measured using laser doppler vibrometry on unpatterned wafers and released cantilever beams. The film structure and properties are shown to vary with thickness, with values of d33f, d31 and d33 of up to 2.9, −1.9 and 6.5 pm V−1, respectively. These values are comparable with AlN deposited on a Pt metal electrode, but with the benefit of a fabrication process that uses only standard CMOS metals.

  6. CMOS-compatible graphene photodetector covering all optical communication bands

    Pospischil, Andreas; Humer, Markus; Furchi, Marco M.; Bachmann, Dominic; Guider, Romain; Fromherz, Thomas; Mueller, Thomas

    2013-11-01

    Optical interconnects are becoming attractive alternatives to electrical wiring in intra- and interchip communication links. Particularly, the integration with silicon complementary metal-oxide semiconductor (CMOS) technology has received considerable interest because of the ability of cost-effective integration of electronics and optics on a single chip. Although silicon enables the realization of optical waveguides and passive components, the integration of another, optically absorbing, material is required for photodetection. Traditionally, germanium or compound semiconductors are used for this purpose; however, their integration with silicon technology faces major challenges. Recently, graphene emerged as a viable alternative for optoelectronic applications, including photodetection. Here, we demonstrate an ultra-wideband CMOS-compatible photodetector based on graphene. We achieved a multigigahertz operation over all fibre-optic telecommunication bands beyond the wavelength range of strained germanium photodetectors, the responsivity of which is limited by their bandgap. Our work complements the recent demonstration of a CMOS-integrated graphene electro-optical modulator, and paves the way for carbon-based optical interconnects.

  7. Development of CMOS Imager Block for Capsule Endoscope

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  8. CMOS IC design for wireless medical and health care

    Wang, Zhihua; Chen, Hong

    2014-01-01

    This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to tu...

  9. Seamless integration of CMOS and microfluidics using flip chip bonding

    We demonstrate the microassembly of PDMS (polydimethylsiloxane) microfluidics with integrated circuits made in complementary metal-oxide-semiconductor (CMOS) processes. CMOS-sized chips are flip chip bonded to a flexible polyimide printed circuit board (PCB) with commercially available solder paste patterned using a SU-8 epoxy. The average resistance of each flip chip bond is negligible and all connections are electrically isolated. PDMS is attached to the flexible polyimide PCB using a combination of oxygen plasma treatment and chemical bonding with 3-aminopropyltriethoxysilane. The total device has a burst pressure of 175 kPA which is limited by the strength of the flip chip attachment. This technique allows the sensor area of the die to act as the bottom of the microfluidic channel. The SU-8 provides a barrier between the pad ring (electrical interface) and the fluids; post-processing is not required on the CMOS die. This assembly method shows great promise for developing analytic systems which combine the strengths of microelectronics and microfluidics into one device. (paper)

  10. CMOS integration of inkjet-printed graphene for humidity sensing.

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  11. High Q-factor CMOS-MEMS inductor

    Dai, Ching-Liang; Liu, Mao-Chen

    2008-01-01

    This study investigates a high Q-factor spiral inductor fabricated by the CMOS (complementary metal oxide semiconductor) process and a post-process. The spiral inductor is manufactured on silicon substrate using the 0.35 micrometers CMOS process. In order to reduce the substrate loss and enhance the Q-factor of the inductor, silicon substrate under the inductor is removed using a post-process. The post-process uses RIE (reactive ion etching) to etch the sacrificial layer of silicon dioxide, and then TMAH (tetra methyl ammonium hydroxide) is employed to remove the underlying silicon substrate and obtain the suspended spiral inductor. The advantage of the post process is compatible with the CMOS process. The Agilent 8510C network analyzer and a Cascade probe station are used to measure the performances of the spiral inductor. Experiments indicate that the spiral inductor has a Q-factor of 15 at 11 GHz, an inductance of 4 nH at 25.5 GHz and a self-resonance frequency of about 27 GHz.

  12. First result on biased CMOS MAPs-on-diamond devices

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected

  13. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    Kazusuke Maenaka; Kohei Higuchi; Oleg Nizhnik

    2011-01-01

    A 1.1 µW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  14. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    Esposito, M; Anaxagoras, T; Konstantinidis, AC; Zheng, Y.; Speller, RD; Evans, PM; Allinson, NM; Wells, K.

    2014-01-01

    Recently CMOS Active Pixels Sensors (APSs) have become a valuable alternative to amorphous Silicon and Selenium Flat Panel Imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non...

  15. SiGe BiCMOS RF ICs and Components for High Speed Wireless Data Networks

    Svitek, Richard M

    2005-01-01

    The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvem...

  16. Adaptive oxide electronics: A review

    Ha, Sieu D.; Ramanathan, Shriram

    2011-10-01

    Novel information processing techniques are being actively explored to overcome fundamental limitations associated with CMOS scaling. A new paradigm of adaptive electronic devices is emerging that may reshape the frontiers of electronics and enable new modalities. Creating systems that can learn and adapt to various inputs has generally been a complex algorithm problem in information science, albeit with wide-ranging and powerful applications from medical diagnosis to control systems. Recent work in oxide electronics suggests that it may be plausible to implement such systems at the device level, thereby drastically increasing computational density and power efficiency and expanding the potential for electronics beyond Boolean computation. Intriguing possibilities of adaptive electronics include fabrication of devices that mimic human brain functionality: the strengthening and weakening of synapses emulated by electrically, magnetically, thermally, or optically tunable properties of materials.In this review, we detail materials and device physics studies on functional metal oxides that may be utilized for adaptive electronics. It has been shown that properties, such as resistivity, polarization, and magnetization, of many oxides can be modified electrically in a non-volatile manner, suggesting that these materials respond to electrical stimulus similarly as a neural synapse. We discuss what device characteristics will likely be relevant for integration into adaptive platforms and then survey a variety of oxides with respect to these properties, such as, but not limited to, TaOx, SrTiO3, and Bi4-xLaxTi3O12. The physical mechanisms in each case are detailed and analyzed within the framework of adaptive electronics. We then review theoretically formulated and current experimentally realized adaptive devices with functional oxides, such as self-programmable logic and neuromorphic circuits. Finally, we speculate on what advances in materials physics and engineering may

  17. Design, Implementation And Characterization Of Xor Phase Detector For Dpll In 45 Nm Cmos Technology

    Delvadiya Harikrushna I; Mr. Mukesh Tiwari; Jay Karan Singh; Jay Karan Sing

    2011-01-01

    In this paper the implementation of XOR phase detector in 45 nm submicron CMOS technology and it’sCMOS design layout using Microwind 3.1 for Digital Phase Locked Loop in sub-nanometres CMOSTechnology is presented. The input-output transfer characteristic of XOR phase detector is presented. TheCMOS XOR phase detector produces error pulses on both rising and falling edges while the CMOS phasefrequency detector will respond only to positive or negative transitions. XOR phase detector will try to...

  18. Design and tests of offset-compensated in-pixel amplifiers for CMOS pixel sensors

    This paper presents novel in-pixel amplifiers for CMOS pixel sensors. Two kinds of offset-compensated amplifiers allow the sensors to achieve a high signal-to-noise ratio. Based on theoretical analysis, the gain of the input offset-compensated amplifier is less sensitive to threshold voltage variation than the output offset-compensated amplifier. A 12μm pitch CMOS pixel sensor with the input offset-compensated amplifier was therefore designed and fabricated in a 0.13μm CMOS technology. Measurements indicate that the implementation of this amplifier can result in a high signal-to-noise ratio for a CMOS pixel sensor.

  19. CMOS APS 器件及其在星敏感器中的应用%Application of CMOS APS in Star Tracker

    李杰; 刘金国; 刘亚侠; 郝志航

    2004-01-01

    介绍了CMOS有源像元图像传感器(APS)的原理与结构特点,阐述了CMOS APS与CCD比较应用于星敏感器的潜在优势,详细介绍了CMOS图像传感器在星敏感器中的应用现状,并对基于CMOS APS与基于CCD的星敏感器的测量精度结果进行对比,展望了CMOS APS星敏感器的发展前景.

  20. An ultra-low power self-timed column-level ADC for a CMOS pixel sensor based vertex detector

    Zhang, L.; Wang, M.

    2014-11-01

    The International Large Detector (ILD) is a detector concept for the future linear collider experiment. The vertex detector is the key tool to achieve high precision measurements for flavor tagging, which puts stringent requirements on the CMOS pixel sensors. Due to the cooling systems which deteriorate the material budget and increase the multiple scattering, it is important to reduce the power consumption. This paper presents an ultra-low power self-timed column-level ADC for the CMOS pixel sensors, aiming to equip the outer layers of the vertex detector. The ADC was designed to operate in two modes (active and idle) adapted to the low hit density in the outer layers. The architecture employs an enhanced sample-and-hold circuit and a self-timed technique. The total power consumption with a 3-V supply is 225μW during idle mode, which is the most frequent situation. This value rises to 425μW in the case of the active mode. It occupies an area of 35 × 590μm2.

  1. An ultra-low power self-timed column-level ADC for a CMOS pixel sensor based vertex detector

    The International Large Detector (ILD) is a detector concept for the future linear collider experiment. The vertex detector is the key tool to achieve high precision measurements for flavor tagging, which puts stringent requirements on the CMOS pixel sensors. Due to the cooling systems which deteriorate the material budget and increase the multiple scattering, it is important to reduce the power consumption. This paper presents an ultra-low power self-timed column-level ADC for the CMOS pixel sensors, aiming to equip the outer layers of the vertex detector. The ADC was designed to operate in two modes (active and idle) adapted to the low hit density in the outer layers. The architecture employs an enhanced sample-and-hold circuit and a self-timed technique. The total power consumption with a 3-V supply is 225μW during idle mode, which is the most frequent situation. This value rises to 425μW in the case of the active mode. It occupies an area of 35 × 590μm2

  2. Adaptive Lighting

    Petersen, Kjell Yngve; Søndergaard, Karin; Kongshaug, Jesper

    2015-01-01

    Adaptive LightingAdaptive lighting is based on a partial automation of the possibilities to adjust the colour tone and brightness levels of light in order to adapt to people’s needs and desires. IT support is key to the technical developments that afford adaptive control systems. The possibilities offered by adaptive lighting control are created by the ways that the system components, the network and data flow can be coordinated through software so that the dynamic variations are controlled i...

  3. SRAM lifetime improvement by using adaptive proactive reconfiguration

    Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio

    2012-01-01

    Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design strategies at the Nanoscale circuit system level. In this paper we have introduced an adaptive proactive reconfiguration technique that considers the inherent process variability (variability-aware) and BTI aging, and effectively enlarges the SRAM lifetime. Peer Reviewed

  4. Leakage Power Reduction and Analysis of CMOS Sequential Circuits

    M. Janaki Rani

    2012-02-01

    Full Text Available A significant portion of the total power consumption in high performance digital circuits in deep sub micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

  5. Double junction photodiode for X-ray CMOS sensor IC

    A CMOS compatible P+/Nwell/Psub double junction photodiode pixel was proposed, which can efficiently detect fluorescence from CsI(Tl) scintillation in an X-ray sensor. Photoelectric and spectral responses of P+/Nwell, Nwell/Psub and P+/Nwell/Psub photodiodes were analyzed and modeled. Simulation results show P+/Nwell/Psub photodiode has larger photocurrent than P+/Nwell photodiode and Nwell/Psub photodiode, and its spectral response is more in accordance with CsI(Tl) fluorescence spectrum. Improved P+/Nwell/Psub photodiode detecting CsI(Tl) fluorescence was designed in CSMC 0.5 μm CMOS process, CTIA (capacitive transimpedance amplifier) architecture was used to readout photocurrent signal. CMOS X-ray sensor IC prototype contains 8 × 8 pixel array and pixel pitch is 100 × 100 μm2. Testing results show the dark current of the improved P+/Nwell/Psub photodiode (6.5 pA) is less than that of P+/Nwell and P+/Nwell/Psub photodiodes (13 pA and 11 pA respectively). The sensitivity of P+/Nwell/Psub photodiode is about 20 pA/lux under white LED. The spectrum response of P+/Nwell/Psub photodiode ranges from 400 nm to 800 nm with a peak at 532 nm, which is in accordance with the fluorescence spectrum of CsI(Tl) in an indirect X-ray sensor. Preliminary testing results show the sensitivity of X-ray sensor IC under Cu target X-ray is about 0.21 V·m2/W or 5097e−/pixel @ 8.05 keV considering the pixel size, integration time and average energy of X-ray photons. (semiconductor devices)

  6. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

  7. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

    Yin-Shui Xia; Lun-Yao Wang; A. E. A. Almaini

    2005-01-01

    A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. Pspice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.

  8. CMOS instrumentation amplifier with offset cancellation circuitry and high PSRR for low power application

    This paper presents the design and development of a CMOS instrumentation amplifier for biomedical application. The instrumentation amplifier possesses a very high power-supply rejection ratio (PSRR) and is able to operate at single supply voltage for low power application with improved performance compared to existing work. It also has a full CMOS implementation of offset cancellation circuitry. (author)

  9. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  10. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors...

  11. Monolithic CMOS Pixel R&D for the ILC at LBNL

    M. Battaglia; Abrams, G.; Denes, P.; Greiner, L. C.; Hooberman., B; Tompkins, L.; Wieman, H. H.

    2005-01-01

    An R&D program on monolithic CMOS pixel sensors for application at the ILC has been started at LBNL. This program profits of significant synergies with other R&D activities on CMOS pixel sensors. The project activities after the first semester of the R&D program are reviewed.

  12. Parasitic-aware optimization of CMOS RF circuits

    Allstot, David J; Choi, Kiyong

    2007-01-01

    Dedication. Contributing Authors. Preface. Part I: Background on Parasitic-Aware Optimization. 1: Introduction. 1. Introduction. 2. Overview of Wireless Transceivers. 3. Outline of the Book. 2: Modeling of On-Chip Passive and Active Components. 1. Monolithic Inductors. 2. Monolithic Varactors. 3. MOS Transistors. 3: Parasitic-Aware Optimization. 1. Gradient Decent Optimization. 2. Simulated Annealing. 3. Simulated Annealing with Tunneling Process. 4. Genetic Algorithm (GA). 5. Particle Swarm Optimization (PSO). 6. Post PVT Variation Optimization. Part II: Optimization of CMOS RF Circuits. 4: O

  13. Solar Battery Charger in CMOS 0.25 um Technology

    Tao Wang; Chang-Ching Huang; Tian-Jen Wang

    2014-01-01

    A solar cell powered Li-ion battery charger in CMOS 0.25um is proposed. The solar battery charger consists of a DC/DC boost converter and a battery charger. The voltage generated by a solar cell is up converted from 0.65V to 1.8V, which is used as the VDD of the battery charger.  In this way, the solar battery charger automatically converts solar energy to electricity and stores it directly to a Li-ion rechargeable battery. In this system, a super capacitor is needed as a charge buffer betwee...

  14. Free form CMOS electronics: Physically flexible and stretchable

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  15. Measurements with a CMOS pixel sensor in magnetic fields

    Boer, W. de; Bartsch, V.; Bol, J.; Dierlamm, A.; Grigoriev, E.; Hauler, F.; Herz, O.; Jungermann, L. E-mail: levin.jungermann@cern.ch; Koppenhoefer, M.; Sopczak, A.; Schneider, Th

    2002-07-11

    CMOS technique, which is the standard process used by most of the semiconductor factories worldwide, allows the production of both cheap and highly integrated sensors. The prototypes MIMOSA -I and MIMOSA-II were designed by the IReS-LEPSI collaboration in order to investigate the potential of this new technique for charged particle tracking (Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking, LEPSI, IN2P3, Strasbourg, France). For this purpose it is necessary to study the effects of magnetic fields as they appear in high-energy physics on these sensors.

  16. Displacement damage effects in pinned photodiode CMOS image sensors

    This paper investigates the effects of displacement damage in Pinned Photodiode (PPD) CMOS Image Sensors (CIS) using proton and neutron irradiations. The DDD ranges from 12 TeV/g to 1.2 * 106 TeV/g. Particle fluence up to 5 * 1014 n.cm-2 is investigated to observe electro-optic degradation in harsh environments. The dark current is also investigated and it would appear that it is possible to use the dark current spectroscopy in PPD CIS. The dark current random telegraph signal is also observed and characterized using the maximum transition amplitude. (authors)

  17. CMOS RF circuit design for reliability and variability

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  18. CMOS technology and current-feedback op-amps

    Bruun, Erik

    1993-01-01

    solutions providing improved input characteristics are presented. Problems related to the achievable output voltage swing are examined, and circuits which may be used to achieve a near rail to rail output swing are proposed. It is concluded that mere translations of bipolar circuit designs yield a rather......Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  19. Performance Analysis of Visible Light Communication Using CMOS Sensors.

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  20. Design procedure for optimizing CMOS low noise operational amplifiers

    Li Zhiyuan; Ye Yizheng; Ma Jianguo

    2009-01-01

    This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

  1. Monolithic CMOS-MEMS resonant beams for ultrasensitive mass detection

    Verd Martorell, Jaume

    2008-01-01

    Estructures ressonants en forma de biga (p.e. ponts o palanques) són molt interessants com a element transductor en sensors físics, químics i biològics basats en sistemes micro-/nanoelectromecànics (M-/NEMS) degut a la seva simplicitat, al gran rang de dominis que poden sensar, i a la seva extremada alta sensibilitat. Aquesta tesis està focalitzada en el disseny, fabricació i caracterització de CMOS-MEMS monolítics basats en bigues ressonants a escala sub-micromètrica per a la seva utilitzaci...

  2. Development of high gain photodiode array based on commercial CMOS process

    Developing photodiodes in commercial CMOS process and integrating it with readout electronics without any process modification involves formidable challenges. Due to low resistivity of the wafer used in commercial CMOS process, the junction capacitance per area of the PN junction is quite large thereby limiting the size of the active area of the photodiode leading to degradation in high speed response. On the contrary, the sensitivity and quantum efficiency of the optical detector tends to improve with increase in active area of the detector. The major challenge in designing high gain photodiode in sub micron CMOS technology is to avoid the premature perimeter edge breakdown or the soft breakdown. This paper reports two different design approaches of high gain photodiode arrays in commercial 0.35 um CMOS technology and HV CMOS process

  3. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Castro, Xitzel Sanchez; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  4. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  5. The Dexela 2923 CMOS X-ray detector: A flat panel detector based on CMOS active pixel sensors for medical imaging applications

    Konstantinidis, A. C.; Szafraniec, M. B.; Speller, R.D.; Olivo, A.

    2012-01-01

    Complementary metal-oxide-semiconductors (CMOS) active pixel sensors (APS) have been introduced recently in many scientific applications. This work reports on the performance (in terms of signal and noise transfer) of an X-ray detector that uses a novel CMOS APS which was developed for medical X-ray imaging applications. For a full evaluation of the detector's performance, electro-optical and X-ray characterizations were carried out. The former included measuring read noise, full well capacit...

  6. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems. PMID:24353389

  7. Adaptive skills

    Staša Stropnik; Jana Kodrič

    2013-01-01

    Adaptive skills are defined as a collection of conceptual, social and practical skills that are learned by people in order to function in their everyday lives. They include an individual's ability to adapt to and manage her or his surroundings to effectively function and meet social or community expectations. Good adaptive skills promote individual's independence in different environments, whereas poorly developed adaptive skills are connected to individual's dependency and with g...

  8. Tracking burst patterns in hippocampal cultures with high-density CMOS-MEAs

    Gandolfo, M.; Maccione, A.; Tedesco, M.; Martinoia, S.; Berdondini, L.

    2010-10-01

    In this work, we investigate the spontaneous bursting behaviour expressed by in vitro hippocampal networks by using a high-resolution CMOS-based microelectrode array (MEA), featuring 4096 electrodes, inter-electrode spacing of 21 µm and temporal resolution of 130 µs. In particular, we report an original development of an adapted analysis method enabling us to investigate spatial and temporal patterns of activity and the interplay between successive network bursts (NBs). We first defined and detected NBs, and then, we analysed the spatial and temporal behaviour of these events with an algorithm based on the centre of activity trajectory. We further refined the analysis by using a technique derived from statistical mechanics, capable of distinguishing the two main phases of NBs, i.e. (i) a propagating and (ii) a reverberating phase, and by classifying the trajectory patterns. Finally, this methodology was applied to signal representations based on spike detection, i.e. the instantaneous firing rate, and directly based on voltage-coded raw data, i.e. activity movies. Results highlight the potentialities of this approach to investigate fundamental issues on spontaneous neuronal dynamics and suggest the hypothesis that neurons operate in a sort of 'team' to the perpetuation of the transmission of the same information.

  9. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs). PMID:24301987

  10. An ebCMOS camera system for marine bioluminescence observation: The LuSEApher prototype

    The ebCMOS camera, called LuSEApher, is a marine bioluminescence recorder device adapted to extreme low light level. This prototype is based on the skeleton of the LUSIPHER camera system originally developed for fluorescence imaging. It has been installed at 2500 m depth off the Mediterranean shore on the site of the ANTARES neutrino telescope. The LuSEApher camera is mounted on the Instrumented Interface Module connected to the ANTARES network for environmental science purposes (European Seas Observatory Network). The LuSEApher is a self-triggered photo detection system with photon counting ability. The presentation of the device is given and its performances such as the single photon reconstruction, noise performances and trigger strategy are presented. The first recorded movies of bioluminescence are analyzed. To our knowledge, those types of events have never been obtained with such a sensitivity and such a frame rate. We believe that this camera concept could open a new window on bioluminescence studies in the deep sea.

  11. An ebCMOS camera system for marine bioluminescence observation: The LuSEApher prototype

    Dominjon, A., E-mail: a.dominjon@ipnl.in2p3.fr [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Ageron, M. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Billault, M.; Brunner, J. [CNRS/IN2P3, Centre de Physique des Particules de Marseille, Marseille, F-13288 (France); Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Calabria, P. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Chabanat, E. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France); Universite de Lyon, Universite Lyon 1, Lyon F-69003 (France); Chaize, D.; Doan, Q.T.; Guerin, C.; Houles, J.; Vagneron, L. [CNRS/IN2P3, Institut de Physique Nucleaire de Lyon, Villeurbanne F-69622 (France)

    2012-12-11

    The ebCMOS camera, called LuSEApher, is a marine bioluminescence recorder device adapted to extreme low light level. This prototype is based on the skeleton of the LUSIPHER camera system originally developed for fluorescence imaging. It has been installed at 2500 m depth off the Mediterranean shore on the site of the ANTARES neutrino telescope. The LuSEApher camera is mounted on the Instrumented Interface Module connected to the ANTARES network for environmental science purposes (European Seas Observatory Network). The LuSEApher is a self-triggered photo detection system with photon counting ability. The presentation of the device is given and its performances such as the single photon reconstruction, noise performances and trigger strategy are presented. The first recorded movies of bioluminescence are analyzed. To our knowledge, those types of events have never been obtained with such a sensitivity and such a frame rate. We believe that this camera concept could open a new window on bioluminescence studies in the deep sea.

  12. A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast transient response

    Han, Wang; Maomao, Sun

    2014-04-01

    This paper presents a low-dropout regulator (LDO) for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59° phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6-μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113 μA. The line regulation and load regulation are improved to 0.1 mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.

  13. Single donor electronics and quantum functionalities with advanced CMOS technology

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  14. A CMOS Imager with Focal Plane Compression using Predictive Coding

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  15. Illumination robust change detection with CMOS imaging sensors

    Rengarajan, Vijay; Gupta, Sheetal B.; Rajagopalan, A. N.; Seetharaman, Guna

    2015-05-01

    Change detection between two images in the presence of degradations is an important problem in the computer vision community, more so for the aerial scenario which is particularly challenging. Cameras mounted on moving platforms such as aircrafts or drones are subject to general six-dimensional motion as the motion is not restricted to a single plane. With CMOS cameras increasingly in vogue due to their low power consumption, the inevitability of rolling-shutter (RS) effect adds to the challenge. This is caused by sequential exposure of rows in CMOS cameras unlike conventional global shutter cameras where all pixels are exposed simultaneously. The RS effect is particularly pronounced in aerial imaging since each row of the imaging sensor is likely to experience a different motion. For fast-moving platforms, the problem is further compounded since the rows are also affected by motion blur. Moreover, since the two images are shot at different times, illumination differences are common. In this paper, we propose a unified computational framework that elegantly exploits the scarcity constraint to deal with the problem of change detection in images degraded by RS effect, motion blur as well as non-global illumination differences. We formulate an optimization problem where each row of the distorted image is approximated as a weighted sum of the corresponding rows in warped versions of the reference image due to camera motion within the exposure period to account for geometric as well as photometric differences. The method has been validated on both synthetic and real data.

  16. Smart CMOS image sensor for lightning detection and imaging.

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach. PMID:23458812

  17. CMOS mm-wave transceivers for Gbps wireless communication

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  18. 3D integration of sub-surface photonics with CMOS

    Jalali, Bahram; Indukuri, Tejaswi; Koonath, Prakash

    2006-02-01

    The integration of photonics and electronics on a single silicon substrate requires technologies that can add optical functionalities without significantly sacrificing valuable wafer area. To this end, we have developed an innovative fabrication process, called SIMOX 3-D Sculpting, that enables monolithic optoelectronic integration in a manner that does not compromise the economics of CMOS manufacturing. In this technique, photonic devices are realized in subsurface silicon layers that are separated from the surface silicon layer by an intervening SiO II layer. The surface silicon layer may then be utilized for electronic circuitry. SIMOX 3-D sculpting involves (1) the implantation of oxygen ions into a patterned silicon substrate followed by (2) high temperature anneal to create buried waveguide-based photonic devices. This process has produced subterranean microresonators with unloaded quality factors of 8000 and extinction ratios >20dB. On the surface silicon layers, MOS transistor structures have been fabricated. The small cross-sectional area of the waveguides lends itself to the realization of nonlinear optical devices. We have previously demonstrated spectral broadening and continuum generation in silicon waveguides utilizing Kerr optical nonlinearity. This may be combined with microresonator filters for on-chip supercontiuum generation and spectral carving. The monolithic integration of CMOS circuits and optical modulators with such multi-wavelength sources represent an exciting avenue for silicon photonics.

  19. Electronic-photonic integrated circuits on the CMOS platform

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  20. A charge pump for driving CMOS active pixel reset

    XU Jiang-tao; LI Bin-qiao; YAO Su-ying; SUN Zhong-yan

    2009-01-01

    To overcome the limitation of low image signal swing range and long reset time in four transistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open perfor-mance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage tipple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is eliminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 ~ 106 pixeis.

  1. High-stage analog accumulator for TDI CMOS image sensors

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  2. Single donor electronics and quantum functionalities with advanced CMOS technology

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature. (topical review)

  3. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  4. Performance of Very Small Robotic Fish Equipped with CMOS Camera

    Yang Zhao

    2015-10-01

    Full Text Available Underwater robots are often used to investigate marine animals. Ideally, such robots should be in the shape of fish so that they can easily go unnoticed by aquatic animals. In addition, lacking a screw propeller, a robotic fish would be less likely to become entangled in algae and other plants. However, although such robots have been developed, their swimming speed is significantly lower than that of real fish. Since to carry out a survey of actual fish a robotic fish would be required to follow them, it is necessary to improve the performance of the propulsion system. In the present study, a small robotic fish (SAPPA was manufactured and its propulsive performance was evaluated. SAPPA was developed to swim in bodies of freshwater such as rivers, and was equipped with a small CMOS camera with a wide-angle lens in order to photograph live fish. The maximum swimming speed of the robot was determined to be 111 mm/s, and its turning radius was 125 mm. Its power consumption was as low as 1.82 W. During trials, SAPPA succeeded in recognizing a goldfish and capturing an image of it using its CMOS camera.

  5. CMOS low data rate imaging method based on compressed sensing

    Xiao, Long-long; Liu, Kun; Han, Da-peng

    2012-07-01

    Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

  6. CMOS-TDI detector technology for reconnaissance application

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  7. NV-CMOS HD camera for day/night imaging

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  8. Adaptive Lighting

    Petersen, Kjell Yngve; Søndergaard, Karin; Kongshaug, Jesper

    2015-01-01

    Adaptive Lighting Adaptive lighting is based on a partial automation of the possibilities to adjust the colour tone and brightness levels of light in order to adapt to people’s needs and desires. IT support is key to the technical developments that afford adaptive control systems. The possibilities...... offered by adaptive lighting control are created by the ways that the system components, the network and data flow can be coordinated through software so that the dynamic variations are controlled in ways that meaningfully adapt according to people’s situations and design intentions. This book discusses...... distributed differently into an architectural body. We also examine what might occur when light is dynamic and able to change colour, intensity and direction, and when it is adaptive and can be brought into interaction with its surroundings. In short, what happens to an architectural space when artificial...

  9. A radiation hardened hybrid spintronic/CMOS nonvolatile unit using magnetic tunnel junctions

    Conventional complementary metal-oxide semiconductor (CMOS)-based devices are approaching their physical limits to continue the Moore's law. Spintronic devices that exploit the intrinsic spin freedom of the electron in addition to its fundamental electrical charge show great potential in nanoscale technology nodes. In particular, hybrid spintronic/CMOS technology based on magnetic tunnel junctions (MTJs) has been considered as a very promising approach thanks to the high speed, low power, good scalability and full compatibility of MTJs with CMOS technology. It is also considered as a potential technology for high-reliability electronics due to the intrinsic hardness to the radiation effect of the MTJs. However, hybrid spintronic/CMOS circuits are still vulnerable to the radiation effect due to their CMOS peripheral circuits (e.g. write/read circuits) during the access operations. In this paper, we propose a radiation hardened hybrid spintronic/CMOS nonvolatile unit to address this issue effectively. By using a physics-based pMTJ compact model and a 40 nm CMOS design kit, hybrid simulations are performed to demonstrate the performance of the proposed unit. The simulation results show that the proposed unit is quite robust against radiation effects with less overhead in terms of hardware area and power consumption compared with the previous works. (paper)

  10. High-performance VGA-resolution digital color CMOS imager

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  11. Optimization of ultra-low-power CMOS transistors

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  12. SiGe HBT BiCMOS technology for millimeter-wave applications

    Joseph, Alvin; Dahlstrom, Mattias; Liu, Qizhi; Orner, Bradley; Liu, Xuefeng; Sheridan, David; Rassel, Robert; Dunn, Jim; Ahlgren, David

    2006-03-01

    We present the advances in Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT) and BiCMOS technology capabilities to address the emerging millimetre-wave (mmWave) applications. SiGe HBTs with f MAX performance reaching 350 GHz that are integrated with advanced CMOS and high-frequency passives is envisioned to allow better integration capability for mmWave applications. This capability of SiGe HBT BiCMOS technology is discussed relative to an InP HBT technology.

  13. Development of high-performances monolithic CMOS detectors for space applications

    Larnaudie, Franck; Vignon, Bruno; Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Martin-Gonthier, Philippe; Corbière, Franck; Basolo, Stephanie

    2002-01-01

    This paper describes the development of a 750x750 pixels CMOS image sensor for star tracker applications. A first demonstrator of such a star tracker called SSM star tracker built around a 512x512 detector has been recently developed and proves the feasibility of such instrument. In order to take fully advantage of the CMOS image sensor step, the 750x750 device called SSM CMOS detector which will take part of the final star tracker, can be considered as a major technical breakthrough that...

  14. Developing CMOS Camera and USB Device Drivers in Linux 2.6.32

    CH. P. N. S. Sujitha

    2013-07-01

    Full Text Available —This paper proposes CMOS camera and USB device drivers implementation on S3C2440 using LINUX 2.6.32. The CMOS camera driver is used for video acquisition applications, which implements image-sensor technology and USB driver is used for data acquisition applications, establishes communication between host computer and a number of peripheral devices. OV9650 CMOS camera is implemented in linux 2.6.32, uses V4L2 protocol for complying. Similarly USB device in LINUX kernel uses struct urb structure to communicate with all USB devices

  15. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    Zujun Wang; Shaoyan Huang; Minbo Liu; Zhigang Xiao; Baoping He; Zhibin Yao; Jiangkun Sheng

    2014-01-01

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN)...

  16. Polarisation analysing complementary metal-oxide semiconductor image sensor in 65-nm standard CMOS technology

    N. Wakama

    2013-09-01

    Full Text Available In the present study, the authors demonstrate a complementary metal-oxide semiconductor (CMOS image sensor implemented with on-chip polarisers using 65-nm standard CMOS technology. The polariser is composed of metal wire grids made of metal wires fabricated by the CMOS process. An extinction ratio of 18.8 dB was obtained for a single pixel with an on-chip polariser, where the line/space widths have the finest pitch obtainable by 65-nm technology. Electrical crosstalk between pixels is reduced by over 25% using a guard ring structure. Polarisation imaging by the sensor was also performed.

  17. Reset noise reduction through column-level feedback reset in CMOS image sensors

    A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6 μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination. (semiconductor integrated circuits)

  18. Reset noise reduction through column-level feedback reset in CMOS image sensors*

    Li Binqiao; Xu Jiangtao; Xie Shuang; Sun Zhongyan

    2011-01-01

    A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18 μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

  19. A CMOS current preamplifier and shaper with 50Ω line driver for liquid argon preshower

    In the field of liquid argon calorimetry for the LHC detector program, a CMOS ''current conveyor'' preamplifier was cold preshower. It is an improved version of the ICON circuit which had been formerly designed by the RD2 collaboration. This paper also presents a CMOS linear output buffer, featuring a dynamic range close to ±2V on a 50Ω load, for a 21 mW power dissipation at 77K. Furthermore a biquadratic 7 MHz bandpass filter was developed, based on a high speed rail to rail CMOS operational amplifier. It is meant to be the filter placed at the output of the ICON preamplifier

  20. Mutation analysis of the c-mos proto-oncogene in human ovarian teratomas.

    de Foy, K. A.; Gayther, S A; Colledge, W.H.; Crockett, S; Scott, I V; Evans, M.J.; Ponder, B A

    1998-01-01

    Female transgenic mice lacking a functional c-mos proto-oncogene develop ovarian teratomas, indicating that c-mos may behave as a tumour-suppressor gene for this type of tumour. We have analysed the entire coding region of the c-MOS gene in a series of human ovarian teratomas to determine whether there are any cancer-causing alterations. DNA from twenty teratomas was analysed by single-strand conformational analysis (SSCA) and heteroduplex analysis (HA) to screen for somatic and germline muta...

  1. A new interpolating method based on the variation of spectra energy using CMOS array

    Tianjin Tang; Xiangqun Cao; Hongqiu Chen; Bin Lin

    2005-01-01

    @@ A new interpolating method to enhance the resolution of gratings using complementary metal-oxide semiconductor (CMOS) according to the variation of some specified spectral light intensities during the motion of scale grating in a periodic separation is proposed. CMOS image sensor (pixel array 648 × 488) was also introduced as receiving device and its stability was verified experimentally. Many factors in the experiment were analyzed theoretically and contrasted with experiment. The advantages of this novel method were featured by CMOS and the specified spectral variation of the energy distribution was discussed.

  2. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  3. Adaptive Lighting

    Petersen, Kjell Yngve; Søndergaard, Karin; Kongshaug, Jesper

    2015-01-01

    Adaptive Lighting Adaptive lighting is based on a partial automation of the possibilities to adjust the colour tone and brightness levels of light in order to adapt to people’s needs and desires. IT support is key to the technical developments that afford adaptive control systems. The possibilities...... offered by adaptive lighting control are created by the ways that the system components, the network and data flow can be coordinated through software so that the dynamic variations are controlled in ways that meaningfully adapt according to people’s situations and design intentions. This book discusses...... the investigations of lighting scenarios carried out in two test installations: White Cube and White Box. The test installations are discussed as large-scale experiential instruments. In these test installations we examine what could potentially occur when light using LED technology is integrated and...

  4. Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

    White, Mark; MacNeal, Kristen; Cooper, Mark

    2012-01-01

    NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

  5. Small-Scale CMOS Pseudo SRAM Module Design

    李昀; 刘振宇; 韩月秋

    2004-01-01

    An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.

  6. Design of a CMOS multi-mode GNSS receiver VCO

    Long Qiang; Zhuang Yiqi; Yin Yue; Li Zhenrong

    2012-01-01

    A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multimode global navigation satellite system (GNSS) application,which adopts sigma-delta fractional-N technology in the synthesizer,is presented.The structure is selected to optimize the frequency coverage and tuning linearity,based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells,which cover the global positioning system (GPS) and Beidou (BD) bands.The VCO implemented in the 0.18 μm CMOS process can cover the GPS L1,BD B1,B2 and B3 bands with sufficient margin,and exhibits low phase noise by using this tuning curve linearization technique.The equalized Kvco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

  7. An Approach for Self-Timed Synchronous CMOS Circuit Design

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  8. Novel CMOS readout techniques for uncooled pyroelectric IR FPA

    Sun, Tai-Ping; Chin, Yuan-Lung; Chung, Wen-Yaw; Hsiung, Shen-Kan; Chou, Jung-Chuan

    1998-09-01

    Based on the application of the source follower per detector (SFD) input biasing technique, a new redout structure for the IR focal-plane-array (FPA), called the variable gain source follower per detector (VGSFD) is proposed and analyzed. The readout circuit of VGSFD of a unit cell of pyroelectric sensor under investigation, is composed of a source follower per detector circuit, high gain amplifier, and the reset switch. The VGSFD readout chip has been designed in 0.5 micrometers double-poly-double-metal n-well CMOS technology in various formats from 8 by 8 to 128 by 128. The experimental 8 by 8 VGSFD measurement results of the fabricated readout chip at room temperature have successfully verified both the readout function and performance. The high gain, low power, high sensitivity readout performances are achieved in a 50 by 50 micrometers (superscript 2) pixel size.

  9. CMOS APS detector characterization for quantitative X-ray imaging

    Endrizzi, Marco, E-mail: m.endrizzi@ucl.ac.uk [Dipartimento di Fisica, Università di Siena, Via Roma 56, 53100 Siena (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy); Oliva, Piernicola [Dipartimento di Chimica e Farmacia, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Golosio, Bruno [Sezione di Matematica, Fisica e Ingegneria dell' Informazione, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Delogu, Pasquale [Dipartimento di Fisica “E. Fermi”, Università di Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy)

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11–30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  10. New CMOS Compatible Platforms for Integrated Nonlinear Optical Signal Processing

    Moss, D J

    2014-01-01

    Nonlinear photonic chips have succeeded in generating and processing signals all-optically with performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. This paper reviews some of the recent achievements in CMOS-compatible platforms for nonlinear optics, focusing on amorphous silicon and Hydex glass, highlighting their potential future impact as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  11. AN IMPROVED ECG SIGNAL ACQUISITION SYSTEM THROUGH CMOS TECHNOLOGY

    Mrs. Jyoti Athiya

    2012-03-01

    Full Text Available This paper presents the design and realization of low power, high gain PC based system for ECG and data acquisition of a patient’s heart condition. The advantage of this system is the use of standard CMOS process which will reduce the complexity and cost of the manufacturer. The system consists of three subsystems- Operational Amplifier based Pre-amplifier, ADC and USB interface device. High gain around 85 dB, low power dissipation of typically 0.683 mW and 61.5 degree phase-margin for stable closed loop operations wereachieved. All design and simulation were done using Tanner Tool 0.5 μm technology.

  12. Voltage-to-frequency converters CMOS design and implementation

    Azcona Murillo, Cristina; Pueyo, Santiago Celma

    2013-01-01

    This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

  13. A low-power CMOS frequency synthesizer for GPS receivers

    A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm2. (semiconductor integrated circuits)

  14. A photonics design tool for advanced CMOS nodes

    Alloatti, Luca; Stojanovic, Vladimir; Popovic, Milos; Ram, Rajeev Jagga

    2015-01-01

    Recently, we have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigor that is embodied in the 10000 to 50000 design rules that these designs must comply within advanced CMOS manufacturing. Here, we present a photonic design automation (PDA) tool which allows automatic generation of layouts without design-rule violations. Our tool is written in SKILL, the native language of the mainstream electric design automation (EDA) software, Cadence. This allows seamless integration of photonic and electronic design in a single environment. The tool leverages intuitive photonic layer definitions, allowing the designer to focus on the physical properties rather than on technology-dependent details. Removal of design-rule violations - based on Manhattan discretization, Boolean and sizing operations - occurs during data preparation from the initial photonic layers to the final mask...

  15. Analysis of the Noise Characteristics of CMOS Current Conveyors

    Bruun, Erik

    1997-01-01

    The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor is...... described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches to an...... optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors...

  16. CMOS Silicon-on-Sapphire RF Tunable Matching Networks

    Chamseddine Ahmad

    2006-01-01

    Full Text Available This paper describes the design and optimization of an RF tunable network capable of matching highly mismatched loads to 50 at 1.9 GHz. Tuning was achieved using switched capacitors with low-loss, single-transistor switches. Simulations show that the performance of the matching network depends strongly on the switch performances and on the inductor losses. A 0.5 m silicon-on-sapphire (SOS CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process. The matching network provides very good matching for inductive loads, and acceptable matching for highly capacitive loads. A 1 dB compression point greater than dBm was obtained for a wide range of load impedances.

  17. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    Yue Xu

    2011-06-01

    Full Text Available An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature.

  18. A CMOS low-noise instrumentation amplifier using chopper modulation

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...... band hereby ensuring overall low noise performance. The resulting equivalent input referred noise is approximately 7 nV/rootHz for a chopping frequency of 20 kHz. The amplifier operates from a modest supply voltage of 1.8 V, drawing 136 muA of current thus consuming 245 muW of power. The gain is 72.5 d...

  19. Adaptive skills

    Staša Stropnik

    2013-02-01

    Full Text Available Adaptive skills are defined as a collection of conceptual, social and practical skills that are learned by people in order to function in their everyday lives. They include an individual's ability to adapt to and manage her or his surroundings to effectively function and meet social or community expectations. Good adaptive skills promote individual's independence in different environments, whereas poorly developed adaptive skills are connected to individual's dependency and with greater need for control and help with everyday tasks. Assessment of adaptive skills is often connected to assessment of intellectual disability, due to the reason that the diagnosis of intellectual disability includes lower levels of achievements on standardized tests of intellectual abilities as well as important deficits in adaptive skills. Assessment of adaptive behavior is a part of standard assessment battery with children and adults with different problems, disorders or disabilities that affect their everyday functioning. This contribution also presents psychometric tools most regularly used for assessment of adaptive skills and characteristics of adaptive skills with individual clinical groups.

  20. ADAPT Dataset

    National Aeronautics and Space Administration — Advanced Diagnostics and Prognostics Testbed (ADAPT) Project Lead: Scott Poll Subject Fault diagnosis in electrical power systems Description The Advanced...

  1. Fully integrated current-mode CMOS gated baseline restorer circuits

    Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of ±40 microA for the gated integrator circuits, ±100 microA for the CFD constant fraction comparator circuit, and ± 160 microA for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at sub millivolt levels, and arming comparator threshold is maintained at a 0--0.48 V level under on-board DAC control

  2. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis.

    Hageman, Kristin N; Kalayjian, Zaven K; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A; Fridman, Gene Y; Dai, Chenkai; Pouliquen, Philippe O; Georgiou, Julio; Della Santina, Charles C; Andreou, Andreas G

    2016-04-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 (°)/s for the MVP2 and 2.0-14.2 (°)/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  3. Development of radiation hard CMOS active pixel sensors for HL-LHC

    Pernegger, Heinz

    2016-07-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  4. Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

    Li-Shu, Wu; Yan, Zhao; Hong-Chang, Shen; You-Tao, Zhang; Tang-Sheng, Chen

    2016-06-01

    In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal–oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits.

  5. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

    In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

  6. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    National Aeronautics and Space Administration — This Phase I SBIR effort initiates development of a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at...

  7. CMOS-MEMS Microgravity Accelerometer with High-Precision DC Response Project

    National Aeronautics and Space Administration — In this Phase II SBIR project a high-sensitivity low-noise all-silicon CMOS-MEMS accelerometer for quasi-steady measurements of accelerations at sub 1 micro-g...

  8. Sinusoidal Frequency Doublers Circuit With Low Voltage + 1.5 Volt CMOS Inverter

    Bancha Burapattanasiri

    2009-01-01

    This paper is present sinusoidal frequency doublers circuit with low voltage + 1.5 volt CMOS inverter. Main structure of circuit has three parts that is CMOS inverter circuit, differential amplifier circuit, and square root circuit. This circuit has designed to receive input voltage and give output voltage use few MOS transistor, easy to understand, non complex of circuit, high precision, low error and low power. The Simulation of circuit has MOS transistor functional in active and saturation...

  9. Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

    Makoto Ishida; Kazuaki Sawada; Hidekuni Takao; Jong-Wan Kim

    2007-01-01

    This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essenti...

  10. Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

    Bennett, K.; Lala, P. K.; Busaba, F.

    1997-01-01

    Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

  11. CMOS detectors for space applications: from R&D to operational program with large volume foundry

    Martin-Gonthier, Philippe; Magnan, Pierre; Corbière, Franck; Rolando, Sébastien; Saint-Pé, Olivier; Breart de Boisanger, M.; Larnaudie, Franck

    2010-01-01

    Nowadays, CMOS image sensors are widely considered for space applications. The use of CIS (CMOS Image sensor) processes has significantly enhanced their performances such as dark current, quantum efficiency and conversion gain. However, in order to fulfil specific space mission requirements, dedicated research and development work has to be performed to address specific detector performance issues. This is especially the case for dynamic range improvement through output voltage swing optim...

  12. Monte Carlo Study of the Dosimetry of Small-Photon Beams Using CMOS Active Pixel Sensors

    Jimenez Spang, F.

    2014-01-01

    Stereotactic radiosurgery is an increasingly common treatment modality that uses very small photon fields. This technique imposes high dosimetric standards and complexities that remain unsolved. In this work the dosimetric performance of CMOS active pixel sensors is presented for the measurement of small-photons beams. A novel CMOS active pixel sensor called Vanilla developed for scientific applications was used. The detector is an array of 520 × 520 pixels on a 25 μm pitch which allows up to...

  13. NEMS/CMOS sensor for monitoring deposition rates in stencil lithography

    Sansa, Marc; Arcamone, Julien; Verd, Jaume; Uranga, Arantxa; Abadal, Gabriel; Núria, Barniol; Savu, Veronica; van den Boogaart, Marc; Brugger, Jürgen; Perez-Murano, Francesc

    2009-01-01

    A nanoelectromechanical mass sensor is used to characterize material deposition rates in stencil lithography. The material flux through micron size apertures is mapped with high spatial (below 1 μm) and deposition rate (below 10 pm/s) resolutions by displacing the stencil apertures over the sensor. The sensor is based on a resonating metallic beam (with submicron size width and thickness) monolithically integrated with a CMOS circuit, resulting in a CMOS/NEMS self-oscillator. The sensor is us...

  14. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Amine Bermak; Milin Zhang

    2010-01-01

    Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression...

  15. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Kiyotaka Sasagawa; Jun Ohta; Takashi Tokuda; Toshihiko Noda

    2010-01-01

    In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS) image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-...

  16. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Shoji Kawahito; Shinya Itoh; Satoshi Aoyama; Sungho Suh

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effec...

  17. Analysis and Optimization of Noise Response for Low-Noise CMOS Image Sensors

    Martin-Gonthier, Philippe; Molina, Romain; Cervantes, Paola; Magnan, Pierre

    2012-01-01

    CMOS image sensors are nowadays widely used in imaging applications and particularly in low light flux applications. This is really possible thanks to a reduction of noise obtained, among others, by the use of pinned photodiode associated with a Correlated Double Sampling readout. It reveals new noise sources which become the major contributors. This paper presents noise measurements on low-noise CMOS image sensor. Image sensor noise is analyzed and optimization is done in order to reach an i...

  18. Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors

    Martin-Gonthier, Philippe; Havard, E.; Magnan, Pierre

    2010-01-01

    Interface and near oxide traps in small gate area MOS transistors (gate area ,1 mm2) lead to RTS noise which implies the emergence of noisy pixels in CMOS image sensors. To reduce this noise, two simple and efficient layout techniques of custom transistors have been imagined. These techniques have been successfully implemented in an image sensor test chip fabricated in a 0.35 mm CMOS image sensor process. Experimental results demonstrate a significant reduction of the noisy pixels for the ...

  19. Design of low-power K-band circuits in CMOS technology

    Ali, Mohammed Kamal Abdelrahman

    2015-01-01

    Die Entwicklung von Millimeterwellen-Transceivern auf Basis moderner CMOS-Technologien steht derzeit weltweit im Fokus von Wissenschaft und Forschung. Dabei sind insbesondere Schaltungen für die ISM-Bänder bei 24 GHz bzw. 60 GHz von Interesse. Beim Entwurf von CMOS-Schaltungen zur Erzeugung und Umsetzung von Frequenzen in diesen Frequenzbereichen ergeben sich zahlreiche unterschiedliche Problemstellungen. So ist einerseits die Performance von spannungsgesteuerten Oszillatoren (VCOs) bei Mill...

  20. A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing

    Wu, Xinyu; Saxena, Vishal; Zhu, Kehan

    2015-01-01

    Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigur...

  1. A Study of a Versatile Low Power CMOS Pulse Generator for Ultra Wideband Radios

    Marsden, Kevin Matthew

    2004-01-01

    Ultra-Wideband (UWB) technologies are at the forefront of wireless communications, offering the possibility to provide extremely high data rate wireless solutions. In addition to high data rate applications, UWB technologies also offer an extremely low cost alternative for many low data rate systems. In this thesis, we describe the design of a CMOS pulse generator for impulse based UWB systems. The structure of our pulse generator is based on the topology of a single tap CMOS power amplifi...

  2. A low-noise CMOS front-end for TOF-PET

    Rolo, M. D.; Alves, L. N.; Martins, E. V.; Rivetti, A.; Santos, M. B.; Varela, J

    2011-01-01

    An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder ...

  3. CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

    Ekavut Kritchanchai; Jiann-Shiun Yuan

    2015-01-01

    Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation...

  4. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    Benoit, M; de Mendizabal, J. Bilbao; Chen, H; Chen, K; Di Bello, F.A; Ferrere, D; Golling, T; Gonzalez-Sevilla, S; Iacobucci, G; Lanni, F; Liu, H; Meng, L; Miucci, A; Muenstermann, D; Nessi, M; Peric, I; Rimoldi, M; Ristic, B; Pinto, M. Vicente Barrero; Vossebeld, J; Weber, M; Wu, W; Xu, L

    2016-01-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  5. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  6. CMOS-sensors for energy-resolved X-ray imaging

    Doering, D.; Amar-Youcef, S.; Baudot, J.; Deveaux, M.; Dulinski, W.; Kachel, M.; Linnik, B.; Müntz, C.; Stroth, Joachim

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ``color sensitive" X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors.

  7. CMOS-sensors for energy-resolved X-ray imaging

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

  8. Effects of Fiber-optic Plates on Image Quality of CMOS X-ray Detectors

    Radiation damage and its effects on image quality of Complementary metal-oxide-semiconductor (CMOS) devices have also been reported by previous studies. In this regard, most CMOS sensor manufacturers usually employ a fiber-optic plate (FOP) bonded to the CMOS photodiode array. In this configuration, the FOP layer absorbs un-attenuated x-ray photons through an overlaid scintillator; otherwise the un-attenuated photons might be absorbed within the CMOS photodiode array directly. Therefore, it is important to select an optimal thickness of an FOP layer for the long-term use of CMOS sensors providing high-quality images. By comparing the image qualities of the CMOS detector measured without and with FOP, the effects of FOP on the imaging system have been investigated for various x-ray spectra. Measurements showed that the FOP degraded the x-ray sensitivity and resolving power, whereas it enhanced noise properties by absorbing un-attenuated x-ray photons. As a result, the use of FOP enhances the DQE performance which mainly governs x-ray image quality. However, for a low exposure imaging, the use of FOP may not be appropriate because it reduces the light photon transmittance by ∼55% which implies that the image quality could be easily affected by additional electronics noise rather than quantum noise. In this regard, the use of FOP may be more appropriate for industrial applications in which irradiation condition is harsh

  9. Effects of Fiber-optic Plates on Image Quality of CMOS X-ray Detectors

    Yun, Seungman; Han, Jong Chul; Kim, Ho Kyung [Pusan National Univ., Busan (Korea, Republic of)

    2014-05-15

    Radiation damage and its effects on image quality of Complementary metal-oxide-semiconductor (CMOS) devices have also been reported by previous studies. In this regard, most CMOS sensor manufacturers usually employ a fiber-optic plate (FOP) bonded to the CMOS photodiode array. In this configuration, the FOP layer absorbs un-attenuated x-ray photons through an overlaid scintillator; otherwise the un-attenuated photons might be absorbed within the CMOS photodiode array directly. Therefore, it is important to select an optimal thickness of an FOP layer for the long-term use of CMOS sensors providing high-quality images. By comparing the image qualities of the CMOS detector measured without and with FOP, the effects of FOP on the imaging system have been investigated for various x-ray spectra. Measurements showed that the FOP degraded the x-ray sensitivity and resolving power, whereas it enhanced noise properties by absorbing un-attenuated x-ray photons. As a result, the use of FOP enhances the DQE performance which mainly governs x-ray image quality. However, for a low exposure imaging, the use of FOP may not be appropriate because it reduces the light photon transmittance by ∼55% which implies that the image quality could be easily affected by additional electronics noise rather than quantum noise. In this regard, the use of FOP may be more appropriate for industrial applications in which irradiation condition is harsh.

  10. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Sreenivasa Rao.Ijjada

    2012-06-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

  11. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Sreenivasa Rao.Ijjada

    2011-07-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.

  12. An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

    Guo, Zhiyong; Li, Qiang; Liu, Haiqi; Yan, Bo; Li, Guangjun

    2011-06-01

    This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), ? input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

  13. Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

    Mahmou, Raja

    2012-01-01

    The present work consists of designing a Single Balanced Mixer(SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated. Keywords: SBM Mixer, Radio Frequency, 65 nm CMOS Technology, Non-Linearity, Power Consumption.

  14. Ambiguous Adaptation

    Møller Larsen, Marcus; Lyngsie, Jacob

    We investigate why some exchange relationships terminate prematurely. We argue that investments in informal governance structures induce premature termination in relationships already governed by formal contracts. The formalized adaptive behavior of formal governance structures and the flexible and...... reciprocal adaptation of informal governance structure create ambiguity in situations of contingencies, which, subsequently, increases the likelihood of premature relationship termination. Using a large sample of exchange relationships in the global service provider industry, we find support for a hypothesis...

  15. Strategic Adaptation

    Andersen, Torben Juul

    2015-01-01

    This article provides an overview of theoretical contributions that have influenced the discourse around strategic adaptation including contingency perspectives, strategic fit reasoning, decision structure, information processing, corporate entrepreneurship, and strategy process. The related...... concepts of strategic renewal, dynamic managerial capabilities, dynamic capabilities, and strategic response capabilities are discussed and contextualized against strategic responsiveness. The insights derived from this article are used to outline the contours of a dynamic process of strategic adaptation...

  16. Is adaptation. Truly an adaptation? Is adaptation. Truly an adaptation?

    Thais Flores Nogueira Diniz

    2008-04-01

    Full Text Available The article begins by historicizing film adaptation from the arrival of cinema, pointing out the many theoretical approaches under which the process has been seen: from the concept of “the same story told in a different medium” to a comprehensible definition such as “the process through which works can be transformed, forming an intersection of textual surfaces, quotations, conflations and inversions of other texts”. To illustrate this new concept, the article discusses Spike Jonze’s film Adaptation. according to James Naremore’s proposal which considers the study of adaptation as part of a general theory of repetition, joined with the study of recycling, remaking, and every form of retelling. The film deals with the attempt by the scriptwriter Charles Kaufman, cast by Nicholas Cage, to adapt/translate a non-fictional book to the cinema, but ends up with a kind of film which is by no means what it intended to be: a film of action in the model of Hollywood productions. During the process of creation, Charles and his twin brother, Donald, undergo a series of adventures involving some real persons from the world of film, the author and the protagonist of the book, all of them turning into fictional characters in the film. In the film, adaptation then signifies something different from itstraditional meaning. The article begins by historicizing film adaptation from the arrival of cinema, pointing out the many theoretical approaches under which the process has been seen: from the concept of “the same story told in a different medium” to a comprehensible definition such as “the process through which works can be transformed, forming an intersection of textual surfaces, quotations, conflations and inversions of other texts”. To illustrate this new concept, the article discusses Spike Jonze’s film Adaptation. according to James Naremore’s proposal which considers the study of adaptation as part of a general theory of repetition

  17. High resolution, high bandwidth global shutter CMOS area scan sensors

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  18. Capacitively Coupled CMOS VCSEL Driver Circuits for Optical Communication

    Kozlov, Victor

    This thesis presents the analysis, design and implementation of a common-cathode capacitively-coupled VCSEL driver in 65nm CMOS intended for short-reach optical interconnects. The driver consists of an AC-coupled high-frequency path and a low-frequency path that provides DC signal components. By increasing the low-frequency path bandwidth by 10 times compared to previous AC-coupled drivers allowed the on-chip coupling capacitor to be reduced to 2.1pF, occupying 3 times less area than prior art. The driver introduces capacitively-coupled two-tap emphasis to equalize the VCSEL's optical response. The VCSEL was modulated with an OMA of up to 5.1dBm and an ER of 9dB, measuring an RMS jitter of 5ps at a data rate of 15Gb/s, which represents the highest OMA and ER achieved in high-speed anode-driving LDDs. The driver could be programmed for a low-power mode, outputting 2.3dBm OMA at power consumption of only 30mW, corresponding to an energy efficiency of 2pJ/bit.

  19. Passive radiation detection using optically active CMOS sensors

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  20. CMOS solid state photomultipliers for ultra-low light levels

    Johnson, Erik B.; Stapels, Christopher J.; Chen, Xaio Jie; Whitney, Chad; Chapman, Eric C.; Alberghini, Guy; Rines, Rich; Augustine, Frank; Christian, James

    2011-05-01

    Detection of single photons is crucial for a number of applications. Geiger photodiodes (GPD) provide large gains with an insignificant amount of multiplication noise exclusively from the diode. When the GPD is operated above the reverse bias breakdown voltage, the diode can avalanche due to charged pairs generated from random noise (typically thermal) or incident photons. The GPD is a binary device, as only one photon is needed to trigger an avalanche, regardless of the number of incident photons. A solid-state photomultiplier (SSPM) is an array of GPDs, and the output of the SSPM is proportional to the incident light intensity, providing a replacement for photomultiplier tubes. We have developed CMOS SSPMs using a commercial fabrication process for a myriad of applications. We present results on the operation of these devices for low intensity light pulses. The data analysis provides a measured of the junction capacitance (~150 fF), which affects the rise time (~2 ns), the fall time (~32 ns), and gain (>106). Multipliers for the cross talk and after pulsing are given, and a consistent picture within the theory of operation of the expected dark current and photodetection efficiency is demonstrate. Enhancement of the detection efficiency with respect to the quantum efficiency at unity gain for shallow UV photons is measured, indicating an effect due to fringe fields within the diode structure. The signal and noise terms have been deconvolved from each other, providing the fundamental model for characterizing the behavior at low-light intensities.

  1. Neutron-induced soft errors in CMOS circuits

    The subject of this thesis is a systematic study of soft errors occurring in CMOS integrated circuits when being exposed to radiation. The vast majority of commercial circuits operate in the natural environment ranging from the sea level to aircraft flight altitudes (less than 20 km), where the errors are caused mainly by interaction of atmospheric neutrons with silicon. Initially, the soft error rate (SER) of a static memory was measured for supply voltages from 2V to 5V when irradiated by 14 MeV and 100 MeV neutrons. Increased error rate due to the decreased supply voltage has been identified as a potential hazard for operation of future low-voltage circuits. A novel methodology was proposed for accurate SER characterization of a manufacturing process and it was validated by measurements on a 0.6 μm process and 100 MeV neutrons. The methodology can be applied to the prediction of SER in the natural environment

  2. A CMOS ASIC Design for SiPM Arrays.

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  3. Optimization of ultra-low-power CMOS transistors

    Stockinger, M

    2000-01-01

    chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/mu m. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 mu m and 0.1 mu m devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for its superior drive performance are given. It is compared to already known device structures and practical alternatives are suggested with respect to its manufacturability. In a second optimization study the gate delay times of complete CMOS inverters are minimized. Both the doping profiles of the NMOS and PMOS transistors are optimized at the same time which results again in PCD devices. The inverter speeds are improved by 54 % and 97 % for the 0.25 mu m and 0.1 mu m devices, respectively. Ultra-low-power CMO...

  4. A CMOS Amperometric System for Multi-Neurotransmitter Detection.

    Massicotte, Genevieve; Carrara, Sandro; Di Micheli, Giovanni; Sawan, Mohamad

    2016-06-01

    In vivo multi-target and selective concentration monitoring of neurotransmitters can help to unravel the brain chemical complex signaling interplay. This paper presents a dedicated integrated potentiostat transducer circuit and its selective electrode interface. A custom 2-electrode time-based potentiostat circuit was fabricated with 0.13 μm CMOS technology and provides a wide dynamic input current range of 20 pA to 600 nA with 56 μ W, for a minimum sampling frequency of 1.25 kHz. A multi-working electrode chip is functionalized with carbon nanotubes (CNT)-based chemical coatings that offer high sensitivity and selectivity towards electroactive dopamine and non-electroactive glutamate. The prototype was experimentally tested with different concentrations levels of both neurotransmitter types, and results were similar to measurements with a commercially available potentiostat. This paper validates the functionality of the proposed biosensor, and demonstrates its potential for the selective detection of a large number of neurochemicals. PMID:26761882

  5. Smart CMOS sensor for wideband laser threat detection

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  6. Charge collection studies in irradiated HV-CMOS particle detectors

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  7. CMOS Image Sensor with a Built-in Lane Detector.

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  8. CMOS Image Sensor with a Built-in Lane Detector

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  9. A hierarchical approach to test generation for CMOS VLSI circuits

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  10. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  11. A CMOS pressure sensor tag chip for passive wireless applications.

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  12. MEMS Very Low Capacitive Pressure Sensor Based on CMOS Process

    The CMOS standard process with advantage of simplicity in term of design and fabrication process compatibility has triggered the invention of MEMS very low capacitive pressure sensor, (MEMS-VLCPS). In this paper the development of the whole structure of MEMS-VLCPS that involves the design simulation, fabrication and testing is described. The novelty of this work lies in the design and fabrication process itself. A new technique in fabricating thin sensor membrane of VLCPS using seal-off techniques is also presented. The physical structure of the membrane consists of parallel plate. The top plate acts as the flexible electrode membrane and the bottom plate acts as the counter electrode membrane. Both plates are separated by absolute air gap with fixed end at both sides. As a result, it was found that the etch-opening holes of 0.8 μm and seal-off thickness of 4000 Angstrom gave the optimum sealing surface. The percentage of relative capacitance change is extracted from the reference capacitance measurement. Air gap thickness of 0.3 μm gives the highest percentage of PRCC showing that smaller air gap thickness provides a larger change in capacitance value. (author)

  13. CMOS indoor light energy harvesting system for wireless sensing applications

    Ferreira Carvalho, Carlos Manuel

    2016-01-01

    This book discusses in detail the CMOS implementation of energy harvesting.  The authors describe an integrated, indoor light energy harvesting system, based on a controller circuit that dynamically and automatically adjusts its operation to meet the actual light circumstances of the environment where the system is placed.  The system is intended to power a sensor node, enabling an autonomous wireless sensor network (WSN). Although designed to cope with indoor light levels, the system is also able to work with higher levels, making it an all-round light energy harvesting system.  The discussion includes experimental data obtained from an integrated manufactured prototype, which in conjunction with a photovoltaic (PV) cell, serves as a proof of concept of the desired energy harvesting system.  ·         Discusses several energy sources which can be used to power energy harvesting systems and includes an overview of PV cell technologies  ·         Includes an introduction to voltage step-...

  14. Radiation-hardened bulk Si-gate CMOS microprocessor family

    RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 106 rads (Si) and transient upset hardness of 5 x 108 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C2L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

  15. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination.

    Rufino, Giancarlo; Grassi, Michele

    2009-01-01

    This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively. PMID:22408538

  16. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  17. Implementation of high-speed–low-power adaptive finite impulse response filter with novel architecture

    Manish Jaiswal

    2015-03-01

    Full Text Available An energy efficient high-speed adaptive finite impulse response filter with novel architecture is developed. Synthesis results along with novel architecture on different complementary metal–oxide semiconductor (CMOS families are presented. Analysis is performed using Artix-7, Spartan-6 and Virtex-4 for most popular adaptive least mean square filter for different orders such as N = 8, 16, 32. The presented work is done using MATLAB (2013b and Xilinx (14.2. From the synthesis results, it can be found that CMOS (28 nm achieves the lowest power and critical path delay compared to others, and thus proves its efficiency in terms of energy. Different parameters are considered such as look up tables and input–output blocks, along with their optimised results.

  18. Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS

    Long, Cheng; Yu, Zhu; Kai, Zhu; Chixiao, Chen; Junyan, Ren

    2013-10-01

    A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.

  19. Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

    Bonacini, Sandro; Kloukinas, Kostas

    2007-01-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

  20. Adaptive test

    Kjeldsen, Lars Peter; Eriksen, Mette Rose

    2010-01-01

    Artikelen er en evaluering af de adaptive tests, som blev indført i folkeskolen. Artiklen sætter særligt fokus på evaluering i folkeskolen, herunder bidrager den med vejledning til evaluering, evalueringsværktøjer og fagspecifkt evalueringsmateriale.......Artikelen er en evaluering af de adaptive tests, som blev indført i folkeskolen. Artiklen sætter særligt fokus på evaluering i folkeskolen, herunder bidrager den med vejledning til evaluering, evalueringsværktøjer og fagspecifkt evalueringsmateriale....

  1. Performance of commercial CMOS cameras for high-speed multicolor photometry

    Pokhvala, S M; Reshetnyk, V M

    2013-01-01

    We present some results of testing of commercial color CMOS cameras for astronomical applications. CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in CMOS sensors is close to the Johnson BVR system. We demonstrate transformation from the Bayer color system to the Johnson one. Our photometric measurements with color CMOS cameras coupled to small telescopes (11 - 30 inch) reveal that in video mode stars up to V $\\sim$ 9 can be shot at 24 frames per second. Using a high-speed CMOS camera with short exposure times (10 - 20 ms) we can perform an imaging mode called "lucky imaging". We can pick out high quality frames and combine them into a single image using "shift-and-add" technique. This allows us obtain an image with much higher resolution than would be possible shooting a single image with long exposure. For image selection we use the Strehl-selection method. We demonstrates advan...

  2. A high frame rate, 16 million pixels, radiation hard CMOS sensor

    Guerrini, N.; Turchetta, R.; Van Hoften, G.; Henderson, R.; McMullan, G.; Faruqi, A. R.

    2011-03-01

    CMOS sensors provide the possibility of designing detectors for a large variety of applications with all the benefits and flexibility of the widely used CMOS process. In this paper we describe a novel CMOS sensor designed for transmission electron microscopy. The overall design consists of a large 61 × 63 mm2 silicon area containing 16 million pixels arranged in a 4K × 4K array, with radiation hard geometry. All this is combined with a very fast readout, the possibility of region of interest (ROI) readout, pixel binning with consequent frame rate increase and a dynamic range close to 12 bits. The high frame rate has been achieved using 32 parallel analogue outputs each one operating at up to 20 MHz. Binning of pixels can be controlled externally and the flexibility of the design allows several possibilities, such as 2 × 2 or 4 × 4 binning. Other binning configurations where the number of rows and the number of columns are not equal, such as 2 × 1 or 2 × 4, are also possible. Having control of the CMOS design allowed us to optimise the pixel design, in particular with regard to its radiation hardness, and to make optimum choices in the design of other regions of the final sensor. An early prototype was also designed with a variety of geometries in order to optimise the readout structure and these are presented. The sensor was manufactured in a 0.35 μm standard CMOS process.

  3. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    Zujun Wang

    2014-07-01

    Full Text Available The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD, dark signal spike, dark signal non-uniformity (DSNU, noise (VN, saturation output signal voltage (VS, and dynamic range (DR versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  4. CMOS图像传感器及其应用%CMOS Image Sensor and Its Application

    谈新权; 何永泰

    2001-01-01

    CMOS图像传感器是近年来市场上出现的一种新的摄像器件。文中对CMOS图像传感器与CCD图像传感器作了比较。分析了CMOS像传感器的工作原理及其优越的性能。提供了CMOS像传感器的应用实例。CMOS成像器在红外成像领域具有广阔的应用前景。%CMOS image sensor is a new solid-state pickup element.This article compares the performance of a CMOS image sensor with CCD image sensor.The operation principle and significant performance advantages of CMOS image sensor are analysed.An application example of CMOS image sensor is given in the article.CMOS image sensor has the prospects of application in the infrared imaging.

  5. Testability of VLSI (Very Large Scale Integration) leakage faults in CMOS (Complementary Metal Oxide Semiconductor)

    Malaiya, Y. K.; Su, S. Y. H.

    1983-09-01

    With the advent of VLSI (Very Large Scale Integration), the importance of CMOS (Complementary Metal Oxide Semiconductor) technology has increased. CMOS offers some very significant advantages over NMOS, and has emerged very competitive. Therefore, testability of CMOS devices is of considerable importance. CMOS devices exhibit some failure modes which are not adequately represented by the classical stuck-at fault model. A new fault model is introduced here to represent such faults. Leakage faults are specifically examined in this report, such faults increase the static supply current (which is ordinarily quite low) substantially. A leakage testing experiment consists of applying different vectors to the circuit, and in each case measuring the static supply current. This experimentally obtained data is then analyzed to obtain fault-related information. Leakage testing offers extra testability without any additional pins. It can detect some faults which cannot be detected by the conventional testing. Test generation for several basic CMOS structures is considered. Correspondence between leakage testing and conventional testing is studied. Two methods for analyzing experimental data are presented. Available experimental data was analyzed to obtain statistical information.

  6. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD), dark signal spike, dark signal non-uniformity (DSNU), noise (VN), saturation output signal voltage (VS), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike

  7. An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

    Ashish Raghuwanshi

    2013-09-01

    Full Text Available One of the key issues in CMOS circuit design is the large amount of power being dissipated in the circuits. Energy recovering circuitry based on adiabatic principles is a relatively new technique used to implement low power dissipating circuits. By recycling the charge at capacitive nodes in the circuit, adiabatic logic families can achieve very low power dissipation. In this paper we had design and simulate the Inverter, Two-Input Nand gate, Two-Input Nor gate, Two-Input Xor gate, 2:1 Multiplexer on the basis of CMOS Logic and Adiabatic Switching logic using 180nm CMOS technology in Cadence design environment. Two adiabatic families are used in this work, Oneis the Positive Feedback Adiabatic Logic (PFAL and the other is the Efficient Charge Recovery Logic (ECRL Finally, the analysis of the average dynamic power dissipation with respect to the frequency and the load capacitance was done to show the amount of power dissipated by the CMOS, PFAL and ECRL family. The results shows that power saving of adiabatic circuit can reach more than 90% as compare to conventional static CMOS logic

  8. Ultrastretchable and flexible copper interconnect-based smart patch for adaptive thermotherapy

    Hussain, Aftab M.

    2014-12-03

    Unprecedented 800% stretchable, non-polymeric, widely used, low-cost, naturally rigid, metallic thin-film copper (Cu)-based flexible and non-invasive, spatially tunable, mobile thermal patch with wireless controllability, adaptability (tunes the amount of heat based on the temperature of the swollen portion), reusability, and affordability due to low-cost complementary metal oxide semiconductor (CMOS) compatible integration. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. Electronic dosimetry and neutron metrology by CMOS active pixel sensor

    This work aims at demonstrating the possibility to use active pixel sensors as operational neutron dosemeters. To do so, the sensor that has been used has to be γ-transparent and to be able to detect neutrons on a wide energy range with a high detection efficiency. The response of the device, made of the CMOS sensor MIMOSA-5 and a converter in front of the sensor (polyethylene for fast neutron detection and 10B for thermal neutron detection), has been compared with Monte Carlo simulations carried out with MCNPX and GEANT4. These codes have been before-hand validated to check they can be used properly for our application. Experiments to characterize the sensor have been performed at IPHC and at IRSN/LMDN (Cadarache). The results of the sensor irradiation to photon sources and mixed field (241AmBe source) show the γ-transparency of the sensor by applying an appropriate threshold on the deposited energy (around 100 keV). The associated detection efficiency is satisfactory with a value of 10-3, in good agreement with MCNPX and GEANT4. Other features of the device have been tested with the same source, like the angular response. The last part of this work deals with the detection of thermal neutrons (eV-neutrons). Assays have been done in Cadarache (IRSN) with a 252Cf source moderated with heavy water (with and without cadmium shell). Results asserted a very high detection efficiency (up to 6*10-3 for a pure 10B converter) in good agreement with GEANT4. (author)

  10. Silicides and germanides for nano-CMOS applications

    Kittl, J.A. [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)], E-mail: kittlj@imec.be; Opsomer, K.; Torregiani, C.; Demeurisse, C.; Mertens, S.; Brunco, D.P.; Van Dal, M.J.H.; Lauwers, A. [IMEC, Kapeldreef 75, 3001 Leuven (Belgium)

    2008-12-05

    An overview of silicides and germanides for nano-CMOS applications is presented. The historical evolution describing the migration from the use of Ti silicide to Co silicide to Ni silicide as contacting material is first discussed. These changes in silicide material were mainly motivated by the inability to form the target low resistivity silicide phase in small structures due to low nucleation density. This issue was found first for the low resistivity C54 TiSi{sub 2} at linewidths below 200 nm and later for the low resistivity CoSi{sub 2}, at linewidths below 40 nm. A detailed description of scalability and thermal stability issues for NiSi is then presented. No nucleation issues were found in small structures for NiSi, which grows by diffusion or interface limited kinetics with Ni as main moving species. However, silicidation can be excessive in small structures due to Ni diffusion from surrounding areas, resulting in thicker films than targeted in small devices. This can be controlled by using a silicidation process with two rapid thermal processing steps, the first one to control the amount of Ni reacted and the second one to convert the silicide to the target low resistivity monosilicide phase. One of the main issues for applications of NiSi is its low thermal stability: thin NiSi films agglomerate at relatively low temperatures. The process window and thermal stability of Ni and Pt-based films reacted with Si, Si:Ge and Si:C substrates is reviewed. Addition of Ge is shown to degrade thermal stability while addition of C or Pt improves it. Contact resistivity considerations and implementation of dual band-edge silicides are discussed, as well as promising results for the extension of Ni-based silicides to future nodes. Finally a brief overview of germanides is presented discussing NiGe and PdGe as main candidates.

  11. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  12. Compact CMOS Camera Demonstrator (C3D) for Ukube-1

    Harriss, R. D.; Holland, A. D.; Barber, S. J.; Karout, S.; Burgon, R.; Dryer, B. J.; Murray, N. J.; Hall, D. J.; Smith, P. H.; Grieg, T.; Tutt, J. H.; Endicott, J.; Jerram, P.; Morris, D.; Robbins, M.; Prevost, V.; Holland, K.

    2011-09-01

    The Open University, in collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space Agency's UKube-1 pilot Cubesat programme. Cubesat payloads offer a unique opportunity to rapidly build and fly space hardware for minimal cost, providing easy access to the space environment. Based around the e2v 1.3 MPixel 0.18 micron process eye-on-Si CMOS devices, the instrument consists of a radiation characterisation imager as well as a narrow field imager (NFI) and a wide field imager (WFI). The narrow and wide field imagers are expected to achieve resolutions of 25 m and 350 m respectively from a 650 km orbit, providing sufficient swathe width to view the southern UK with the WFI and London with the NFI. The radiation characterisation experiment has been designed to verify and reinforce ground based testing that has been conducted on the e2v eye-on-Si family of devices and includes TEC temperature control circuitry as well as RADFET in-orbit dosimetry. Of particular interest are SEU and SEL effects. The novel instrument design allows for a wide range of capabilities within highly constrained mass, power and space budgets providing a model for future use on similarly constrained missions, such as planetary rovers. Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.

  13. sCMOS detector for imaging VNIR spectrometry

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  14. A CMOS-logic-based reactor instrumentation system

    The paper describes a Control and Instrumentation (C and I) system for nuclear reactors. The project approach to design was established at the outset so that all organizations conformed to a nationally applied and audited quality assurance standard; those engaged in setting design objectives and subsequent assessment/justification were different from those involved in detailed design of the C and I equipment and the on-line test equipment. The design was undertaken in three separate sequential stages and each organization worked to written design guidelines. In the equipment design, a standard 'building block' technique was adopted so that a wide range of measurements for reactor safety equipment could be provided from standard plug-in cards and modules fitted in rugged purpose-designed racks. CMOS (Complementary Metal Oxide Semiconductor) digitally based equipment was selected for this application after extensive evaluation of other technologies. The racks contain all the electronics so that sensors are just passive components, i.e. there are no driver circuits in the containment area. Analogue signals from sensors are immediately converted to digital words and all subsequent processing or trip functions are performed digitally, in some cases by microprocessors. Where microprocessors are used, they are always dedicated to a single-channel function and software is written so that it is simple and checkable. The availability of data as digital words allows in-situ automatic testing of all cards during normal operation by on-line test equipment which can also perform 'active' tests on particular channels by controlling test signal generators built into all channels. Interlocks prevent active testing of more than one subsystem at a time. A particular system is described which is arranged as four identical redundant subsystems and one set of on-line test equipment, but this is only one of many possible arrangements

  15. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    Olesen, Ole

    1997-01-01

    digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures...

  16. Designing of RF Single Balanced Mixer with a 65 nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

    Raja Mahmou

    2012-01-01

    Full Text Available The present work consists of designing a Single Balanced Mixer (SBM with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

  17. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p/sup +/n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience.

  18. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p+n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  19. Noise Eliminating Technologies in CMOS Image Sensors%CMOS图像传感器的消噪技术

    梁红玉; 朱宇明; 徐宏; 白培康

    2000-01-01

    Aim To introduce the noise eliminating technologies in CMOS image sensors. Methods The advantages and disadvantages of CMOS image sensors and CCD image sensors are compared. The methods of the noise eliminating technologies of CMOS image sensors are analyzed. The actuality and trend of development are introduced. Results At present these technologies can eliminate efficiently noises and improve signal noise rate. Conclusion The development trend of the noise eliminating technologies of CMOS image sensors is foreseen. Key words: % 目的 介绍 CMOS 图像传感器的消噪技术. 方法 比较了 CMOS 图像传感器与 CCD 图像传感器的优缺点, 分析了 CMOS 图像传感器消噪技术的方法, 介绍了其研制现状及发展趋势. 结果 目前采用的消噪技术有效地降低了噪声, 提高了信噪比. 结论 预见了 CMOS 图像传感器消噪技术的发展趋势.

  20. An approach to the optical interconnect made in standard CMOS process

    Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

    2009-05-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  1. An approach to the optical interconnect made in standard CMOS process

    Yu Changliang; Mao Luhong; Xiao Xindong; Xie Sheng; Zhang Shilin

    2009-01-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide,metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  2. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System.

    Rae, Bruce R; Muir, Keith R; Gong, Zheng; McKendry, Jonathan; Girkin, John M; Gu, Erdan; Renshaw, David; Dawson, Martin D; Henderson, Robert K

    2009-01-01

    We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

  3. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    Martin D. Dawson

    2009-11-01

    Full Text Available We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM. This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented.

  4. Analysis and Design of Monolithic Inductors in Sub-micron CMOS

    Fallesen, Carsten; Jørgensen, Allan

    1997-01-01

    In the last few years the CMOS processes have gone into deep sub-micron channel lengths. This means that it is now possible to make GHz applications in CMOS. In analog GHz applications it is often necessary to have access to inductors. This report describes the development of a physical model of...... the planar inductors used in sub-micron CMOS. The model developed should be ofsuch a quality that it can be used for even very demanding circuits. The result of the model should be useable in all the normal circuit simulators used today. The model should furthermore be very fast in order to be useable...... for optimization. To verify the model more than 40 inductors have been produced and their performance have been measured. The produced inductors sweep a number of design parameters of the inductors, in order to get a realistic dataset. The produced inductors have inductances values of 2 nH to 10 n...

  5. TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

    Buckland, Matthew Daniel

    2016-01-01

    The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

  6. 2D and 3D CMOS MAPS with high performance pixel-level signal processing

    Traversi, Gianluca, E-mail: gianluca.traversi@unibg.i [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Gaioni, Luigi; Manghisoni, Massimo [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Ratti, Lodovico [University of Pavia and INFN Pavia (Italy); Re, Valerio [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy)

    2011-02-01

    Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

  7. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  8. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  9. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  10. A novel monolithic ultraviolet image sensor based on a standard CMOS process

    Li Guike; Feng Peng; Wu Nanjian

    2011-01-01

    We present a monolithic ultraviolet (UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists ofa CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16 × 16 image sensor prototype chip is implemented in a 0.18 μm standard CMOS logic process.The pixel and image sensor were measured.Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

  11. High efficiency grating couplers based on shared process with CMOS MOSFETs

    Qiu Chao; Sheng Zhen; Li Le; Albert Pang; Wu Ai-Min; Wang Xi; Zou Shi-Chang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers.In this work,a high-efficiency and complementary metal-oxide-semiconductor (CMOS) process compatible grating coupler is proposed.The poly-Si layer used as a gate in the CMOS metal-oxide-semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler,which greatly enhances its coupling efficiency.With optimal structure parameters,a coupling efficiency can reach as high as ~ 70% at a wavelength of 1550 nm as indicated by simulation.From the angle of fabrication,all masks and etching steps are shared between MOSFETs and grating couplers,-thereby making the high performance grating couplers easily integrated with CMOS circuits.Fabrication errors such as alignment shift are also simulated,showing that the device is quite tolerant in fabrication.

  12. Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE

    Mugdha Sathe

    2014-07-01

    Full Text Available According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.

  13. A flexible mixed-signal/RF CMOS technology for implantable electronics applications

    A novel post-CMOS fabrication process has been developed to transform a 0.18 µm 1P6M mixed-signal/RF CMOS (complementary metal oxide semiconductor)-integrated circuit chips fabricated on an 8 inch SOI (silicon-on-insulator) wafer into flexible devices sandwiched between biocompatible material (10 µm parylene-C on both sides in this case) and enables future implementation of implantable and fully integrated electronic devices. The functionality of the flexible integrated circuits is demonstrated by a low phase noise RF CMOS VCO (voltage-controlled oscillator) circuit in a ring oscillator configuration that operates at a few hundred MHz to GHz. We report here the associated post-processing technology to make these flexible IC chips and the characterization of both MOS transistors and the demonstration circuit on the flexible IC chip under bending stresses.

  14. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

    Vilella, E.; Benoit, M.; Casanova, R.; Casse, G.; Ferrere, D.; Iacobucci, G.; Peric, I.; Vossebeld, J.

    2016-01-01

    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

  15. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  16. The evaluation system of the 2-D scanning mirror based on CMOS sensor

    Zeng, Gui-ying; Xie, Yuan; Chen, Jin-xing

    2010-10-01

    The high precision two-dimension scanning control technique is being developed for the next geosynchronous satellites FY-4 satellites which is using the three-axis stabilization stages. How to evaluate the point and scanning precision of the scanning mirror is one of the most important technologies. This paper describes the optoelectronic measure method based on CMOS sensors to evaluate the point and scanning precision of the scanning mirror in the laboratory, which is a 2-D dynamic angle measurement system. Some technologies, such as the sup-pixel orientation technology and the CMOS ROI technology, are used in the measurement system. The research shows that the angle measurement system based on IBIS-6600CMOS sensors can attain the 20°× 20° field of view, 2" accuracy, and 1Kframes/s speed. But the system is sensitive to the environment and it can only be worked in the laboratory.

  17. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  18. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  19. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process. PMID:27337723

  20. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-01

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process. PMID:25782697